From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85856C001B0 for ; Mon, 24 Jul 2023 11:36:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229573AbjGXLgJ (ORCPT ); Mon, 24 Jul 2023 07:36:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229578AbjGXLgI (ORCPT ); Mon, 24 Jul 2023 07:36:08 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E39E10E5 for ; Mon, 24 Jul 2023 04:35:42 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-666e6ecb52dso2254151b3a.2 for ; Mon, 24 Jul 2023 04:35:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690198529; x=1690803329; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=Nq+WD11NKB4CXcEv93Ud41HBi4eLx3VHmopZE3v/plY=; b=okTJNX3NPbF3G51qRtyVNKm80OBvG3dKzI7rkFmxSlzP7OmN8SBEt0He0rbvd+Xtgo YN3Dbhtl0gVz2j6iwSJqKapELXo6vXO/EIOR2hVulgnstfUGiPvWIq/e0uMuI29MWUAW Z63Ns4Xq4nFfNhI28HDB3iSoynEGn45tB9U+aKR2/GDO9L7jnSuCcCqEprW07yvGd88x x0JUivRn6QOJdXPaWfSJYvroU/jsKVopHdiJBSepYJ+xRraEesE5hTKHS6mK11hgvwOy wxabIlMSJMnvxUTxLmOFnOCbLqePa+oq5KX3kmtAFz85ORGYoLPS+UwjPaBNPSAHTR0t nh3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690198529; x=1690803329; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Nq+WD11NKB4CXcEv93Ud41HBi4eLx3VHmopZE3v/plY=; b=HafuuAmM4UYZZX/LhT9I/dcqEeguifYSV2qihGvEraWh7BWXjxwJeLv4aczgg9eyUW ba6kdmx7wZPYoPpP/DXe8T1Ypj7NSvkFUBfcqCCpL2PTE047AFy35ts+u7slAFC0s8M8 dcfmPzYnXtze6jsX2XRwAjT9MKycl916PCXrIGmlkyll6h/ngu9Pe/dCepPgI6s6HMy8 CRebkDe122jhyKILj5muEUoXyTBfovfVqNBJ3BOvI8yM32jOB11yyeL58GuYfAUSfP6U LMkWuabk50edyQMsU6GIOlh9ekI8upCrVMcsEG+k2VtDXFzB5aKcchTvM0sevZoOTSaI m6ng== X-Gm-Message-State: ABy/qLY4xhKWyAyHe+GrmM/3kVMVEtejp35VOLW1ICSHlPj6R689fDxE lzTi69EJ3eXe295rgiOHxRtJ X-Google-Smtp-Source: APBJJlGj/DRjzrBVCUXmiE8BzEgzvxUx4ah3hIYdCVLFv2yCQuRG9vnvJiRkhR1pRC/961sFgsf9XQ== X-Received: by 2002:a05:6a20:13da:b0:138:92ef:78f9 with SMTP id ho26-20020a056a2013da00b0013892ef78f9mr4638511pzc.6.1690198529261; Mon, 24 Jul 2023 04:35:29 -0700 (PDT) Received: from thinkpad ([117.206.118.29]) by smtp.gmail.com with ESMTPSA id r2-20020a170902be0200b001b85bb5fd77sm8665833pls.119.2023.07.24.04.35.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 04:35:28 -0700 (PDT) Date: Mon, 24 Jul 2023 17:05:21 +0530 From: Manivannan Sadhasivam To: Yoshihiro Shimoda Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, marek.vasut+renesas@gmail.com, fancer.lancer@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v18 11/20] PCI: dwc: Add EDMA_UNROLL capability flag Message-ID: <20230724113521.GJ6291@thinkpad> References: <20230721074452.65545-1-yoshihiro.shimoda.uh@renesas.com> <20230721074452.65545-12-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230721074452.65545-12-yoshihiro.shimoda.uh@renesas.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Jul 21, 2023 at 04:44:43PM +0900, Yoshihiro Shimoda wrote: > Renesas R-Car Gen4 PCIe controllers have an unexpected register value on > the dbi+0x97b register. So, add a new capability flag "EDMA_UNROLL" s/in the dbi+0x97b/in the eDMA CTRL > which would force the unrolled eDMA mapping for the problematic device. > > Suggested-by: Serge Semin > Signed-off-by: Yoshihiro Shimoda Reviewed-by: Manivannan Sadhasivam - Mani > Reviewed-by: Serge Semin > --- > drivers/pci/controller/dwc/pcie-designware.c | 8 +++++++- > drivers/pci/controller/dwc/pcie-designware.h | 5 +++-- > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index c4998194fe74..4812ce040f1e 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -883,8 +883,14 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) > * Indirect eDMA CSRs access has been completely removed since v5.40a > * thus no space is now reserved for the eDMA channels viewport and > * former DMA CTRL register is no longer fixed to FFs. > + * > + * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason > + * have zeros in the eDMA CTRL register even though the HW-manual > + * explicitly states there must FFs if the unrolled mapping is enabled. > + * For such cases the low-level drivers are supposed to manually > + * activate the unrolled mapping to bypass the auto-detection procedure. > */ > - if (dw_pcie_ver_is_ge(pci, 540A)) > + if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL)) > val = 0xFFFFFFFF; > else > val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 94bc20f5f600..6821446d7c66 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -51,8 +51,9 @@ > > /* DWC PCIe controller capabilities */ > #define DW_PCIE_CAP_REQ_RES 0 > -#define DW_PCIE_CAP_IATU_UNROLL 1 > -#define DW_PCIE_CAP_CDM_CHECK 2 > +#define DW_PCIE_CAP_EDMA_UNROLL 1 > +#define DW_PCIE_CAP_IATU_UNROLL 2 > +#define DW_PCIE_CAP_CDM_CHECK 3 > > #define dw_pcie_cap_is(_pci, _cap) \ > test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) > -- > 2.25.1 > -- மணிவண்ணன் சதாசிவம்