From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Atish Patra <atishp@atishpatra.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
Conor Dooley <conor@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: [PATCH v3 2/7] dt-bindings: riscv: Add smstateen entry
Date: Mon, 24 Jul 2023 19:50:28 +0530 [thread overview]
Message-ID: <20230724142033.306538-3-mchitale@ventanamicro.com> (raw)
In-Reply-To: <20230724142033.306538-1-mchitale@ventanamicro.com>
Add an entry for the Smstateen extension to the riscv,isa-extensions
property.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cc1f546fdbdc..36ff6749fbba 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -128,6 +128,12 @@ properties:
changes to interrupts as frozen at commit ccbddab ("Merge pull
request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
+ - const: smstateen
+ description: |
+ The standard Smstateen extension for controlling access to CSRs
+ added by other RISC-V extensions in H/S/VS/U/VU modes and as
+ ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
+
- const: ssaia
description: |
The standard Ssaia supervisor-level extension for the advanced
--
2.34.1
next prev parent reply other threads:[~2023-07-24 14:20 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-24 14:20 [PATCH v3 0/7] Risc-V Kvm Smstateen Mayuresh Chitale
2023-07-24 14:20 ` [PATCH v3 1/7] RISC-V: Detect Smstateen extension Mayuresh Chitale
2023-07-24 14:20 ` Mayuresh Chitale [this message]
2023-07-24 16:27 ` [PATCH v3 2/7] dt-bindings: riscv: Add smstateen entry Conor Dooley
2023-07-24 14:20 ` [PATCH v3 3/7] RISC-V: KVM: Add kvm_vcpu_config Mayuresh Chitale
2023-07-24 14:20 ` [PATCH v3 4/7] RISC-V: KVM: Enable Smstateen accesses Mayuresh Chitale
2023-07-24 14:20 ` [PATCH v3 5/7] RISCV: KVM: Add senvcfg context save/restore Mayuresh Chitale
2023-07-24 14:20 ` [PATCH v3 6/7] RISCV: KVM: Add sstateen0 " Mayuresh Chitale
2023-07-24 14:20 ` [PATCH v3 7/7] RISCV: KVM: Add sstateen0 to ONE_REG Mayuresh Chitale
2023-07-24 16:38 ` [PATCH v3 0/7] Risc-V Kvm Smstateen Conor Dooley
2023-07-25 4:17 ` Anup Patel
2023-07-25 10:06 ` Conor Dooley
2023-07-25 15:43 ` Anup Patel
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