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[2003:e4:1f1b:d600:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id n10-20020a170906164a00b00977cad140a8sm9766474ejd.218.2023.07.26.09.27.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Jul 2023 09:27:50 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, Rob Herring Subject: [PATCH v3 3/7] dt-bindings: arm: tegra: pmc: Move additionalProperties Date: Wed, 26 Jul 2023 18:27:40 +0200 Message-ID: <20230726162744.2113008-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230726162744.2113008-1-thierry.reding@gmail.com> References: <20230726162744.2113008-1-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding For indented subschemas it can be difficult to understand which block an additionalProperties property belongs to. Moving it closer to the beginning of a block is a good way to clarify this. Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v2: - add Reviewed-by: from Rob .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 0ac258bc7be0..d6f2c5862841 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -126,6 +126,7 @@ properties: description: The vast majority of hardware blocks of Tegra SoC belong to a core power domain, which has a dedicated voltage rail that powers the blocks. + additionalProperties: false properties: operating-points-v2: description: Should contain level, voltages and opp-supported-hw @@ -139,12 +140,11 @@ properties: - operating-points-v2 - "#power-domain-cells" - additionalProperties: false - i2c-thermtrip: type: object description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, hardware-triggered thermal reset will be enabled. + additionalProperties: false properties: nvidia,i2c-controller-id: $ref: /schemas/types.yaml#/definitions/uint32 @@ -176,10 +176,9 @@ properties: - nvidia,reg-addr - nvidia,reg-data - additionalProperties: false - powergates: type: object + additionalProperties: false description: | This node contains a hierarchy of power domain nodes, which should match the powergates on the Tegra SoC. Each powergate node represents a power- @@ -224,7 +223,6 @@ properties: "^[a-z0-9]+$": type: object additionalProperties: false - properties: clocks: minItems: 1 @@ -246,8 +244,6 @@ properties: - resets - '#power-domain-cells' - additionalProperties: false - patternProperties: "^[a-f0-9]+-[a-f0-9]+$": type: object -- 2.41.0