* [PATCH] arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration
@ 2023-07-24 22:22 Marek Vasut
2023-07-25 7:41 ` Marco Felsch
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Marek Vasut @ 2023-07-24 22:22 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Adam Ford, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Li Jun, Marco Felsch, NXP Linux Team,
Peng Fan, Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, devicetree
The CSI1 PHY reference clock are limited to 125 MHz according to:
i.MX 8M Nano Applications Processor Reference Manual, Rev. 2, 07/2022
Table 5-1. Clock Root Table (continued) / page 319
Slice Index n = 123 .
Currently those IMX8MN_CLK_CSI1_PHY_REF clock are configured to be
fed directly from 1 GHz PLL2 , which overclocks them . Instead, drop
the configuration altogether, which defaults the clock to 24 MHz REF
clock input, which for the PHY reference clock is just fine.
Fixes: ae9279f301b5 ("arm64: dts: imx8mn: Add CSI and ISI Nodes")
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Adam Ford <aford173@gmail.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Li Jun <jun.li@nxp.com>
Cc: Marco Felsch <m.felsch@pengutronix.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 9869fe7652fca..aa38dd6dc9ba5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1175,10 +1175,8 @@ mipi_csi: mipi-csi@32e30000 {
compatible = "fsl,imx8mm-mipi-csi2";
reg = <0x32e30000 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>,
- <&clk IMX8MN_CLK_CSI1_PHY_REF>;
- assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>,
- <&clk IMX8MN_SYS_PLL2_1000M>;
+ assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
assigned-clock-rates = <333000000>;
clock-frequency = <333000000>;
clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
--
2.40.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration
2023-07-24 22:22 [PATCH] arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration Marek Vasut
@ 2023-07-25 7:41 ` Marco Felsch
2023-07-25 13:01 ` Adam Ford
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Marco Felsch @ 2023-07-25 7:41 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Adam Ford, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Li Jun, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, devicetree
On 23-07-25, Marek Vasut wrote:
> The CSI1 PHY reference clock are limited to 125 MHz according to:
> i.MX 8M Nano Applications Processor Reference Manual, Rev. 2, 07/2022
> Table 5-1. Clock Root Table (continued) / page 319
> Slice Index n = 123 .
>
> Currently those IMX8MN_CLK_CSI1_PHY_REF clock are configured to be
> fed directly from 1 GHz PLL2 , which overclocks them . Instead, drop
> the configuration altogether, which defaults the clock to 24 MHz REF
> clock input, which for the PHY reference clock is just fine.
>
> Fixes: ae9279f301b5 ("arm64: dts: imx8mn: Add CSI and ISI Nodes")
> Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
> ---
> Cc: Adam Ford <aford173@gmail.com>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Li Jun <jun.li@nxp.com>
> Cc: Marco Felsch <m.felsch@pengutronix.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Richard Cochran <richardcochran@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> ---
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 9869fe7652fca..aa38dd6dc9ba5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -1175,10 +1175,8 @@ mipi_csi: mipi-csi@32e30000 {
> compatible = "fsl,imx8mm-mipi-csi2";
> reg = <0x32e30000 0x1000>;
> interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> - assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>,
> - <&clk IMX8MN_CLK_CSI1_PHY_REF>;
> - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>,
> - <&clk IMX8MN_SYS_PLL2_1000M>;
> + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
> + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
> assigned-clock-rates = <333000000>;
> clock-frequency = <333000000>;
> clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
> --
> 2.40.1
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration
2023-07-24 22:22 [PATCH] arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration Marek Vasut
2023-07-25 7:41 ` Marco Felsch
@ 2023-07-25 13:01 ` Adam Ford
2023-07-25 13:02 ` Fabio Estevam
2023-07-30 13:29 ` Shawn Guo
3 siblings, 0 replies; 5+ messages in thread
From: Adam Ford @ 2023-07-25 13:01 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Li Jun, Marco Felsch, NXP Linux Team,
Peng Fan, Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, devicetree
On Mon, Jul 24, 2023 at 5:22 PM Marek Vasut <marex@denx.de> wrote:
>
> The CSI1 PHY reference clock are limited to 125 MHz according to:
> i.MX 8M Nano Applications Processor Reference Manual, Rev. 2, 07/2022
> Table 5-1. Clock Root Table (continued) / page 319
> Slice Index n = 123 .
>
> Currently those IMX8MN_CLK_CSI1_PHY_REF clock are configured to be
> fed directly from 1 GHz PLL2 , which overclocks them . Instead, drop
> the configuration altogether, which defaults the clock to 24 MHz REF
> clock input, which for the PHY reference clock is just fine.
>
> Fixes: ae9279f301b5 ("arm64: dts: imx8mn: Add CSI and ISI Nodes")
> Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Adam Ford <aford173@gmail.com>
> ---
> Cc: Adam Ford <aford173@gmail.com>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> Cc: Li Jun <jun.li@nxp.com>
> Cc: Marco Felsch <m.felsch@pengutronix.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Richard Cochran <richardcochran@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> ---
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 9869fe7652fca..aa38dd6dc9ba5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -1175,10 +1175,8 @@ mipi_csi: mipi-csi@32e30000 {
> compatible = "fsl,imx8mm-mipi-csi2";
> reg = <0x32e30000 0x1000>;
> interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> - assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>,
> - <&clk IMX8MN_CLK_CSI1_PHY_REF>;
> - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>,
> - <&clk IMX8MN_SYS_PLL2_1000M>;
> + assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
> + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
> assigned-clock-rates = <333000000>;
> clock-frequency = <333000000>;
> clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration
2023-07-24 22:22 [PATCH] arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration Marek Vasut
2023-07-25 7:41 ` Marco Felsch
2023-07-25 13:01 ` Adam Ford
@ 2023-07-25 13:02 ` Fabio Estevam
2023-07-30 13:29 ` Shawn Guo
3 siblings, 0 replies; 5+ messages in thread
From: Fabio Estevam @ 2023-07-25 13:02 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Adam Ford, Conor Dooley, Krzysztof Kozlowski,
Li Jun, Marco Felsch, NXP Linux Team, Peng Fan,
Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, Shawn Guo, devicetree
Hi Marek,
On Mon, Jul 24, 2023 at 7:22 PM Marek Vasut <marex@denx.de> wrote:
>
> The CSI1 PHY reference clock are limited to 125 MHz according to:
> i.MX 8M Nano Applications Processor Reference Manual, Rev. 2, 07/2022
> Table 5-1. Clock Root Table (continued) / page 319
> Slice Index n = 123 .
>
> Currently those IMX8MN_CLK_CSI1_PHY_REF clock are configured to be
> fed directly from 1 GHz PLL2 , which overclocks them . Instead, drop
> the configuration altogether, which defaults the clock to 24 MHz REF
> clock input, which for the PHY reference clock is just fine.
>
> Fixes: ae9279f301b5 ("arm64: dts: imx8mn: Add CSI and ISI Nodes")
> Signed-off-by: Marek Vasut <marex@denx.de>
Good catch:
Reviewed-by: Fabio Estevam <festevam@gmail.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration
2023-07-24 22:22 [PATCH] arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration Marek Vasut
` (2 preceding siblings ...)
2023-07-25 13:02 ` Fabio Estevam
@ 2023-07-30 13:29 ` Shawn Guo
3 siblings, 0 replies; 5+ messages in thread
From: Shawn Guo @ 2023-07-30 13:29 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Adam Ford, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Li Jun, Marco Felsch, NXP Linux Team,
Peng Fan, Pengutronix Kernel Team, Richard Cochran, Rob Herring,
Sascha Hauer, devicetree
On Tue, Jul 25, 2023 at 12:22:47AM +0200, Marek Vasut wrote:
> The CSI1 PHY reference clock are limited to 125 MHz according to:
> i.MX 8M Nano Applications Processor Reference Manual, Rev. 2, 07/2022
> Table 5-1. Clock Root Table (continued) / page 319
> Slice Index n = 123 .
>
> Currently those IMX8MN_CLK_CSI1_PHY_REF clock are configured to be
> fed directly from 1 GHz PLL2 , which overclocks them . Instead, drop
> the configuration altogether, which defaults the clock to 24 MHz REF
> clock input, which for the PHY reference clock is just fine.
>
> Fixes: ae9279f301b5 ("arm64: dts: imx8mn: Add CSI and ISI Nodes")
> Signed-off-by: Marek Vasut <marex@denx.de>
Applied, thanks!
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-07-30 13:30 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-07-24 22:22 [PATCH] arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration Marek Vasut
2023-07-25 7:41 ` Marco Felsch
2023-07-25 13:01 ` Adam Ford
2023-07-25 13:02 ` Fabio Estevam
2023-07-30 13:29 ` Shawn Guo
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).