Re: [PATCH v10 03/11] usb: dwc3: core: Access XHCI address space temporarily to read port info

[Thinh Nguyen <Thinh.Nguyen@synopsys.com>]

On Fri, Jul 28, 2023, Krishna Kurapati wrote:
> Currently host-only capable DWC3 controllers support Multiport.
> Temporarily map XHCI address space for host-only controllers and parse
> XHCI Extended Capabilities registers to read number of usb2 ports and
> usb3 ports present on multiport controller. Each USB Port is at least HS
> capable.
> 
> Since the extcaps header is only being used, move port_count related
> macros and structure from xhci.h to xhci-ext-caps.h.
> 
> The port info for usb2 and usb3 phy are identified as num_usb2_ports
> and num_usb3_ports. The intention is as follows:
> 
> Wherever we need to perform phy operations like:
> 
> LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
> {
> 	phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> 	phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> }
> 
> If number of usb2 ports is 3, loop can go from index 0-2 for
> usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
> if the first 2 ports are SS capable or some other ports like (2 and 3)
> are SS capable. So instead, num_usb2_ports is used to loop around all
> phy's (both hs and ss) for performing phy operations. If any
> usb3_generic_phy turns out to be NULL, phy operation just bails out.
> 
> num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
> phy's as we need to know how many SS capable ports are there for this.
> 
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
>  drivers/usb/dwc3/core.c          | 61 ++++++++++++++++++++++++++++++++
>  drivers/usb/dwc3/core.h          |  5 +++
>  drivers/usb/host/xhci-ext-caps.h | 27 ++++++++++++++
>  drivers/usb/host/xhci.h          | 27 --------------
>  4 files changed, 93 insertions(+), 27 deletions(-)

Please split the moving of code for xhci in a separate commit.

Thanks,
Thinh