* [PATCH v2 0/4] SDM670 CPU Frequency Scaling
@ 2023-08-02 1:15 Richard Acayan
2023-08-02 1:15 ` [PATCH v2 1/4] dt-bindings: interconnect: add SDM670 OSM L3 compatible Richard Acayan
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Richard Acayan @ 2023-08-02 1:15 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Georgi Djakov,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sibi Sankar,
linux-arm-msm, linux-pm, devicetree
Cc: Richard Acayan
Changes since v1 (20230724214209.208699-6-mailingradian@gmail.com):
- removed voltage documentation in device tree (3/4)
- amended commit message to mention bandwidth scaling (3/4)
- accumulated review tags (1-2/4)
This adds CPU frequency scaling and the OSM L3 cache controller to the
SDM670 device tree.
Richard Acayan (4):
dt-bindings: interconnect: add SDM670 OSM L3 compatible
arm64: dts: qcom: sdm670: add osm l3
arm64: dts: qcom: sdm670: add cpu frequency scaling
arm64: dts: qcom: sdm670: add frequency profile
.../bindings/interconnect/qcom,osm-l3.yaml | 1 +
arch/arm64/boot/dts/qcom/sdm670.dtsi | 175 ++++++++++++++++++
2 files changed, 176 insertions(+)
--
2.41.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/4] dt-bindings: interconnect: add SDM670 OSM L3 compatible
2023-08-02 1:15 [PATCH v2 0/4] SDM670 CPU Frequency Scaling Richard Acayan
@ 2023-08-02 1:15 ` Richard Acayan
2023-08-02 1:15 ` [PATCH v2 2/4] arm64: dts: qcom: sdm670: add osm l3 Richard Acayan
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Richard Acayan @ 2023-08-02 1:15 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Georgi Djakov,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sibi Sankar,
linux-arm-msm, linux-pm, devicetree
Cc: Richard Acayan
Add the compatible for the OSM L3 interconnect used in the Snapdragon
670.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index 9d0a98d77ae9..21dae0b92819 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -21,6 +21,7 @@ properties:
- enum:
- qcom,sc7180-osm-l3
- qcom,sc8180x-osm-l3
+ - qcom,sdm670-osm-l3
- qcom,sdm845-osm-l3
- qcom,sm6350-osm-l3
- qcom,sm8150-osm-l3
--
2.41.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/4] arm64: dts: qcom: sdm670: add osm l3
2023-08-02 1:15 [PATCH v2 0/4] SDM670 CPU Frequency Scaling Richard Acayan
2023-08-02 1:15 ` [PATCH v2 1/4] dt-bindings: interconnect: add SDM670 OSM L3 compatible Richard Acayan
@ 2023-08-02 1:15 ` Richard Acayan
2023-08-02 1:15 ` [PATCH v2 3/4] arm64: dts: qcom: sdm670: add cpu frequency scaling Richard Acayan
2023-08-02 1:15 ` [PATCH v2 4/4] arm64: dts: qcom: sdm670: add frequency profile Richard Acayan
3 siblings, 0 replies; 6+ messages in thread
From: Richard Acayan @ 2023-08-02 1:15 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Georgi Djakov,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sibi Sankar,
linux-arm-msm, linux-pm, devicetree
Cc: Richard Acayan
Add the interconnect node for L3 cache on SDM670.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index a1c207c0266d..45f9633d2d2c 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -1354,5 +1354,15 @@ intc: interrupt-controller@17a00000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <3>;
};
+
+ osm_l3: interconnect@17d41000 {
+ compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3";
+ reg = <0 0x17d41000 0 0x1400>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
};
};
--
2.41.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/4] arm64: dts: qcom: sdm670: add cpu frequency scaling
2023-08-02 1:15 [PATCH v2 0/4] SDM670 CPU Frequency Scaling Richard Acayan
2023-08-02 1:15 ` [PATCH v2 1/4] dt-bindings: interconnect: add SDM670 OSM L3 compatible Richard Acayan
2023-08-02 1:15 ` [PATCH v2 2/4] arm64: dts: qcom: sdm670: add osm l3 Richard Acayan
@ 2023-08-02 1:15 ` Richard Acayan
2023-08-02 1:15 ` [PATCH v2 4/4] arm64: dts: qcom: sdm670: add frequency profile Richard Acayan
3 siblings, 0 replies; 6+ messages in thread
From: Richard Acayan @ 2023-08-02 1:15 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Georgi Djakov,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sibi Sankar,
linux-arm-msm, linux-pm, devicetree
Cc: Richard Acayan
Add CPU frequency scaling, and also add the corresponding memory and
cache bandwidths for each frequency.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 149 +++++++++++++++++++++++++++
1 file changed, 149 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 45f9633d2d2c..e1ef3fc2ace0 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
@@ -35,6 +36,10 @@ CPU0: cpu@0 {
compatible = "qcom,kryo360";
reg = <0x0 0x0>;
enable-method = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
next-level-cache = <&L2_0>;
@@ -56,6 +61,10 @@ CPU1: cpu@100 {
compatible = "qcom,kryo360";
reg = <0x0 0x100>;
enable-method = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
next-level-cache = <&L2_100>;
@@ -72,6 +81,10 @@ CPU2: cpu@200 {
compatible = "qcom,kryo360";
reg = <0x0 0x200>;
enable-method = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
next-level-cache = <&L2_200>;
@@ -88,6 +101,10 @@ CPU3: cpu@300 {
compatible = "qcom,kryo360";
reg = <0x0 0x300>;
enable-method = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
next-level-cache = <&L2_300>;
@@ -104,6 +121,10 @@ CPU4: cpu@400 {
compatible = "qcom,kryo360";
reg = <0x0 0x400>;
enable-method = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
next-level-cache = <&L2_400>;
@@ -120,6 +141,10 @@ CPU5: cpu@500 {
compatible = "qcom,kryo360";
reg = <0x0 0x500>;
enable-method = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
next-level-cache = <&L2_500>;
@@ -136,6 +161,10 @@ CPU6: cpu@600 {
compatible = "qcom,kryo360";
reg = <0x0 0x600>;
enable-method = "psci";
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu6_opp_table>;
+ interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
next-level-cache = <&L2_600>;
@@ -152,6 +181,10 @@ CPU7: cpu@700 {
compatible = "qcom,kryo360";
reg = <0x0 0x700>;
enable-method = "psci";
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu6_opp_table>;
+ interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
next-level-cache = <&L2_700>;
@@ -246,6 +279,111 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu0_opp1: opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <400000 4800000>;
+ };
+
+ cpu0_opp2: opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-peak-kBps = <400000 4800000>;
+ };
+
+ cpu0_opp3: opp-748800000 {
+ opp-hz = /bits/ 64 <748800000>;
+ opp-peak-kBps = <1200000 4800000>;
+ };
+
+ cpu0_opp4: opp-998400000 {
+ opp-hz = /bits/ 64 <998400000>;
+ opp-peak-kBps = <1804000 8908800>;
+ };
+
+ cpu0_opp5: opp-1209600000 {
+ opp-hz = /bits/ 64 <1209600000>;
+ opp-peak-kBps = <2188000 8908800>;
+ };
+
+ cpu0_opp6: opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-peak-kBps = <2188000 13516800>;
+ };
+
+ cpu0_opp7: opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-peak-kBps = <3072000 15052800>;
+ };
+
+ cpu0_opp8: opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <3072000 22118400>;
+ };
+
+ cpu0_opp9: opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <4068000 23040000>;
+ };
+ };
+
+ cpu6_opp_table: opp-table-cpu6 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu6_opp1: opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <400000 4800000>;
+ };
+
+ cpu6_opp2: opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-peak-kBps = <400000 4800000>;
+ };
+
+ cpu6_opp3: opp-825600000 {
+ opp-hz = /bits/ 64 <825600000>;
+ opp-peak-kBps = <1200000 4800000>;
+ };
+
+ cpu6_opp4: opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ opp-peak-kBps = <1200000 4800000>;
+ };
+
+ cpu6_opp5: opp-1132800000 {
+ opp-hz = /bits/ 64 <1132800000>;
+ opp-peak-kBps = <2188000 8908800>;
+ };
+
+ cpu6_opp6: opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-peak-kBps = <4068000 12902400>;
+ };
+
+ cpu6_opp7: opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <4068000 12902400>;
+ };
+
+ cpu6_opp8: opp-1747200000 {
+ opp-hz = /bits/ 64 <1747200000>;
+ opp-peak-kBps = <4068000 15052800>;
+ };
+
+ cpu6_opp9: opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ opp-peak-kBps = <4068000 15052800>;
+ };
+
+ cpu6_opp10: opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-peak-kBps = <6220000 19046400>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -1364,5 +1502,16 @@ osm_l3: interconnect@17d41000 {
#interconnect-cells = <1>;
};
+
+ cpufreq_hw: cpufreq@17d43000 {
+ compatible = "qcom,cpufreq-hw";
+ reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
+ reg-names = "freq-domain0", "freq-domain1";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #freq-domain-cells = <1>;
+ };
};
};
--
2.41.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 4/4] arm64: dts: qcom: sdm670: add frequency profile
2023-08-02 1:15 [PATCH v2 0/4] SDM670 CPU Frequency Scaling Richard Acayan
` (2 preceding siblings ...)
2023-08-02 1:15 ` [PATCH v2 3/4] arm64: dts: qcom: sdm670: add cpu frequency scaling Richard Acayan
@ 2023-08-02 1:15 ` Richard Acayan
2023-08-10 20:20 ` Konrad Dybcio
3 siblings, 1 reply; 6+ messages in thread
From: Richard Acayan @ 2023-08-02 1:15 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Georgi Djakov,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sibi Sankar,
linux-arm-msm, linux-pm, devicetree
Cc: Richard Acayan
Add the coefficients for the CPU frequencies to aid in frequency
scaling.
Profiling setup:
- freqbench (https://github.com/kdrag0n/freqbench)
- LineageOS kernel, android_kernel_google_msm-4.9
- recommended configuration options by freqbench
- disabled options that require clang or 32-bit compilers
- mmc governor switched from simple_ondemand to powersave
Frequency domains: cpu1 cpu6
Offline CPUs: cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7
Sampling power every 1000 ms
Baseline power usage: 445 mW
===== CPU 1 =====
Frequencies: 300 576 748 998 1209 1324 1516 1612 1708
300: 1114 3.7 C/MHz 43 mW 11.6 J 25.8 I/mJ 269.4 s
576: 2138 3.7 C/MHz 51 mW 7.1 J 42.2 I/mJ 140.3 s
748: 2780 3.7 C/MHz 67 mW 7.3 J 41.3 I/mJ 107.9 s
998: 3706 3.7 C/MHz 73 mW 5.9 J 51.1 I/mJ 80.9 s
1209: 4490 3.7 C/MHz 86 mW 5.7 J 52.2 I/mJ 66.8 s
1324: 4918 3.7 C/MHz 90 mW 5.5 J 54.6 I/mJ 61.0 s
1516: 5631 3.7 C/MHz 103 mW 5.5 J 54.9 I/mJ 53.3 s
1612: 5987 3.7 C/MHz 109 mW 5.5 J 55.0 I/mJ 50.1 s
1708: 6344 3.7 C/MHz 126 mW 5.9 J 50.5 I/mJ 47.3 s
===== CPU 6 =====
Frequencies: 300 652 825 979 1132 1363 1536 1747 1843 1996
300: 1868 6.2 C/MHz 53 mW 8.5 J 35.2 I/mJ 160.6 s
652: 4073 6.2 C/MHz 96 mW 7.1 J 42.4 I/mJ 73.7 s
825: 5132 6.2 C/MHz 117 mW 6.9 J 43.7 I/mJ 58.5 s
979: 6099 6.2 C/MHz 151 mW 7.4 J 40.4 I/mJ 49.2 s
1132: 7071 6.2 C/MHz 207 mW 8.8 J 34.1 I/mJ 42.4 s
1363: 8482 6.2 C/MHz 235 mW 8.3 J 36.1 I/mJ 35.4 s
1536: 9578 6.2 C/MHz 287 mW 9.0 J 33.3 I/mJ 31.3 s
1747: 10892 6.2 C/MHz 340 mW 9.4 J 32.0 I/mJ 27.6 s
1843: 11471 6.2 C/MHz 368 mW 9.6 J 31.1 I/mJ 26.2 s
1996: 12425 6.2 C/MHz 438 mW 10.6 J 28.3 I/mJ 24.2 s
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index e1ef3fc2ace0..0ac39d3d68ca 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -36,6 +36,8 @@ CPU0: cpu@0 {
compatible = "qcom,kryo360";
reg = <0x0 0x0>;
enable-method = "psci";
+ capacity-dmips-mhz = <610>;
+ dynamic-power-coefficient = <203>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
@@ -61,6 +63,8 @@ CPU1: cpu@100 {
compatible = "qcom,kryo360";
reg = <0x0 0x100>;
enable-method = "psci";
+ capacity-dmips-mhz = <610>;
+ dynamic-power-coefficient = <203>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
@@ -81,6 +85,8 @@ CPU2: cpu@200 {
compatible = "qcom,kryo360";
reg = <0x0 0x200>;
enable-method = "psci";
+ capacity-dmips-mhz = <610>;
+ dynamic-power-coefficient = <203>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
@@ -101,6 +107,8 @@ CPU3: cpu@300 {
compatible = "qcom,kryo360";
reg = <0x0 0x300>;
enable-method = "psci";
+ capacity-dmips-mhz = <610>;
+ dynamic-power-coefficient = <203>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
@@ -121,6 +129,8 @@ CPU4: cpu@400 {
compatible = "qcom,kryo360";
reg = <0x0 0x400>;
enable-method = "psci";
+ capacity-dmips-mhz = <610>;
+ dynamic-power-coefficient = <203>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
@@ -141,6 +151,8 @@ CPU5: cpu@500 {
compatible = "qcom,kryo360";
reg = <0x0 0x500>;
enable-method = "psci";
+ capacity-dmips-mhz = <610>;
+ dynamic-power-coefficient = <203>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
@@ -161,6 +173,8 @@ CPU6: cpu@600 {
compatible = "qcom,kryo360";
reg = <0x0 0x600>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <393>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
@@ -181,6 +195,8 @@ CPU7: cpu@700 {
compatible = "qcom,kryo360";
reg = <0x0 0x700>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <393>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
--
2.41.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 4/4] arm64: dts: qcom: sdm670: add frequency profile
2023-08-02 1:15 ` [PATCH v2 4/4] arm64: dts: qcom: sdm670: add frequency profile Richard Acayan
@ 2023-08-10 20:20 ` Konrad Dybcio
0 siblings, 0 replies; 6+ messages in thread
From: Konrad Dybcio @ 2023-08-10 20:20 UTC (permalink / raw)
To: Richard Acayan, Andy Gross, Bjorn Andersson, Georgi Djakov,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sibi Sankar,
linux-arm-msm, linux-pm, devicetree
On 2.08.2023 03:15, Richard Acayan wrote:
> Add the coefficients for the CPU frequencies to aid in frequency
> scaling.
>
> Profiling setup:
> - freqbench (https://github.com/kdrag0n/freqbench)
> - LineageOS kernel, android_kernel_google_msm-4.9
> - recommended configuration options by freqbench
> - disabled options that require clang or 32-bit compilers
> - mmc governor switched from simple_ondemand to powersave
>
> Frequency domains: cpu1 cpu6
> Offline CPUs: cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7
> Sampling power every 1000 ms
> Baseline power usage: 445 mW
>
> ===== CPU 1 =====
> Frequencies: 300 576 748 998 1209 1324 1516 1612 1708
>
> 300: 1114 3.7 C/MHz 43 mW 11.6 J 25.8 I/mJ 269.4 s
> 576: 2138 3.7 C/MHz 51 mW 7.1 J 42.2 I/mJ 140.3 s
> 748: 2780 3.7 C/MHz 67 mW 7.3 J 41.3 I/mJ 107.9 s
> 998: 3706 3.7 C/MHz 73 mW 5.9 J 51.1 I/mJ 80.9 s
> 1209: 4490 3.7 C/MHz 86 mW 5.7 J 52.2 I/mJ 66.8 s
> 1324: 4918 3.7 C/MHz 90 mW 5.5 J 54.6 I/mJ 61.0 s
> 1516: 5631 3.7 C/MHz 103 mW 5.5 J 54.9 I/mJ 53.3 s
> 1612: 5987 3.7 C/MHz 109 mW 5.5 J 55.0 I/mJ 50.1 s
> 1708: 6344 3.7 C/MHz 126 mW 5.9 J 50.5 I/mJ 47.3 s
>
> ===== CPU 6 =====
> Frequencies: 300 652 825 979 1132 1363 1536 1747 1843 1996
>
> 300: 1868 6.2 C/MHz 53 mW 8.5 J 35.2 I/mJ 160.6 s
> 652: 4073 6.2 C/MHz 96 mW 7.1 J 42.4 I/mJ 73.7 s
> 825: 5132 6.2 C/MHz 117 mW 6.9 J 43.7 I/mJ 58.5 s
> 979: 6099 6.2 C/MHz 151 mW 7.4 J 40.4 I/mJ 49.2 s
> 1132: 7071 6.2 C/MHz 207 mW 8.8 J 34.1 I/mJ 42.4 s
> 1363: 8482 6.2 C/MHz 235 mW 8.3 J 36.1 I/mJ 35.4 s
> 1536: 9578 6.2 C/MHz 287 mW 9.0 J 33.3 I/mJ 31.3 s
> 1747: 10892 6.2 C/MHz 340 mW 9.4 J 32.0 I/mJ 27.6 s
> 1843: 11471 6.2 C/MHz 368 mW 9.6 J 31.1 I/mJ 26.2 s
> 1996: 12425 6.2 C/MHz 438 mW 10.6 J 28.3 I/mJ 24.2 s
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
I've looked into this a bit and upstream handling of dynamic power seems
broken on qcom.. Trying to resolve this
Konrad
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-- links below jump to the message on this page --
2023-08-02 1:15 [PATCH v2 0/4] SDM670 CPU Frequency Scaling Richard Acayan
2023-08-02 1:15 ` [PATCH v2 1/4] dt-bindings: interconnect: add SDM670 OSM L3 compatible Richard Acayan
2023-08-02 1:15 ` [PATCH v2 2/4] arm64: dts: qcom: sdm670: add osm l3 Richard Acayan
2023-08-02 1:15 ` [PATCH v2 3/4] arm64: dts: qcom: sdm670: add cpu frequency scaling Richard Acayan
2023-08-02 1:15 ` [PATCH v2 4/4] arm64: dts: qcom: sdm670: add frequency profile Richard Acayan
2023-08-10 20:20 ` Konrad Dybcio
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