From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19F09C001DF for ; Wed, 2 Aug 2023 15:01:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234720AbjHBPB4 (ORCPT ); Wed, 2 Aug 2023 11:01:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234865AbjHBPB3 (ORCPT ); Wed, 2 Aug 2023 11:01:29 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F8E23AA4 for ; Wed, 2 Aug 2023 08:01:11 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1bbff6b2679so26842835ad.1 for ; Wed, 02 Aug 2023 08:01:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1690988470; x=1691593270; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VKnkNq9mHXbpDqEgJF2mGpUUpQc6aLvqIlFOdqDcBBw=; b=cPNW5uKbbO57D4rsKk1kcASZLXLSTInnQ/7hwa+23F859w8h1FA2JvSgyBYhIpdrz1 vYPwzAEicH8mdGSTfbMY/ZnxChf/bt1j9v5tSqS1fwOVwV5eeIeDX8SjcBn3TuLRwtOl ZhDW6hzVr8pjqd/OI4VsiBYp3M2Bivv07pyK2CxXmDOBE0ybJ7PJ90CTZBJPjMcMl54A QYRpDuR6WLtYoFKCRJLos56B9wrCf0/xz2vFcKd7RAbf3If6dVd9W32sgkomiMdfqeNA qevf0RO9IRX/r9ggk9x9l6QnaBgEVRkLdi/UJXotopxnJUBDmqsDPo8rSqbNY+W2360Y cF3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690988470; x=1691593270; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VKnkNq9mHXbpDqEgJF2mGpUUpQc6aLvqIlFOdqDcBBw=; b=aK+HIcmTBOD6WwQYRvgSRd1a5cUiSNZyxgTvUB30Ori7I47uRsG9u1+DOXF6auQPrv eG290QWxARsX5xcFzaBalTCN072ykh0EbbUAUjvvPTwii/kiVWt8DwTLl49kdFPNSq1D kKyFc4FyImyamxFSk8YKqW1hB+xpupz6VcgjLcrFPogLPjV5kT9uhftcsjlgXzkzkL/u tLfVBBTtQnUj9gLEocEK9h1KnC6j9hglucigxpuYaVn8qbGuhe5wAi+uh3lOpjs20Qd7 drTSySzUXNN9A+7Qfefo8/4HlSSp/+voV0UhrUegmU9fWqMNvkfV9mdHrsjHxmfd93uV zyDA== X-Gm-Message-State: ABy/qLb+atW91hrj4Nze02YaUWeHhbUsaYeWylN8XBFt8td8Ho8XQY1e Wv43zvYMoRez/r1KMfxYdoXWpg== X-Google-Smtp-Source: APBJJlEJravBKwN/7shsEYuXL01uLpmauUOzN4CqF8LhW3ObOtY0jZNiAr7N2OIh60lGxz2X1USnlw== X-Received: by 2002:a17:902:c20d:b0:1bb:9bc8:d22d with SMTP id 13-20020a170902c20d00b001bb9bc8d22dmr14427707pll.16.1690988470174; Wed, 02 Aug 2023 08:01:10 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id v11-20020a1709028d8b00b001bb99e188fcsm12503963plo.194.2023.08.02.08.01.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 08:01:09 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v7 06/15] irqchip/riscv-intc: Add support for RISC-V AIA Date: Wed, 2 Aug 2023 20:30:09 +0530 Message-Id: <20230802150018.327079-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230802150018.327079-1-apatel@ventanamicro.com> References: <20230802150018.327079-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The RISC-V advanced interrupt architecture (AIA) extends the per-HART local interrupts in following ways: 1. Minimum 64 local interrupts for both RV32 and RV64 2. Ability to process multiple pending local interrupts in same interrupt handler 3. Priority configuration for each local interrupts 4. Special CSRs to configure/access the per-HART MSI controller We add support for #1 and #2 described above in the RISC-V intc driver. Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-intc.c | 34 ++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 4e2704bc25fb..1a0fc87152c5 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include #include #include +#include static struct irq_domain *intc_domain; @@ -30,6 +31,15 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) generic_handle_domain_irq(intc_domain, cause); } +static asmlinkage void riscv_intc_aia_irq(struct pt_regs *regs) +{ + unsigned long topi; + + while ((topi = csr_read(CSR_TOPI))) + generic_handle_domain_irq(intc_domain, + topi >> TOPI_IID_SHIFT); +} + /* * On RISC-V systems local interrupts are masked or unmasked by writing * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written @@ -39,12 +49,18 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) static void riscv_intc_irq_mask(struct irq_data *d) { - csr_clear(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) + csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_clear(CSR_IE, BIT(d->hwirq)); } static void riscv_intc_irq_unmask(struct irq_data *d) { - csr_set(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) + csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_set(CSR_IE, BIT(d->hwirq)); } static void riscv_intc_irq_eoi(struct irq_data *d) @@ -115,16 +131,20 @@ static struct fwnode_handle *riscv_intc_hwnode(void) static int __init riscv_intc_init_common(struct fwnode_handle *fn) { - int rc; + int rc, nr_irqs = riscv_isa_extension_available(NULL, SxAIA) ? + 64 : BITS_PER_LONG; - intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG, + intc_domain = irq_domain_create_linear(fn, nr_irqs, &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; } - rc = set_handle_irq(&riscv_intc_irq); + if (riscv_isa_extension_available(NULL, SxAIA)) + rc = set_handle_irq(&riscv_intc_aia_irq); + else + rc = set_handle_irq(&riscv_intc_irq); if (rc) { pr_err("failed to set irq handler\n"); return rc; @@ -132,7 +152,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) riscv_set_intc_hwnode_fn(riscv_intc_hwnode); - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); + pr_info("%d local interrupts mapped%s\n", + nr_irqs, riscv_isa_extension_available(NULL, SxAIA) ? + " using AIA" : ""); return 0; } -- 2.34.1