[PATCH 0/3] Fix Versa3 clock mapping

Biju Das
2023-08-02T12:25:20Z

According to Table 3. ("Output Source") in the 5P35023 datasheet,
the output clock mapping should be 0=REF, 1=SE1, 2=SE2, 3=SE3,
4=DIFF1, 5=DIFF2. But the code uses inverse.

This patch series aims to document clock-output-names in bindings and
fix the mapping in driver.

Biju Das (3):
dt-bindings: clock: versaclock3: Document clock-output-names
clk: vc3: Fix output clock mapping
arm64: dts: renesas: rz-smarc-common: Use versa3 clk for audio mclk

.../bindings/clock/renesas,5p35023.yaml | 14 ++--
.../boot/dts/renesas/rz-smarc-common.dtsi | 14 ++--
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 23 +++++++
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 23 +++++++
arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 27 ++++++++
drivers/clk/clk-versaclock3.c | 68 +++++++++----------
6 files changed, 124 insertions(+), 45 deletions(-)

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2.25.1