From: Bjorn Helgaas <helgaas@kernel.org>
To: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
bhelgaas@google.com, krzysztof.kozlowski@linaro.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
lpieralisi@kernel.org, bharat.kumar.gogada@amd.com,
michal.simek@amd.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 2/2] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses.
Date: Tue, 8 Aug 2023 10:49:39 -0500 [thread overview]
Message-ID: <20230808154939.GA313654@bhelgaas> (raw)
In-Reply-To: <20230808103733.93707-4-thippeswamy.havalige@amd.com>
On Tue, Aug 08, 2023 at 04:07:33PM +0530, Thippeswamy Havalige wrote:
> Our controller is expecting ECAM size to be programmed by software. By
> programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB
> ECAM region which is used to detect 16 buses, so by updating
> "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB
> ECAM region to detect 256 buses.
>
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
1) I'm still concerned that this adds a revlock with the corresponding
DT change. Is that acceptable? Should it be mentioned in the commit
log?
2) Lorenzo or Krzysztof, if/when you apply this, please drop the
period at the end of the subject line. I've mentioned it several
times to no avail.
> ---
> changes in v2:
> - Update this changes in a seperate patch.
> ---
> drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
> index a73554e..b515019 100644
> --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> @@ -126,7 +126,7 @@
> #define E_ECAM_CR_ENABLE BIT(0)
> #define E_ECAM_SIZE_LOC GENMASK(20, 16)
> #define E_ECAM_SIZE_SHIFT 16
> -#define NWL_ECAM_VALUE_DEFAULT 12
> +#define NWL_ECAM_VALUE_DEFAULT 16
>
> #define CFG_DMA_REG_BAR GENMASK(2, 0)
> #define CFG_PCIE_CACHE GENMASK(7, 0)
> --
> 1.8.3.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-08-08 16:25 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-08 10:37 [PATCH v2] PCI: xilinx-nwl: Remove unnecessary code which updates primary,secondary and sub-ordinate bus numbers Thippeswamy Havalige
2023-08-08 10:37 ` [PATCH v2 0/2] Increase ecam size value to discover 256 buses during Thippeswamy Havalige
2023-08-08 10:37 ` [PATCH v2 1/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example Thippeswamy Havalige
2023-08-08 17:16 ` Hugo Villeneuve
2023-08-08 10:37 ` [PATCH v2 2/2] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Thippeswamy Havalige
2023-08-08 15:49 ` Bjorn Helgaas [this message]
2023-08-08 15:56 ` [PATCH v2] PCI: xilinx-nwl: Remove unnecessary code which updates primary,secondary and sub-ordinate bus numbers Bjorn Helgaas
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