[PATCH 0/3] arm64: dts: ti: Introduce AM62P SoCs

[PATCH 0/3] arm64: dts: ti: Introduce AM62P SoCs

[Vignesh Raghavendra]

This series adds basic support for AM62P family of SoCs and specifically
AM62P5 variant. Also adds AM62P5-SK EVM support with basic peripheral
like UART.

TRM at [0] and Schematics is at [1]

[0]: https://www.ti.com/lit/pdf/spruj83
[1]: https://www.ti.com/lit/zip/sprr487

Bryan Brattlof (3):
  dt-bindings: arm: ti: Add bindings for AM62P5 SoCs
  arm64: dts: ti: Introduce AM62P5 family of SoCs
  arm64: dts: ti: Add support for the AM62P5-SK

 .../devicetree/bindings/arm/ti/k3.yaml        |   6 +
 arch/arm64/boot/dts/ti/Makefile               |   3 +
 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi     | 129 +++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi      |  16 ++
 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi   |  30 ++++
 arch/arm64/boot/dts/ti/k3-am62p.dtsi          | 109 +++++++++++
 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts       | 169 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p5.dtsi         | 107 +++++++++++
 arch/arm64/boot/dts/ti/k3-pinctrl.h           |   3 +
 9 files changed, 572 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5.dtsi

-- 
2.41.0

[PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs

[Vignesh Raghavendra]

From: Bryan Brattlof <bb@ti.com>

Add bindings for TI's AM62P5 family of devices.

Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
index 5ca6af492507..93b2774cc0a9 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -25,6 +25,12 @@ properties:
               - ti,am62a7-sk
           - const: ti,am62a7
 
+      - description: K3 AM62P5 SoC
+        items:
+          - enum:
+              - ti,am62p5-sk
+          - const: ti,am62p5
+
       - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra
         items:
           - const: phytec,am625-phyboard-lyra-rdk
-- 
2.41.0

Re: [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs

[Rob Herring]

On Thu, 10 Aug 2023 10:23:12 +0530, Vignesh Raghavendra wrote:
> From: Bryan Brattlof <bb@ti.com>
> 
> Add bindings for TI's AM62P5 family of devices.
> 
> Signed-off-by: Bryan Brattlof <bb@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
>  Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:


doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230810045314.2676833-2-vigneshr@ti.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs

[Conor Dooley]

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On Thu, Aug 10, 2023 at 10:23:12AM +0530, Vignesh Raghavendra wrote:
> From: Bryan Brattlof <bb@ti.com>
> 
> Add bindings for TI's AM62P5 family of devices.
> 
> Signed-off-by: Bryan Brattlof <bb@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
>  Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> index 5ca6af492507..93b2774cc0a9 100644
> --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
> +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> @@ -25,6 +25,12 @@ properties:
>                - ti,am62a7-sk
>            - const: ti,am62a7
>  
> +      - description: K3 AM62P5 SoC

SoC seems a bit off here, since the sk is actually a board using the
SoC, but it seems to be the convention for TI stuff,
Acked-by: Conor Dooley <conor.dooley@microchip.com>



> +        items:
> +          - enum:
> +              - ti,am62p5-sk
> +          - const: ti,am62p5
> +
>        - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra
>          items:
>            - const: phytec,am625-phyboard-lyra-rdk
> -- 
> 2.41.0
> 

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Re: [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs

[Nishanth Menon]

On 17:03-20230810, Conor Dooley wrote:
> On Thu, Aug 10, 2023 at 10:23:12AM +0530, Vignesh Raghavendra wrote:
> > From: Bryan Brattlof <bb@ti.com>
> > 
> > Add bindings for TI's AM62P5 family of devices.
> > 
> > Signed-off-by: Bryan Brattlof <bb@ti.com>
> > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> > ---
> >  Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> > index 5ca6af492507..93b2774cc0a9 100644
> > --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
> > +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> > @@ -25,6 +25,12 @@ properties:
> >                - ti,am62a7-sk
> >            - const: ti,am62a7
> >  
> > +      - description: K3 AM62P5 SoC
> 
> SoC seems a bit off here, since the sk is actually a board using the
> SoC, but it seems to be the convention for TI stuff,

Thanks for providing that perspective - there will be new boards
getting added to the enum list, they should be one line additions at
this point.

But, your point taken. K3 AM625P SoC based boards is more appropriate.

I can do the local change as I apply and keep your ack unless you
object.

> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> 
> 
> 
> > +        items:
> > +          - enum:
> > +              - ti,am62p5-sk
> > +          - const: ti,am62p5
> > +
> >        - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra
> >          items:
> >            - const: phytec,am625-phyboard-lyra-rdk
> > -- 
> > 2.41.0
> > 



-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs

[Conor Dooley]

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On Thu, Aug 10, 2023 at 01:43:08PM -0500, Nishanth Menon wrote:
> On 17:03-20230810, Conor Dooley wrote:
> > On Thu, Aug 10, 2023 at 10:23:12AM +0530, Vignesh Raghavendra wrote:
> > > From: Bryan Brattlof <bb@ti.com>
> > > 
> > > Add bindings for TI's AM62P5 family of devices.
> > > 
> > > Signed-off-by: Bryan Brattlof <bb@ti.com>
> > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> > > ---
> > >  Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++
> > >  1 file changed, 6 insertions(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> > > index 5ca6af492507..93b2774cc0a9 100644
> > > --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
> > > +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> > > @@ -25,6 +25,12 @@ properties:
> > >                - ti,am62a7-sk
> > >            - const: ti,am62a7
> > >  
> > > +      - description: K3 AM62P5 SoC
> > 
> > SoC seems a bit off here, since the sk is actually a board using the
> > SoC, but it seems to be the convention for TI stuff,
> 
> Thanks for providing that perspective - there will be new boards
> getting added to the enum list, they should be one line additions at
> this point.
> 
> But, your point taken. K3 AM625P SoC based boards is more appropriate.
> 
> I can do the local change as I apply and keep your ack unless you
> object.

Oh totally no objection, "xyz SoC based boards" is what most people seem
to use.

> 
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > 
> > 
> > 
> > > +        items:
> > > +          - enum:
> > > +              - ti,am62p5-sk
> > > +          - const: ti,am62p5
> > > +
> > >        - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra
> > >          items:
> > >            - const: phytec,am625-phyboard-lyra-rdk
> > > -- 
> > > 2.41.0
> > > 
> 
> 
> 
> -- 
> Regards,
> Nishanth Menon
> Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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Re: [PATCH 1/3] dt-bindings: arm: ti: Add bindings for AM62P5 SoCs

[Nishanth Menon]

On 10:55-20230813, Conor Dooley wrote:
> On Thu, Aug 10, 2023 at 01:43:08PM -0500, Nishanth Menon wrote:
> > On 17:03-20230810, Conor Dooley wrote:
> > > On Thu, Aug 10, 2023 at 10:23:12AM +0530, Vignesh Raghavendra wrote:
> > > > From: Bryan Brattlof <bb@ti.com>
> > > > 
> > > > Add bindings for TI's AM62P5 family of devices.
> > > > 
> > > > Signed-off-by: Bryan Brattlof <bb@ti.com>
> > > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> > > > ---
> > > >  Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++
> > > >  1 file changed, 6 insertions(+)
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> > > > index 5ca6af492507..93b2774cc0a9 100644
> > > > --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
> > > > +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
> > > > @@ -25,6 +25,12 @@ properties:
> > > >                - ti,am62a7-sk
> > > >            - const: ti,am62a7
> > > >  
> > > > +      - description: K3 AM62P5 SoC
> > > 
> > > SoC seems a bit off here, since the sk is actually a board using the
> > > SoC, but it seems to be the convention for TI stuff,
> > 
> > Thanks for providing that perspective - there will be new boards
> > getting added to the enum list, they should be one line additions at
> > this point.
> > 
> > But, your point taken. K3 AM625P SoC based boards is more appropriate.
> > 
> > I can do the local change as I apply and keep your ack unless you
> > object.
> 
> Oh totally no objection, "xyz SoC based boards" is what most people seem
> to use.

Thank you V2 addresses it (the version I committed in), but looks like
the k3.yaml can do with a cleanup - will do it in one shot once the
window opens up.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

[PATCH 2/3] arm64: dts: ti: Introduce AM62P5 family of SoCs

[Vignesh Raghavendra]

From: Bryan Brattlof <bb@ti.com>

The AM62Px is an extension of the existing Sitara AM62x low-cost family
of application processors built for Automotive and Linux Application
development. Scalable Arm Cortex-A53 performance and embedded features,
such as: multi high-definition display support, 3D-graphics
acceleration, 4K video acceleration, and extensive peripherals make the
AM62Px well-suited for a broad range of automation and industrial
application, including automotive digital instrumentation, automotive
displays, industrial HMI, and more.

Some highlights of AM62P SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
  Dual/Single core variants are provided in the same package to allow HW
  compatible designs.
* One Device manager Cortext-R5F for system power and resource
  management, and one Cortex-R5F for Functional Safety or
  general-purpose usage.
* One 3D GPU up to 50 GLFOPS
* H.264/H.265 Video Encode/Decode.
* Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or
  2x OLDI-SL), DSI, or DPI. Up to 3840x1080@60fps resolution
* Integrated Giga-bit Ethernet switch supporting up to a total of two
  external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for
  NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
  1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized Hardware Security Module with support for secure
  boot, debug security and crypto acceleration and trusted execution
  environment.
* One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
  enabling battery powered system design.

For those interested, more details about this SoC can be found in the
Technical Reference Manual here:

    https://www.ti.com/lit/pdf/spruj83

Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi   | 129 ++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi    |  16 +++
 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi |  30 +++++
 arch/arm64/boot/dts/ti/k3-am62p.dtsi        | 109 +++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p5.dtsi       | 107 ++++++++++++++++
 arch/arm64/boot/dts/ti/k3-pinctrl.h         |   3 +
 6 files changed, 394 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p.dtsi
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5.dtsi

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
new file mode 100644
index 000000000000..3ce70be634b9
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for the AM62P main domain peripherals
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+	oc_sram: sram@70000000 {
+		compatible = "mmio-sram";
+		reg = <0x00 0x70000000 0x00 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x00 0x70000000 0x10000>;
+	};
+
+	gic500: interrupt-controller@1800000 {
+		compatible = "arm,gic-v3";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
+		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
+		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
+		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
+		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
+		/*
+		 * vcpumntirq:
+		 * virtual CPU interface maintenance interrupt
+		 */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+		gic_its: msi-controller@1820000 {
+			compatible = "arm,gic-v3-its";
+			reg = <0x00 0x01820000 0x00 0x10000>;
+			socionext,synquacer-pre-its = <0x1000000 0x400000>;
+			msi-controller;
+			#msi-cells = <1>;
+		};
+	};
+
+	dmss: bus@48000000 {
+		compatible = "simple-mfd";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-ranges;
+		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
+
+		ti,sci-dev-id = <25>;
+
+		secure_proxy_main: mailbox@4d000000 {
+			compatible = "ti,am654-secure-proxy";
+			#mbox-cells = <1>;
+			reg-names = "target_data", "rt", "scfg";
+			reg = <0x00 0x4d000000 0x00 0x80000>,
+			      <0x00 0x4a600000 0x00 0x80000>,
+			      <0x00 0x4a400000 0x00 0x80000>;
+			interrupt-names = "rx_012";
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	dmsc: system-controller@44043000 {
+		compatible = "ti,k2g-sci";
+		ti,host-id = <12>;
+		mbox-names = "rx", "tx";
+		mboxes = <&secure_proxy_main 12>,
+			 <&secure_proxy_main 13>;
+		reg-names = "debug_messages";
+		reg = <0x00 0x44043000 0x00 0xfe0>;
+
+		k3_pds: power-controller {
+			compatible = "ti,sci-pm-domain";
+			#power-domain-cells = <2>;
+		};
+
+		k3_clks: clock-controller {
+			compatible = "ti,k2g-sci-clk";
+			#clock-cells = <2>;
+		};
+
+		k3_reset: reset-controller {
+			compatible = "ti,sci-reset";
+			#reset-cells = <2>;
+		};
+	};
+
+	main_pmx0: pinctrl@f4000 {
+		compatible = "pinctrl-single";
+		reg = <0x00 0xf4000 0x00 0x2ac>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0xffffffff>;
+		status = "disabled";
+	};
+
+	main_timer0: timer@2400000 {
+		compatible = "ti,am654-timer";
+		reg = <0x00 0x2400000 0x00 0x400>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 36 2>;
+		clock-names = "fck";
+		assigned-clocks = <&k3_clks 36 2>;
+		assigned-clock-parents = <&k3_clks 36 3>;
+		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+		ti,timer-pwm;
+	};
+
+	main_uart0: serial@2800000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02800000 0x00 0x100>;
+		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 146 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+
+	main_uart1: serial@2810000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02810000 0x00 0x100>;
+		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 152 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
new file mode 100644
index 000000000000..bd6e8c12a1e8
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for the AM62P mcu domain peripherals
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu {
+	mcu_pmx0: pinctrl@4084000 {
+		compatible = "pinctrl-single";
+		reg = <0x00 0x04084000 0x00 0x88>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0xffffffff>;
+		status = "disabled";
+	};
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
new file mode 100644
index 000000000000..da8430222948
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for the AM62P wakeup domain peripherals
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_wakeup {
+	wkup_conf: bus@43000000 {
+		compatible = "simple-bus";
+		reg = <0x00 0x43000000 0x00 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x00 0x43000000 0x20000>;
+
+		chipid: chipid@14 {
+			compatible = "ti,am654-chipid";
+			reg = <0x14 0x4>;
+		};
+	};
+
+	wkup_uart0: serial@2b300000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x2b300000 0x00 0x100>;
+		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 114 0>;
+		clock-names = "fclk";
+		status = "disabled";
+	};
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
new file mode 100644
index 000000000000..305dda92ae7f
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for the AM62P5 SoC family
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/ {
+	model = "Texas Instruments K3 AM62P5 SoC";
+	compatible = "ti,am62p5";
+	interrupt-parent = <&gic500>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+
+		psci: psci {
+			compatible = "arm,psci-1.0";
+			method = "smc";
+		};
+	};
+
+	a53_timer0: timer-cl0-cpu0 {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	cbass_main: bus@f0000 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
+			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
+			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+			 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
+			 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
+			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+			 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
+			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
+			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
+			 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
+			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
+			 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
+			 <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
+			 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
+			 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
+			 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
+			 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
+			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
+			 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
+			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
+			 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
+			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
+			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
+			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
+			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
+			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+
+			 /* MCU Domain Range */
+			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral Window */
+
+			 /* Wakeup Domain Range */
+			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
+			 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; /* WKUP CTRL MMR */
+
+		cbass_mcu: bus@4000000 {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral Window */
+		};
+
+		cbass_wakeup: bus@b00000 {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
+				 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; /* WKUP CTRL MMR */
+		};
+	};
+};
+
+/* Now include peripherals for each bus segment */
+#include "k3-am62p-main.dtsi"
+#include "k3-am62p-mcu.dtsi"
+#include "k3-am62p-wakeup.dtsi"
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
new file mode 100644
index 000000000000..50147bb63e03
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for the AM62P5 SoC family (quad core)
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * TRM: https://www.ti.com/lit/pdf/spruj83
+ */
+
+/dts-v1/;
+
+#include "k3-am62p.dtsi"
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0: cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			reg = <0x000>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			clocks = <&k3_clks 135 0>;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53";
+			reg = <0x001>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			clocks = <&k3_clks 136 0>;
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53";
+			reg = <0x002>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			clocks = <&k3_clks 137 0>;
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53";
+			reg = <0x003>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			clocks = <&k3_clks 138 0>;
+		};
+	};
+
+	l2_0: l2-cache0 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+		cache-size = <0x80000>;
+		cache-line-size = <64>;
+		cache-sets = <512>;
+	};
+};
diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
index 6004e0967ec5..2a4e0e084d69 100644
--- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
+++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
@@ -41,6 +41,9 @@
 #define AM62AX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
 #define AM62AX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
 
+#define AM62PX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM62PX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
 #define AM62X_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
 #define AM62X_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
 
-- 
2.41.0

Re: [PATCH 2/3] arm64: dts: ti: Introduce AM62P5 family of SoCs

[Andrew Davis]

On 8/9/23 11:53 PM, Vignesh Raghavendra wrote:
> From: Bryan Brattlof <bb@ti.com>
> 
> The AM62Px is an extension of the existing Sitara AM62x low-cost family
> of application processors built for Automotive and Linux Application
> development. Scalable Arm Cortex-A53 performance and embedded features,
> such as: multi high-definition display support, 3D-graphics
> acceleration, 4K video acceleration, and extensive peripherals make the
> AM62Px well-suited for a broad range of automation and industrial
> application, including automotive digital instrumentation, automotive
> displays, industrial HMI, and more.
> 
> Some highlights of AM62P SoC are:
> * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
>    Dual/Single core variants are provided in the same package to allow HW
>    compatible designs.
> * One Device manager Cortext-R5F for system power and resource
>    management, and one Cortex-R5F for Functional Safety or
>    general-purpose usage.
> * One 3D GPU up to 50 GLFOPS
> * H.264/H.265 Video Encode/Decode.
> * Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or
>    2x OLDI-SL), DSI, or DPI. Up to 3840x1080@60fps resolution
> * Integrated Giga-bit Ethernet switch supporting up to a total of two
>    external ports (TSN capable).
> * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for
>    NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
>    1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
> * Dedicated Centralized Hardware Security Module with support for secure
>    boot, debug security and crypto acceleration and trusted execution
>    environment.
> * One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
> * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
>    enabling battery powered system design.
> 
> For those interested, more details about this SoC can be found in the
> Technical Reference Manual here:
> 
>      https://www.ti.com/lit/pdf/spruj83
> 
> Signed-off-by: Bryan Brattlof <bb@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-am62p-main.dtsi   | 129 ++++++++++++++++++++
>   arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi    |  16 +++
>   arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi |  30 +++++
>   arch/arm64/boot/dts/ti/k3-am62p.dtsi        | 109 +++++++++++++++++
>   arch/arm64/boot/dts/ti/k3-am62p5.dtsi       | 107 ++++++++++++++++
>   arch/arm64/boot/dts/ti/k3-pinctrl.h         |   3 +
>   6 files changed, 394 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
>   create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
>   create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
>   create mode 100644 arch/arm64/boot/dts/ti/k3-am62p.dtsi
>   create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5.dtsi
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
> new file mode 100644
> index 000000000000..3ce70be634b9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
> @@ -0,0 +1,129 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree file for the AM62P main domain peripherals
> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +&cbass_main {
> +	oc_sram: sram@70000000 {
> +		compatible = "mmio-sram";
> +		reg = <0x00 0x70000000 0x00 0x10000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x00 0x00 0x70000000 0x10000>;
> +	};
> +
> +	gic500: interrupt-controller@1800000 {
> +		compatible = "arm,gic-v3";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
> +		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
> +		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
> +		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
> +		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
> +		/*
> +		 * vcpumntirq:
> +		 * virtual CPU interface maintenance interrupt
> +		 */
> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		gic_its: msi-controller@1820000 {
> +			compatible = "arm,gic-v3-its";
> +			reg = <0x00 0x01820000 0x00 0x10000>;
> +			socionext,synquacer-pre-its = <0x1000000 0x400000>;
> +			msi-controller;
> +			#msi-cells = <1>;
> +		};
> +	};
> +
> +	dmss: bus@48000000 {
> +		compatible = "simple-mfd";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		dma-ranges;
> +		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
> +
> +		ti,sci-dev-id = <25>;
> +
> +		secure_proxy_main: mailbox@4d000000 {
> +			compatible = "ti,am654-secure-proxy";
> +			#mbox-cells = <1>;
> +			reg-names = "target_data", "rt", "scfg";
> +			reg = <0x00 0x4d000000 0x00 0x80000>,
> +			      <0x00 0x4a600000 0x00 0x80000>,
> +			      <0x00 0x4a400000 0x00 0x80000>;
> +			interrupt-names = "rx_012";
> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +	};
> +
> +	dmsc: system-controller@44043000 {
> +		compatible = "ti,k2g-sci";
> +		ti,host-id = <12>;
> +		mbox-names = "rx", "tx";
> +		mboxes = <&secure_proxy_main 12>,
> +			 <&secure_proxy_main 13>;
> +		reg-names = "debug_messages";
> +		reg = <0x00 0x44043000 0x00 0xfe0>;
> +
> +		k3_pds: power-controller {
> +			compatible = "ti,sci-pm-domain";
> +			#power-domain-cells = <2>;
> +		};
> +
> +		k3_clks: clock-controller {
> +			compatible = "ti,k2g-sci-clk";
> +			#clock-cells = <2>;
> +		};
> +
> +		k3_reset: reset-controller {
> +			compatible = "ti,sci-reset";
> +			#reset-cells = <2>;
> +		};
> +	};
> +
> +	main_pmx0: pinctrl@f4000 {
> +		compatible = "pinctrl-single";
> +		reg = <0x00 0xf4000 0x00 0x2ac>;
> +		#pinctrl-cells = <1>;
> +		pinctrl-single,register-width = <32>;
> +		pinctrl-single,function-mask = <0xffffffff>;
> +		status = "disabled";

Any reason we disable this by default here? I get it is not very useful
without any child nodes, but still it is technically complete as far
as the binding cares, right?

> +	};
> +
> +	main_timer0: timer@2400000 {
> +		compatible = "ti,am654-timer";
> +		reg = <0x00 0x2400000 0x00 0x400>;
> +		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&k3_clks 36 2>;
> +		clock-names = "fck";
> +		assigned-clocks = <&k3_clks 36 2>;
> +		assigned-clock-parents = <&k3_clks 36 3>;
> +		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
> +		ti,timer-pwm;
> +	};
> +
> +	main_uart0: serial@2800000 {
> +		compatible = "ti,am64-uart", "ti,am654-uart";
> +		reg = <0x00 0x02800000 0x00 0x100>;
> +		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> +		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 146 0>;
> +		clock-names = "fclk";
> +		status = "disabled";
> +	};
> +
> +	main_uart1: serial@2810000 {
> +		compatible = "ti,am64-uart", "ti,am654-uart";
> +		reg = <0x00 0x02810000 0x00 0x100>;
> +		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
> +		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 152 0>;
> +		clock-names = "fclk";
> +		status = "disabled";
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
> new file mode 100644
> index 000000000000..bd6e8c12a1e8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
> @@ -0,0 +1,16 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree file for the AM62P mcu domain peripherals

Lot of the documents call this the "MCU" domain, all caps, same for WAKEUP and
MAIN domains, no big deal either way.

> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +&cbass_mcu {
> +	mcu_pmx0: pinctrl@4084000 {
> +		compatible = "pinctrl-single";
> +		reg = <0x00 0x04084000 0x00 0x88>;
> +		#pinctrl-cells = <1>;
> +		pinctrl-single,register-width = <32>;
> +		pinctrl-single,function-mask = <0xffffffff>;
> +		status = "disabled";
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
> new file mode 100644
> index 000000000000..da8430222948
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree file for the AM62P wakeup domain peripherals
> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +&cbass_wakeup {
> +	wkup_conf: bus@43000000 {
> +		compatible = "simple-bus";
> +		reg = <0x00 0x43000000 0x00 0x20000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x00 0x00 0x43000000 0x20000>;
> +
> +		chipid: chipid@14 {
> +			compatible = "ti,am654-chipid";
> +			reg = <0x14 0x4>;
> +		};
> +	};
> +
> +	wkup_uart0: serial@2b300000 {
> +		compatible = "ti,am64-uart", "ti,am654-uart";
> +		reg = <0x00 0x2b300000 0x00 0x100>;
> +		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> +		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 114 0>;
> +		clock-names = "fclk";
> +		status = "disabled";
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
> new file mode 100644
> index 000000000000..305dda92ae7f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
> @@ -0,0 +1,109 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree file for the AM62P5 SoC family
> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/soc/ti,sci_pm_domain.h>
> +
> +#include "k3-pinctrl.h"
> +
> +/ {
> +	model = "Texas Instruments K3 AM62P5 SoC";
> +	compatible = "ti,am62p5";
> +	interrupt-parent = <&gic500>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	chosen { };

This empty chosen node doing anything for us?

Otherwise LGTM,

Acked-by: Andrew Davis <afd@ti.com>

> +
> +	firmware {
> +		optee {
> +			compatible = "linaro,optee-tz";
> +			method = "smc";
> +		};
> +
> +		psci: psci {
> +			compatible = "arm,psci-1.0";
> +			method = "smc";
> +		};
> +	};
> +
> +	a53_timer0: timer-cl0-cpu0 {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
> +	};
> +
> +	pmu: pmu {
> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	cbass_main: bus@f0000 {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +
> +		ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
> +			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
> +			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
> +			 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
> +			 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
> +			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
> +			 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
> +			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
> +			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
> +			 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
> +			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
> +			 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
> +			 <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
> +			 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
> +			 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
> +			 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
> +			 <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
> +			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
> +			 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
> +			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
> +			 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
> +			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
> +			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
> +			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
> +			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
> +			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
> +
> +			 /* MCU Domain Range */
> +			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral Window */
> +
> +			 /* Wakeup Domain Range */
> +			 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
> +			 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
> +			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; /* WKUP CTRL MMR */
> +
> +		cbass_mcu: bus@4000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral Window */
> +		};
> +
> +		cbass_wakeup: bus@b00000 {
> +			compatible = "simple-bus";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
> +				 <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
> +				 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; /* WKUP CTRL MMR */
> +		};
> +	};
> +};
> +
> +/* Now include peripherals for each bus segment */
> +#include "k3-am62p-main.dtsi"
> +#include "k3-am62p-mcu.dtsi"
> +#include "k3-am62p-wakeup.dtsi"
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
> new file mode 100644
> index 000000000000..50147bb63e03
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
> @@ -0,0 +1,107 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree file for the AM62P5 SoC family (quad core)
> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> + *
> + * TRM: https://www.ti.com/lit/pdf/spruj83
> + */
> +
> +/dts-v1/;
> +
> +#include "k3-am62p.dtsi"
> +
> +/ {
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0: cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +
> +				core2 {
> +					cpu = <&cpu2>;
> +				};
> +
> +				core3 {
> +					cpu = <&cpu3>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu@0 {
> +			compatible = "arm,cortex-a53";
> +			reg = <0x000>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			clocks = <&k3_clks 135 0>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			compatible = "arm,cortex-a53";
> +			reg = <0x001>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			clocks = <&k3_clks 136 0>;
> +		};
> +
> +		cpu2: cpu@2 {
> +			compatible = "arm,cortex-a53";
> +			reg = <0x002>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			clocks = <&k3_clks 137 0>;
> +		};
> +
> +		cpu3: cpu@3 {
> +			compatible = "arm,cortex-a53";
> +			reg = <0x003>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			clocks = <&k3_clks 138 0>;
> +		};
> +	};
> +
> +	l2_0: l2-cache0 {
> +		compatible = "cache";
> +		cache-unified;
> +		cache-level = <2>;
> +		cache-size = <0x80000>;
> +		cache-line-size = <64>;
> +		cache-sets = <512>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h
> index 6004e0967ec5..2a4e0e084d69 100644
> --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h
> +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h
> @@ -41,6 +41,9 @@
>   #define AM62AX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
>   #define AM62AX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
>   
> +#define AM62PX_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
> +#define AM62PX_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
> +
>   #define AM62X_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
>   #define AM62X_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
>   

Re: [PATCH 2/3] arm64: dts: ti: Introduce AM62P5 family of SoCs

[Krzysztof Kozlowski]

On 10/08/2023 06:53, Vignesh Raghavendra wrote:
> From: Bryan Brattlof <bb@ti.com>
> 
> The AM62Px is an extension of the existing Sitara AM62x low-cost family
> of application processors built for Automotive and Linux Application
> development. Scalable Arm Cortex-A53 performance and embedded features,
> such as: multi high-definition display support, 3D-graphics
> acceleration, 4K video acceleration, and extensive peripherals make the
> AM62Px well-suited for a broad range of automation and industrial
> application, including automotive digital instrumentation, automotive
> displays, industrial HMI, and more.
> 

...

> +
> +		gic_its: msi-controller@1820000 {
> +			compatible = "arm,gic-v3-its";
> +			reg = <0x00 0x01820000 0x00 0x10000>;
> +			socionext,synquacer-pre-its = <0x1000000 0x400000>;
> +			msi-controller;
> +			#msi-cells = <1>;
> +		};
> +	};
> +
> +	dmss: bus@48000000 {
> +		compatible = "simple-mfd";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		dma-ranges;
> +		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
> +
> +		ti,sci-dev-id = <25>;

Are you sure this passes dtbs_check?


> +
> +		secure_proxy_main: mailbox@4d000000 {
> +			compatible = "ti,am654-secure-proxy";
> +			#mbox-cells = <1>;
> +			reg-names = "target_data", "rt", "scfg";
> +			reg = <0x00 0x4d000000 0x00 0x80000>,
> +			      <0x00 0x4a600000 0x00 0x80000>,
> +			      <0x00 0x4a400000 0x00 0x80000>;
> +			interrupt-names = "rx_012";
> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +	};


Best regards,
Krzysztof

[PATCH 3/3] arm64: dts: ti: Add support for the AM62P5-SK

[Vignesh Raghavendra]

From: Bryan Brattlof <bb@ti.com>

Add basic support for the AM62P5-SK platform with UART and ramdisk as
rootfs.

Schematics is at https://www.ti.com/lit/zip/sprr487

Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 arch/arm64/boot/dts/ti/Makefile         |   3 +
 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 169 ++++++++++++++++++++++++
 2 files changed, 172 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 437a3d7e8e3a..5a09cad74c44 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -23,6 +23,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
 # Boards with AM62Ax SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
 
+# Boards with AM62Px SoC
+dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
+
 # Boards with AM64x SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
new file mode 100644
index 000000000000..b0882211448e
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for the AM62P5-SK
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Schematics: https://www.ti.com/lit/zip/sprr487
+ */
+
+/dts-v1/;
+
+#include "k3-am62p5.dtsi"
+
+/ {
+	compatible = "ti,am62p5-sk", "ti,am62p5";
+	model = "Texas Instruments AM62P5 SK";
+
+	aliases {
+		serial0 = &wkup_uart0;
+		serial2 = &main_uart0;
+		serial3 = &main_uart1;
+	};
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	memory@80000000 {
+		/* 8G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+		      <0x00000008 0x80000000 0x00000001 0x80000000>;
+		device_type = "memory";
+		bootph-pre-ram;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure_tfa_ddr: tfa@9e780000 {
+			reg = <0x00 0x9e780000 0x00 0x80000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0x9c900000 0x00 0x01e00000>;
+			no-map;
+		};
+	};
+};
+
+&cbass_main {
+	bootph-pre-ram;
+};
+
+&main_pmx0 {
+	status = "okay";
+	bootph-pre-ram;
+
+	main_uart0_pins_default: main-uart0-default-pins {
+		bootph-pre-ram;
+		pinctrl-single,pins = <
+			AM62PX_IOPAD(0x1c8, PIN_INPUT, 0)	/* (A22) UART0_RXD */
+			AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0)	/* (B22) UART0_TXD */
+			AM62PX_IOPAD(0x1d0, PIN_INPUT, 0)	/* (A23) UART0_CTSn */
+			AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0)	/* (C22) UART0_RTSn */
+		>;
+	};
+
+	main_uart1_pins_default: main-uart1-default-pins {
+		bootph-pre-ram;
+		pinctrl-single,pins = <
+			AM62PX_IOPAD(0x194, PIN_INPUT, 2)	/* (D25) MCASP0_AXR3 */
+			AM62PX_IOPAD(0x198, PIN_OUTPUT, 2)	/* (E25) MCASP0_AXR2 */
+			AM62PX_IOPAD(0x1ac, PIN_INPUT, 2)	/* (G23) MCASP0_AFSR */
+			AM62PX_IOPAD(0x1b0, PIN_OUTPUT, 2)	/* (G20) MCASP0_ACLKR */
+		>;
+	};
+};
+
+&main_timer0 {
+	bootph-pre-ram;
+};
+
+&main_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart0_pins_default>;
+	status = "okay";
+	bootph-pre-ram;
+};
+
+&main_uart1 {
+	/* Main UART1 is used by TIFS firmware */
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart1_pins_default>;
+	status = "reserved";
+	bootph-pre-ram;
+};
+
+&cbass_mcu {
+	bootph-pre-ram;
+};
+
+&mcu_pmx0 {
+	status = "okay";
+	bootph-pre-ram;
+
+	wkup_uart0_pins_default: wkup-uart0-default-pins {
+		bootph-pre-ram;
+		pinctrl-single,pins = <
+			AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0)	/* (C7) WKUP_UART0_CTSn */
+			AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0)	/* (C6) WKUP_UART0_RTSn */
+			AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (D8) WKUP_UART0_RXD */
+			AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (D7) WKUP_UART0_TXD */
+		>;
+	};
+};
+
+&cbass_wakeup {
+	bootph-pre-ram;
+};
+
+&wkup_uart0 {
+	/* WKUP UART0 is used by DM firmware */
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_uart0_pins_default>;
+	status = "reserved";
+	bootph-pre-ram;
+};
+
+&wkup_conf {
+	bootph-pre-ram;
+};
+
+&chipid {
+	bootph-pre-ram;
+};
+
+&dmss {
+	bootph-pre-ram;
+};
+
+&dmsc {
+	bootph-pre-ram;
+};
+
+&k3_pds {
+	bootph-pre-ram;
+};
+
+&k3_clks {
+	bootph-pre-ram;
+};
+
+&k3_reset {
+	bootph-pre-ram;
+};
+
+&secure_proxy_main {
+	bootph-pre-ram;
+};
-- 
2.41.0

Re: [PATCH 3/3] arm64: dts: ti: Add support for the AM62P5-SK

[Andrew Davis]

On 8/9/23 11:53 PM, Vignesh Raghavendra wrote:
> From: Bryan Brattlof <bb@ti.com>
> 
> Add basic support for the AM62P5-SK platform with UART and ramdisk as

We usually call the boards "SK-AM6xx", with the SK- first, assuming this
board is named the same way you should fix that here and in the files.

> rootfs.
> 
> Schematics is at https://www.ti.com/lit/zip/sprr487
> 
> Signed-off-by: Bryan Brattlof <bb@ti.com>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> ---
>   arch/arm64/boot/dts/ti/Makefile         |   3 +
>   arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 169 ++++++++++++++++++++++++
>   2 files changed, 172 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> 
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 437a3d7e8e3a..5a09cad74c44 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -23,6 +23,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
>   # Boards with AM62Ax SoC
>   dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
>   
> +# Boards with AM62Px SoC
> +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
> +
>   # Boards with AM64x SoC
>   dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
>   dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> new file mode 100644
> index 000000000000..b0882211448e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> @@ -0,0 +1,169 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree file for the AM62P5-SK
> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> + *
> + * Schematics: https://www.ti.com/lit/zip/sprr487
> + */
> +
> +/dts-v1/;
> +
> +#include "k3-am62p5.dtsi"
> +
> +/ {
> +	compatible = "ti,am62p5-sk", "ti,am62p5";
> +	model = "Texas Instruments AM62P5 SK";
> +
> +	aliases {
> +		serial0 = &wkup_uart0;
> +		serial2 = &main_uart0;
> +		serial3 = &main_uart1;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial2:115200n8";

You can set the path here directly to the node:

stdout-path = &main_uart0;

Then the default baud rate can be defined/selected in
the node with:

current-speed = <115200>;

> +	};
> +
> +	memory@80000000 {
> +		/* 8G RAM */
> +		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
> +		      <0x00000008 0x80000000 0x00000001 0x80000000>;
> +		device_type = "memory";
> +		bootph-pre-ram;
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		secure_tfa_ddr: tfa@9e780000 {
> +			reg = <0x00 0x9e780000 0x00 0x80000>;
> +			alignment = <0x1000>;

You cannot allocate from this memory, no need for alignment.

> +			no-map;
> +		};
> +
> +		secure_ddr: optee@9e800000 {
> +			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
> +			alignment = <0x1000>;

Same.

> +			no-map;
> +		};
> +
> +		wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x00 0x9c900000 0x00 0x01e00000>;
> +			no-map;
> +		};
> +	};
> +};
> +
> +&cbass_main {
> +	bootph-pre-ram;

I'm thinking we will need this for any AM62P based board, should
we bubble this up into the common .dtsi files? Same for most of the
other instances at the end of this file.

Andrew

> +};
> +
> +&main_pmx0 {
> +	status = "okay";
> +	bootph-pre-ram;
> +
> +	main_uart0_pins_default: main-uart0-default-pins {
> +		bootph-pre-ram;
> +		pinctrl-single,pins = <
> +			AM62PX_IOPAD(0x1c8, PIN_INPUT, 0)	/* (A22) UART0_RXD */
> +			AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0)	/* (B22) UART0_TXD */
> +			AM62PX_IOPAD(0x1d0, PIN_INPUT, 0)	/* (A23) UART0_CTSn */
> +			AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0)	/* (C22) UART0_RTSn */
> +		>;
> +	};
> +
> +	main_uart1_pins_default: main-uart1-default-pins {
> +		bootph-pre-ram;
> +		pinctrl-single,pins = <
> +			AM62PX_IOPAD(0x194, PIN_INPUT, 2)	/* (D25) MCASP0_AXR3 */
> +			AM62PX_IOPAD(0x198, PIN_OUTPUT, 2)	/* (E25) MCASP0_AXR2 */
> +			AM62PX_IOPAD(0x1ac, PIN_INPUT, 2)	/* (G23) MCASP0_AFSR */
> +			AM62PX_IOPAD(0x1b0, PIN_OUTPUT, 2)	/* (G20) MCASP0_ACLKR */
> +		>;
> +	};
> +};
> +
> +&main_timer0 {
> +	bootph-pre-ram;
> +};
> +
> +&main_uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&main_uart0_pins_default>;
> +	status = "okay";
> +	bootph-pre-ram;
> +};
> +
> +&main_uart1 {
> +	/* Main UART1 is used by TIFS firmware */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&main_uart1_pins_default>;
> +	status = "reserved";
> +	bootph-pre-ram;
> +};
> +
> +&cbass_mcu {
> +	bootph-pre-ram;
> +};
> +
> +&mcu_pmx0 {
> +	status = "okay";
> +	bootph-pre-ram;
> +
> +	wkup_uart0_pins_default: wkup-uart0-default-pins {
> +		bootph-pre-ram;
> +		pinctrl-single,pins = <
> +			AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0)	/* (C7) WKUP_UART0_CTSn */
> +			AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0)	/* (C6) WKUP_UART0_RTSn */
> +			AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (D8) WKUP_UART0_RXD */
> +			AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (D7) WKUP_UART0_TXD */
> +		>;
> +	};
> +};
> +
> +&cbass_wakeup {
> +	bootph-pre-ram;
> +};
> +
> +&wkup_uart0 {
> +	/* WKUP UART0 is used by DM firmware */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&wkup_uart0_pins_default>;
> +	status = "reserved";
> +	bootph-pre-ram;
> +};
> +
> +&wkup_conf {
> +	bootph-pre-ram;
> +};
> +
> +&chipid {
> +	bootph-pre-ram;
> +};
> +
> +&dmss {
> +	bootph-pre-ram;
> +};
> +
> +&dmsc {
> +	bootph-pre-ram;
> +};
> +
> +&k3_pds {
> +	bootph-pre-ram;
> +};
> +
> +&k3_clks {
> +	bootph-pre-ram;
> +};
> +
> +&k3_reset {
> +	bootph-pre-ram;
> +};
> +
> +&secure_proxy_main {
> +	bootph-pre-ram;
> +};

Re: [PATCH 3/3] arm64: dts: ti: Add support for the AM62P5-SK

[Vignesh Raghavendra]

On 11/08/23 02:49, Andrew Davis wrote:
> On 8/9/23 11:53 PM, Vignesh Raghavendra wrote:
>> From: Bryan Brattlof <bb@ti.com>
>>
>> Add basic support for the AM62P5-SK platform with UART and ramdisk as
> 
> We usually call the boards "SK-AM6xx", with the SK- first, assuming this

SK-AM62P-LP is the orderable part number but the silk screen reads AM62P
SK and so does the EEPROM Board_name field. So I am going just use that
in the bindings as well as file name similar have we have been naming so
far.


> board is named the same way you should fix that here and in the files.
> >> rootfs.
>>
>> Schematics is at https://www.ti.com/lit/zip/sprr487
>>
>> Signed-off-by: Bryan Brattlof <bb@ti.com>
>> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/Makefile         |   3 +
>>   arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 169 ++++++++++++++++++++++++
>>   2 files changed, 172 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
>>
>> diff --git a/arch/arm64/boot/dts/ti/Makefile
>> b/arch/arm64/boot/dts/ti/Makefile
>> index 437a3d7e8e3a..5a09cad74c44 100644
>> --- a/arch/arm64/boot/dts/ti/Makefile
>> +++ b/arch/arm64/boot/dts/ti/Makefile
>> @@ -23,6 +23,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
>>   # Boards with AM62Ax SoC
>>   dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
>>   +# Boards with AM62Px SoC
>> +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
>> +
>>   # Boards with AM64x SoC
>>   dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
>>   dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
>> b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
>> new file mode 100644
>> index 000000000000..b0882211448e
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
>> @@ -0,0 +1,169 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Device Tree file for the AM62P5-SK
>> + * Copyright (C) 2023 Texas Instruments Incorporated -
>> https://www.ti.com/
>> + *
>> + * Schematics: https://www.ti.com/lit/zip/sprr487
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "k3-am62p5.dtsi"
>> +
>> +/ {
>> +    compatible = "ti,am62p5-sk", "ti,am62p5";
>> +    model = "Texas Instruments AM62P5 SK";
>> +
>> +    aliases {
>> +        serial0 = &wkup_uart0;
>> +        serial2 = &main_uart0;
>> +        serial3 = &main_uart1;
>> +    };
>> +
>> +    chosen {
>> +        stdout-path = "serial2:115200n8";
> 
> You can set the path here directly to the node:
> 
> stdout-path = &main_uart0;
> 
> Then the default baud rate can be defined/selected in
> the node with:
> 
> current-speed = <115200>;
> 

Make sense...

>> +    };
>> +
>> +    memory@80000000 {
>> +        /* 8G RAM */
>> +        reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
>> +              <0x00000008 0x80000000 0x00000001 0x80000000>;
>> +        device_type = "memory";
>> +        bootph-pre-ram;
>> +    };
>> +
>> +    reserved-memory {
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +        ranges;
>> +
>> +        secure_tfa_ddr: tfa@9e780000 {
>> +            reg = <0x00 0x9e780000 0x00 0x80000>;
>> +            alignment = <0x1000>;
> 
> You cannot allocate from this memory, no need for alignment.
> 
>> +            no-map;
>> +        };
>> +
>> +        secure_ddr: optee@9e800000 {
>> +            reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
>> +            alignment = <0x1000>;
> 
> Same.
> 
>> +            no-map;
>> +        };
>> +
>> +        wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
>> +            compatible = "shared-dma-pool";
>> +            reg = <0x00 0x9c900000 0x00 0x01e00000>;
>> +            no-map;
>> +        };
>> +    };
>> +};
>> +
>> +&cbass_main {
>> +    bootph-pre-ram;
> 
> I'm thinking we will need this for any AM62P based board, should
> we bubble this up into the common .dtsi files? Same for most of the
> other instances at the end of this file.

will fill all the above. Thanks!

> 
> Andrew
> 
>> +};
>> +
>> +&main_pmx0 {
>> +    status = "okay";
>> +    bootph-pre-ram;
>> +
>> +    main_uart0_pins_default: main-uart0-default-pins {
>> +        bootph-pre-ram;
>> +        pinctrl-single,pins = <
>> +            AM62PX_IOPAD(0x1c8, PIN_INPUT, 0)    /* (A22) UART0_RXD */
>> +            AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0)    /* (B22) UART0_TXD */
>> +            AM62PX_IOPAD(0x1d0, PIN_INPUT, 0)    /* (A23) UART0_CTSn */
>> +            AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0)    /* (C22) UART0_RTSn */
>> +        >;
>> +    };
>> +
>> +    main_uart1_pins_default: main-uart1-default-pins {
>> +        bootph-pre-ram;
>> +        pinctrl-single,pins = <
>> +            AM62PX_IOPAD(0x194, PIN_INPUT, 2)    /* (D25) MCASP0_AXR3 */
>> +            AM62PX_IOPAD(0x198, PIN_OUTPUT, 2)    /* (E25)
>> MCASP0_AXR2 */
>> +            AM62PX_IOPAD(0x1ac, PIN_INPUT, 2)    /* (G23) MCASP0_AFSR */
>> +            AM62PX_IOPAD(0x1b0, PIN_OUTPUT, 2)    /* (G20)
>> MCASP0_ACLKR */
>> +        >;
>> +    };
>> +};
>> +
>> +&main_timer0 {
>> +    bootph-pre-ram;
>> +};
>> +
>> +&main_uart0 {
>> +    pinctrl-names = "default";
>> +    pinctrl-0 = <&main_uart0_pins_default>;
>> +    status = "okay";
>> +    bootph-pre-ram;
>> +};
>> +
>> +&main_uart1 {
>> +    /* Main UART1 is used by TIFS firmware */
>> +    pinctrl-names = "default";
>> +    pinctrl-0 = <&main_uart1_pins_default>;
>> +    status = "reserved";
>> +    bootph-pre-ram;
>> +};
>> +
>> +&cbass_mcu {
>> +    bootph-pre-ram;
>> +};
>> +
>> +&mcu_pmx0 {
>> +    status = "okay";
>> +    bootph-pre-ram;
>> +
>> +    wkup_uart0_pins_default: wkup-uart0-default-pins {
>> +        bootph-pre-ram;
>> +        pinctrl-single,pins = <
>> +            AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0)    /* (C7)
>> WKUP_UART0_CTSn */
>> +            AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0)    /* (C6)
>> WKUP_UART0_RTSn */
>> +            AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0)    /* (D8)
>> WKUP_UART0_RXD */
>> +            AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0)    /* (D7)
>> WKUP_UART0_TXD */
>> +        >;
>> +    };
>> +};
>> +
>> +&cbass_wakeup {
>> +    bootph-pre-ram;
>> +};
>> +
>> +&wkup_uart0 {
>> +    /* WKUP UART0 is used by DM firmware */
>> +    pinctrl-names = "default";
>> +    pinctrl-0 = <&wkup_uart0_pins_default>;
>> +    status = "reserved";
>> +    bootph-pre-ram;
>> +};
>> +
>> +&wkup_conf {
>> +    bootph-pre-ram;
>> +};
>> +
>> +&chipid {
>> +    bootph-pre-ram;
>> +};
>> +
>> +&dmss {
>> +    bootph-pre-ram;
>> +};
>> +
>> +&dmsc {
>> +    bootph-pre-ram;
>> +};
>> +
>> +&k3_pds {
>> +    bootph-pre-ram;
>> +};
>> +
>> +&k3_clks {
>> +    bootph-pre-ram;
>> +};
>> +
>> +&k3_reset {
>> +    bootph-pre-ram;
>> +};
>> +
>> +&secure_proxy_main {
>> +    bootph-pre-ram;
>> +};

-- 
Regards
Vignesh

Re: [PATCH 0/3] arm64: dts: ti: Introduce AM62P SoCs

[Dhruva Gole]

On Aug 10, 2023 at 10:23:11 +0530, Vignesh Raghavendra wrote:
> This series adds basic support for AM62P family of SoCs and specifically
> AM62P5 variant. Also adds AM62P5-SK EVM support with basic peripheral
> like UART.

Thanks for posting this upstream! Series looks good to me.

> 
> TRM at [0] and Schematics is at [1]
> 
> [0]: https://www.ti.com/lit/pdf/spruj83
> [1]: https://www.ti.com/lit/zip/sprr487
> 
> Bryan Brattlof (3):
>   dt-bindings: arm: ti: Add bindings for AM62P5 SoCs
>   arm64: dts: ti: Introduce AM62P5 family of SoCs
>   arm64: dts: ti: Add support for the AM62P5-SK
> 
>  .../devicetree/bindings/arm/ti/k3.yaml        |   6 +
>  arch/arm64/boot/dts/ti/Makefile               |   3 +
>  arch/arm64/boot/dts/ti/k3-am62p-main.dtsi     | 129 +++++++++++++
>  arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi      |  16 ++
>  arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi   |  30 ++++
>  arch/arm64/boot/dts/ti/k3-am62p.dtsi          | 109 +++++++++++
>  arch/arm64/boot/dts/ti/k3-am62p5-sk.dts       | 169 ++++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am62p5.dtsi         | 107 +++++++++++
>  arch/arm64/boot/dts/ti/k3-pinctrl.h           |   3 +

For the series,

Reviewed-by: Dhruva Gole <d-gole@ti.com>

>  9 files changed, 572 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am62p.dtsi
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5.dtsi
> 
> -- 
> 2.41.0
> 
> 

-- 
Best regards,
Dhruva Gole <d-gole@ti.com>

Re: [PATCH 0/3] arm64: dts: ti: Introduce AM62P SoCs

[Nishanth Menon]

On 10:23-20230810, Vignesh Raghavendra wrote:
> This series adds basic support for AM62P family of SoCs and specifically
> AM62P5 variant. Also adds AM62P5-SK EVM support with basic peripheral
> like UART.
> 
> TRM at [0] and Schematics is at [1]
> 
> [0]: https://www.ti.com/lit/pdf/spruj83
> [1]: https://www.ti.com/lit/zip/sprr487
> 

Can you share a bootlog?

> Bryan Brattlof (3):
>   dt-bindings: arm: ti: Add bindings for AM62P5 SoCs
>   arm64: dts: ti: Introduce AM62P5 family of SoCs
>   arm64: dts: ti: Add support for the AM62P5-SK
> 
>  .../devicetree/bindings/arm/ti/k3.yaml        |   6 +
>  arch/arm64/boot/dts/ti/Makefile               |   3 +
>  arch/arm64/boot/dts/ti/k3-am62p-main.dtsi     | 129 +++++++++++++
>  arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi      |  16 ++
>  arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi   |  30 ++++
>  arch/arm64/boot/dts/ti/k3-am62p.dtsi          | 109 +++++++++++
>  arch/arm64/boot/dts/ti/k3-am62p5-sk.dts       | 169 ++++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am62p5.dtsi         | 107 +++++++++++
>  arch/arm64/boot/dts/ti/k3-pinctrl.h           |   3 +




-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D