From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E60BC001B0 for ; Fri, 11 Aug 2023 15:34:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229568AbjHKPez (ORCPT ); Fri, 11 Aug 2023 11:34:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230509AbjHKPew (ORCPT ); Fri, 11 Aug 2023 11:34:52 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5465030FC; Fri, 11 Aug 2023 08:34:40 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E854261044; Fri, 11 Aug 2023 15:34:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4FA4C433C8; Fri, 11 Aug 2023 15:34:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1691768079; bh=r3PGtOgGMhkDijdv+iZVGveDNuPb4HD9QD/+iFIfZYM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=VCl3cPD8dgdIUONQxajxeQQgRrlu1YgPEm+SYDUJk01vLAZIbHIIAWMubcho9PGLK K+ydgi3DaBDyvwiwiX3k3bdVfrNIbrCR61N3oTIx9n3AZbVXWy/cWO9F+x2jPBkgqw Qxm4p4FoGvTXvB9Jx/1iAMeZKqgBivx6dfMeVfY1HgRLWHEuEvQqMQJ8q++3YifJYK hhF/CC4jFkpZ3pZ61RJQw1+MwomN6gkJxqmTuBKsy3nz1Hx26BOH+1+vZYIoC9wa9H 3kUmxgBdwIUtDDuQZOLWE8oa4avDf3up6Nne0WtTKzIfjW87BdJ90p9fsJD553ygg2 UyHpB6r03DLyQ== Date: Fri, 11 Aug 2023 16:34:33 +0100 From: Conor Dooley To: Kamlesh Gurudasani Cc: Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Catalin Marinas , Will Deacon , Maxime Coquelin , Alexandre Torgue , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: Re: [PATCH v2 3/6] dt-bindings: crypto: Add Texas Instruments MCRC64 Message-ID: <20230811-crestless-gratify-21c9bb422375@spud> References: <20230719-mcrc-upstream-v2-0-4152b987e4c2@ti.com> <20230719-mcrc-upstream-v2-3-4152b987e4c2@ti.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="4VYflVWwOKTpj1iN" Content-Disposition: inline In-Reply-To: <20230719-mcrc-upstream-v2-3-4152b987e4c2@ti.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org --4VYflVWwOKTpj1iN Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Aug 11, 2023 at 12:58:50AM +0530, Kamlesh Gurudasani wrote: > Add binding for Texas Instruments MCRC64 >=20 > MCRC64 engine calculates 64-bit cyclic redundancy checks (CRC) > according to the ISO 3309 standard. >=20 > The ISO 3309 64-bit CRC model parameters are as follows: > Generator Polynomial: x^64 + x^4 + x^3 + x + 1 > Polynomial Value: 0x000000000000001B > Initial value: 0x0000000000000000 > Reflected Input: False > Reflected Output: False > Xor Final: 0x0000000000000000 >=20 > Signed-off-by: Kamlesh Gurudasani > --- > Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml | 47 +++++++++++= ++++++++++++++++++++++++++++++++++++ > MAINTAINERS | 5 +++++ > 2 files changed, 52 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml b/Do= cumentation/devicetree/bindings/crypto/ti,mcrc64.yaml > new file mode 100644 > index 000000000000..38bc7efebd68 > --- /dev/null > +++ b/Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml > @@ -0,0 +1,47 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/crypto/ti,mcrc64.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Texas Instruments MCRC64 > + > +description: The MCRC64 engine calculates 64-bit cyclic redundancy checks A newline after "description" please. > + (CRC) according to the ISO 3309 standard. > + > +maintainers: > + - Kamlesh Gurudasani > + > +properties: > + compatible: > + const: ti,am62-mcrc64 Is the am62 an SoC or a family of SoCs? I googled a wee bit for am62 & there seems to be an am625 and an am623? Otherwise, this looks good to me. > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + crc@30300000 { > + compatible =3D "ti,am62-mcrc64"; > + reg =3D <0x30300000 0x1000>; > + clocks =3D <&k3_clks 116 0>; > + power-domains =3D <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; > + }; > + > +... > diff --git a/MAINTAINERS b/MAINTAINERS > index 02a3192195af..66b51f43d196 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -21481,6 +21481,11 @@ S: Maintained > F: Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml > F: drivers/iio/adc/ti-lmp92064.c > =20 > +TI MEMORY CYCLIC REDUNDANCY CHECK (MCRC64) DRIVER > +M: Kamlesh Gurudasani > +S: Maintained > +F: Documentation/devicetree/bindings/crypto/ti,mcrc64.yaml > + > TI PCM3060 ASoC CODEC DRIVER > M: Kirill Marinushkin > L: alsa-devel@alsa-project.org (moderated for non-subscribers) >=20 > --=20 > 2.34.1 >=20 --4VYflVWwOKTpj1iN Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZNZVCQAKCRB4tDGHoIJi 0n5RAP97iRCzLqZPNVjEVkEGcarsRXECumq3U8b3igybE6JXhgD+Kb1DanuELAIb I7R1WODmew1XCk2Elgnp/H8EOq2KKAA= =2dLk -----END PGP SIGNATURE----- --4VYflVWwOKTpj1iN--