* [PATCH v15 1/6] dt-bindings: arm: add AMD Pensando boards
2023-08-11 18:05 [PATCH v15 0/6] Support AMD Pensando Elba SoC Brad Larson
@ 2023-08-11 18:05 ` Brad Larson
2023-08-11 18:05 ` [PATCH v15 2/6] dt-bindings: soc: amd: amd,pensando-elba-ctrl: Add Pensando SoC Controller Brad Larson
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Brad Larson @ 2023-08-11 18:05 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, linux-mmc, linux-spi, adrian.hunter, alcooperx,
andy.shevchenko, arnd, blarson, brendan.higgins, briannorris,
catalin.marinas, conor+dt, davidgow, gsomlo, gerg, hal.feng,
hasegawa-hitomi, j.neuschaefer, joel, kernel, krzk,
krzysztof.kozlowski+dt, lee, lee.jones, broonie, p.zabel, rdunlap,
robh+dt, samuel, fancer.lancer, skhan, suravee.suthikulpanit,
thomas.lendacky, tonyhuang.sunplus, ulf.hansson, vaishnav.a,
walker.chen, will, zhuyinbo, devicetree
Document the compatible for AMD Pensando Elba SoC boards.
Signed-off-by: Brad Larson <blarson@amd.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/arm/amd,pensando.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/amd,pensando.yaml
diff --git a/Documentation/devicetree/bindings/arm/amd,pensando.yaml b/Documentation/devicetree/bindings/arm/amd,pensando.yaml
new file mode 100644
index 000000000000..e5c2591834a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/amd,pensando.yaml
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/amd,pensando.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AMD Pensando SoC Platforms
+
+maintainers:
+ - Brad Larson <blarson@amd.com>
+
+properties:
+ $nodename:
+ const: "/"
+ compatible:
+ oneOf:
+
+ - description: Boards with Pensando Elba SoC
+ items:
+ - enum:
+ - amd,pensando-elba-ortano
+ - const: amd,pensando-elba
+
+additionalProperties: true
+
+...
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v15 2/6] dt-bindings: soc: amd: amd,pensando-elba-ctrl: Add Pensando SoC Controller
2023-08-11 18:05 [PATCH v15 0/6] Support AMD Pensando Elba SoC Brad Larson
2023-08-11 18:05 ` [PATCH v15 1/6] dt-bindings: arm: add AMD Pensando boards Brad Larson
@ 2023-08-11 18:05 ` Brad Larson
2023-08-11 18:05 ` [PATCH v15 3/6] MAINTAINERS: Add entry for AMD PENSANDO Brad Larson
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Brad Larson @ 2023-08-11 18:05 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, linux-mmc, linux-spi, adrian.hunter, alcooperx,
andy.shevchenko, arnd, blarson, brendan.higgins, briannorris,
catalin.marinas, conor+dt, davidgow, gsomlo, gerg, hal.feng,
hasegawa-hitomi, j.neuschaefer, joel, kernel, krzk,
krzysztof.kozlowski+dt, lee, lee.jones, broonie, p.zabel, rdunlap,
robh+dt, samuel, fancer.lancer, skhan, suravee.suthikulpanit,
thomas.lendacky, tonyhuang.sunplus, ulf.hansson, vaishnav.a,
walker.chen, will, zhuyinbo, devicetree
Support the AMD Pensando Elba SoC Controller which is a SPI connected
device providing a miscellaneous set of essential board control/status
registers. This device is present in all Pensando SoC based designs.
Signed-off-by: Brad Larson <blarson@amd.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
v14 changes:
- Change GPL-2.0-only or BSD-2-Clause to GPL-2.0-only OR BSD-2-Clause
v11 changes:
- Fixed the compatible which should have stayed as 'amd,pensando-elba-ctrl',
the commit message, and the filename
- Reference spi-peripheral-props
- Delete spi-max-frequency
- Remove num-cs from example
v10 changes:
- Property renamed to amd,pensando-ctrl
- Driver is renamed and moved to soc/drivers/amd affecting binding
- Delete cs property, driver handles device node creation from parent num-cs
fixing schema reg error in a different way
v9 changes:
- Instead of four nodes, one per chip-select, a single
node is used with reset-cells in the parent.
- No MFD API is used anymore in the driver so it made
sense to move this to drivers/spi.
- This driver is common for all Pensando SoC based designs
so changed the name to pensando-sr.c to not make it Elba
SoC specific.
- Added property cs for the chip-select number which is used
by the driver to create /dev/pensr0.<cs>
---
.../soc/amd/amd,pensando-elba-ctrl.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml
diff --git a/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml
new file mode 100644
index 000000000000..e96978ad1e37
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/amd/amd,pensando-elba-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AMD Pensando Elba SoC Controller
+
+description:
+ The AMD Pensando Elba SoC Controller is a SPI connected device with essential
+ control/status registers accessed on chip select 0. This device is present
+ in all Pensando SoC based designs.
+
+maintainers:
+ - Brad Larson <blarson@amd.com>
+
+properties:
+ compatible:
+ enum:
+ - amd,pensando-elba-ctrl
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - '#reset-cells'
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ system-controller@0 {
+ compatible = "amd,pensando-elba-ctrl";
+ reg = <0>;
+ spi-max-frequency = <12000000>;
+ interrupt-parent = <&porta>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ #reset-cells = <1>;
+ };
+ };
+
+...
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v15 3/6] MAINTAINERS: Add entry for AMD PENSANDO
2023-08-11 18:05 [PATCH v15 0/6] Support AMD Pensando Elba SoC Brad Larson
2023-08-11 18:05 ` [PATCH v15 1/6] dt-bindings: arm: add AMD Pensando boards Brad Larson
2023-08-11 18:05 ` [PATCH v15 2/6] dt-bindings: soc: amd: amd,pensando-elba-ctrl: Add Pensando SoC Controller Brad Larson
@ 2023-08-11 18:05 ` Brad Larson
2023-08-11 18:05 ` [PATCH v15 4/6] arm64: Add config for AMD Pensando SoC platforms Brad Larson
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Brad Larson @ 2023-08-11 18:05 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, linux-mmc, linux-spi, adrian.hunter, alcooperx,
andy.shevchenko, arnd, blarson, brendan.higgins, briannorris,
catalin.marinas, conor+dt, davidgow, gsomlo, gerg, hal.feng,
hasegawa-hitomi, j.neuschaefer, joel, kernel, krzk,
krzysztof.kozlowski+dt, lee, lee.jones, broonie, p.zabel, rdunlap,
robh+dt, samuel, fancer.lancer, skhan, suravee.suthikulpanit,
thomas.lendacky, tonyhuang.sunplus, ulf.hansson, vaishnav.a,
walker.chen, will, zhuyinbo, devicetree
Add entry for AMD PENSANDO maintainer and files
Signed-off-by: Brad Larson <blarson@amd.com>
---
MAINTAINERS | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3be1bdfe8ecc..fdff6b0ca0d7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1804,6 +1804,16 @@ N: allwinner
N: sun[x456789]i
N: sun[25]0i
+ARM/AMD PENSANDO ARM64 ARCHITECTURE
+M: Brad Larson <blarson@amd.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Supported
+F: Documentation/devicetree/bindings/*/amd,pensando*
+F: Documentation/devicetree/bindings/soc/amd/amd,pensando*
+F: arch/arm64/boot/dts/amd/elba*
+F: drivers/soc/amd/
+F: include/uapi/linux/amd-pensando*
+
ARM/Amlogic Meson SoC CLOCK FRAMEWORK
M: Neil Armstrong <neil.armstrong@linaro.org>
M: Jerome Brunet <jbrunet@baylibre.com>
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v15 4/6] arm64: Add config for AMD Pensando SoC platforms
2023-08-11 18:05 [PATCH v15 0/6] Support AMD Pensando Elba SoC Brad Larson
` (2 preceding siblings ...)
2023-08-11 18:05 ` [PATCH v15 3/6] MAINTAINERS: Add entry for AMD PENSANDO Brad Larson
@ 2023-08-11 18:05 ` Brad Larson
2023-08-14 8:40 ` Jonathan Neuschäfer
2023-08-11 18:05 ` [PATCH v15 5/6] arm64: dts: Add AMD Pensando Elba SoC support Brad Larson
2023-08-11 18:05 ` [PATCH v15 6/6] soc: amd: Add support for AMD Pensando SoC Controller Brad Larson
5 siblings, 1 reply; 9+ messages in thread
From: Brad Larson @ 2023-08-11 18:05 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, linux-mmc, linux-spi, adrian.hunter, alcooperx,
andy.shevchenko, arnd, blarson, brendan.higgins, briannorris,
catalin.marinas, conor+dt, davidgow, gsomlo, gerg, hal.feng,
hasegawa-hitomi, j.neuschaefer, joel, kernel, krzk,
krzysztof.kozlowski+dt, lee, lee.jones, broonie, p.zabel, rdunlap,
robh+dt, samuel, fancer.lancer, skhan, suravee.suthikulpanit,
thomas.lendacky, tonyhuang.sunplus, ulf.hansson, vaishnav.a,
walker.chen, will, zhuyinbo, devicetree
Add ARCH_PENSANDO configuration option for AMD Pensando SoC
based platforms.
Signed-off-by: Brad Larson <blarson@amd.com>
---
arch/arm64/Kconfig.platforms | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6069120199bb..9d09a1cc15ee 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -244,6 +244,18 @@ config ARCH_NPCM
General support for NPCM8xx BMC (Arbel).
Nuvoton NPCM8xx BMC based on the Cortex A35.
+config ARCH_PENSANDO
+ bool "AMD Pensando Platforms"
+ help
+ This enables support for the ARMv8 based AMD Pensando SoC
+ family to include the Elba SoC.
+
+ AMD Pensando SoCs support a range of Distributed Services
+ Cards in PCIe format installed into servers. The Elba
+ SoC includes 16 A-72 CPU cores, 144 programmable P4
+ cores for a minimal latency/jitter datapath, and network
+ interfaces up to 200 Gb/s.
+
config ARCH_QCOM
bool "Qualcomm Platforms"
select GPIOLIB
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v15 4/6] arm64: Add config for AMD Pensando SoC platforms
2023-08-11 18:05 ` [PATCH v15 4/6] arm64: Add config for AMD Pensando SoC platforms Brad Larson
@ 2023-08-14 8:40 ` Jonathan Neuschäfer
2023-08-16 1:22 ` Brad Larson
0 siblings, 1 reply; 9+ messages in thread
From: Jonathan Neuschäfer @ 2023-08-14 8:40 UTC (permalink / raw)
To: Brad Larson
Cc: linux-arm-kernel, linux-kernel, linux-mmc, linux-spi,
adrian.hunter, alcooperx, andy.shevchenko, arnd, brendan.higgins,
briannorris, catalin.marinas, conor+dt, davidgow, gsomlo, gerg,
hal.feng, hasegawa-hitomi, j.neuschaefer, joel, kernel, krzk,
krzysztof.kozlowski+dt, lee, lee.jones, broonie, p.zabel, rdunlap,
robh+dt, samuel, fancer.lancer, skhan, suravee.suthikulpanit,
thomas.lendacky, tonyhuang.sunplus, ulf.hansson, vaishnav.a,
walker.chen, will, zhuyinbo, devicetree
[-- Attachment #1: Type: text/plain, Size: 1048 bytes --]
On Fri, Aug 11, 2023 at 11:05:17AM -0700, Brad Larson wrote:
> Add ARCH_PENSANDO configuration option for AMD Pensando SoC
> based platforms.
>
> Signed-off-by: Brad Larson <blarson@amd.com>
> ---
[...]
> +config ARCH_PENSANDO
> + bool "AMD Pensando Platforms"
> + help
> + This enables support for the ARMv8 based AMD Pensando SoC
> + family to include the Elba SoC.
> +
> + AMD Pensando SoCs support a range of Distributed Services
> + Cards in PCIe format installed into servers. The Elba
> + SoC includes 16 A-72 CPU cores, 144 programmable P4
> + cores for a minimal latency/jitter datapath, and network
Out of curiosity, what are A-72 and P4?
A-72 sounds like Arm Cortex A-72, P4 seems to refer to the P4
programming language (https://opennetworking.org/p4/).
Perhaps something like:
+ Cards in PCIe format installed into servers. The Elba
+ SoC includes 16 Cortex A-72 CPU cores, 144 P4-programmable
+ cores for a minimal latency/jitter datapath, and network
Best regards,
Jonathan
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v15 4/6] arm64: Add config for AMD Pensando SoC platforms
2023-08-14 8:40 ` Jonathan Neuschäfer
@ 2023-08-16 1:22 ` Brad Larson
0 siblings, 0 replies; 9+ messages in thread
From: Brad Larson @ 2023-08-16 1:22 UTC (permalink / raw)
To: j.neuschaefer
Cc: adrian.hunter, alcooperx, andy.shevchenko, arnd, blarson,
brendan.higgins, briannorris, broonie, catalin.marinas, conor+dt,
davidgow, devicetree, fancer.lancer, gerg, gsomlo, hal.feng,
hasegawa-hitomi, joel, kernel, krzk, krzysztof.kozlowski+dt,
lee.jones, lee, linux-arm-kernel, linux-kernel, linux-mmc,
linux-spi, p.zabel, rdunlap, robh+dt, samuel, skhan,
suravee.suthikulpanit, thomas.lendacky, tonyhuang.sunplus,
ulf.hansson, vaishnav.a, walker.chen, will, zhuyinbo
Hi Jonathan,
On Mon, Aug 14, 2023 at 10:40:17 +0200, Jonathan Neuschäfer wrote:
> On Fri, Aug 11, 2023 at 11:05:17AM -0700, Brad Larson wrote:
>> Add ARCH_PENSANDO configuration option for AMD Pensando SoC
>> based platforms.
>>
>> Signed-off-by: Brad Larson <blarson@amd.com>
>> ---
> [...]
>> +config ARCH_PENSANDO
>> + bool "AMD Pensando Platforms"
>> + help
>> + This enables support for the ARMv8 based AMD Pensando SoC
>> + family to include the Elba SoC.
>> +
>> + AMD Pensando SoCs support a range of Distributed Services
>> + Cards in PCIe format installed into servers. The Elba
>> + SoC includes 16 A-72 CPU cores, 144 programmable P4
>> + cores for a minimal latency/jitter datapath, and network
>
> Out of curiosity, what are A-72 and P4?
>
> A-72 sounds like Arm Cortex A-72, P4 seems to refer to the P4
> programming language (https://opennetworking.org/p4/).
>
> Perhaps something like:
>
>+ Cards in PCIe format installed into servers. The Elba
>+ SoC includes 16 Cortex A-72 CPU cores, 144 P4-programmable
>+ cores for a minimal latency/jitter datapath, and network
Thanks for the review! Yes, exactly. I'll add that change which
makes the description more precise.
Regards,
Brad
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v15 5/6] arm64: dts: Add AMD Pensando Elba SoC support
2023-08-11 18:05 [PATCH v15 0/6] Support AMD Pensando Elba SoC Brad Larson
` (3 preceding siblings ...)
2023-08-11 18:05 ` [PATCH v15 4/6] arm64: Add config for AMD Pensando SoC platforms Brad Larson
@ 2023-08-11 18:05 ` Brad Larson
2023-08-11 18:05 ` [PATCH v15 6/6] soc: amd: Add support for AMD Pensando SoC Controller Brad Larson
5 siblings, 0 replies; 9+ messages in thread
From: Brad Larson @ 2023-08-11 18:05 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, linux-mmc, linux-spi, adrian.hunter, alcooperx,
andy.shevchenko, arnd, blarson, brendan.higgins, briannorris,
catalin.marinas, conor+dt, davidgow, gsomlo, gerg, hal.feng,
hasegawa-hitomi, j.neuschaefer, joel, kernel, krzk,
krzysztof.kozlowski+dt, lee, lee.jones, broonie, p.zabel, rdunlap,
robh+dt, samuel, fancer.lancer, skhan, suravee.suthikulpanit,
thomas.lendacky, tonyhuang.sunplus, ulf.hansson, vaishnav.a,
walker.chen, will, zhuyinbo, devicetree
Add AMD Pensando common and Elba SoC specific device nodes
Signed-off-by: Brad Larson <blarson@amd.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
v15 changes:
- The first cell in the cpu reg property is always zero. Change
address-cells to <1> and dropped the leading zero from all cpu* reg<>
- Added read-only and spare partitions to flash0
v14 changes:
- Fix dtbs_check l2-cache* property issue by adding required
cache-level and cache-unified properties
- Observed the issue after updating dtschema from 2023.1 to 2023.4
and yamllint from 1.26.3 to 1.30.0
v11 changes:
- Delete reset-names
- Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl'
v9 changes:
- Single node for spi0 system-controller and squash
the reset-controller child into parent
---
arch/arm64/boot/dts/amd/Makefile | 1 +
arch/arm64/boot/dts/amd/elba-16core.dtsi | 197 ++++++++++++++++++
arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 +++++++
arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++
arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 117 +++++++++++
arch/arm64/boot/dts/amd/elba.dtsi | 191 +++++++++++++++++
6 files changed, 614 insertions(+)
create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts
create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi
diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile
index 68103a8b0ef5..8502cc2afbc5 100644
--- a/arch/arm64/boot/dts/amd/Makefile
+++ b/arch/arm64/boot/dts/amd/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb
dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb
diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi
new file mode 100644
index 000000000000..568bcc39ce9f
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2023 Advanced Micro Devices, Inc.
+ */
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 { cpu = <&cpu0>; };
+ core1 { cpu = <&cpu1>; };
+ core2 { cpu = <&cpu2>; };
+ core3 { cpu = <&cpu3>; };
+ };
+
+ cluster1 {
+ core0 { cpu = <&cpu4>; };
+ core1 { cpu = <&cpu5>; };
+ core2 { cpu = <&cpu6>; };
+ core3 { cpu = <&cpu7>; };
+ };
+
+ cluster2 {
+ core0 { cpu = <&cpu8>; };
+ core1 { cpu = <&cpu9>; };
+ core2 { cpu = <&cpu10>; };
+ core3 { cpu = <&cpu11>; };
+ };
+
+ cluster3 {
+ core0 { cpu = <&cpu12>; };
+ core1 { cpu = <&cpu13>; };
+ core2 { cpu = <&cpu14>; };
+ core3 { cpu = <&cpu15>; };
+ };
+ };
+
+ /* CLUSTER 0 */
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x1>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x2>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x3>;
+ next-level-cache = <&l2_0>;
+ enable-method = "psci";
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ /* CLUSTER 1 */
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x100>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x101>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x102>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x103>;
+ next-level-cache = <&l2_1>;
+ enable-method = "psci";
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ /* CLUSTER 2 */
+ cpu8: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x200>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ cpu9: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x201>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ cpu10: cpu@202 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x202>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ cpu11: cpu@203 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x203>;
+ next-level-cache = <&l2_2>;
+ enable-method = "psci";
+ };
+
+ l2_2: l2-cache2 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ /* CLUSTER 3 */
+ cpu12: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x300>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ cpu13: cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x301>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ cpu14: cpu@302 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x302>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ cpu15: cpu@303 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x303>;
+ next-level-cache = <&l2_3>;
+ enable-method = "psci";
+ };
+
+ l2_3: l2-cache3 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi
new file mode 100644
index 000000000000..1a615788f54e
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+&ahb_clk {
+ clock-frequency = <400000000>;
+};
+
+&emmc_clk {
+ clock-frequency = <200000000>;
+};
+
+&flash_clk {
+ clock-frequency = <400000000>;
+};
+
+&ref_clk {
+ clock-frequency = <156250000>;
+};
+
+&qspi {
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-rx-bus-width = <2>;
+ m25p,fast-read;
+ cdns,read-delay = <0>;
+ cdns,tshsl-ns = <0>;
+ cdns,tsd2d-ns = <0>;
+ cdns,tchsh-ns = <0>;
+ cdns,tslch-ns = <0>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ resets = <&rstc 0>;
+ status = "okay";
+};
+
+&wdt0 {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf85263";
+ reg = <0x51>;
+ };
+};
+
+&spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <4>;
+ cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>,
+ <&porta 7 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ rstc: system-controller@0 {
+ compatible = "amd,pensando-elba-ctrl";
+ reg = <0>;
+ spi-max-frequency = <12000000>;
+ interrupt-parent = <&porta>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ #reset-cells = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts
new file mode 100644
index 000000000000..c3f4da2f7449
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-asic.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Device Tree file for AMD Pensando Elba Board.
+ *
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+/dts-v1/;
+
+#include "elba.dtsi"
+#include "elba-16core.dtsi"
+#include "elba-asic-common.dtsi"
+#include "elba-flash-parts.dtsi"
+
+/ {
+ model = "AMD Pensando Elba Board";
+ compatible = "amd,pensando-elba-ortano", "amd,pensando-elba";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ spi1 = &qspi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
new file mode 100644
index 000000000000..9bffdf23511f
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+&flash0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "rsvd";
+ reg = <0x0 0x10000>;
+ read-only;
+ };
+
+ partition@10000 {
+ label = "flash";
+ reg = <0x10000 0xfff0000>;
+ };
+
+ partition@f0000 {
+ label = "golduenv";
+ reg = <0xf0000 0x10000>;
+ };
+
+ partition@100000 {
+ label = "boot0";
+ reg = <0x100000 0x80000>;
+ };
+
+ partition@180000 {
+ label = "golduboot";
+ reg = <0x180000 0x200000>;
+ };
+
+ partition@380000 {
+ label = "brdcfg0";
+ reg = <0x380000 0x10000>;
+ };
+
+ partition@390000 {
+ label = "brdcfg1";
+ reg = <0x390000 0x10000>;
+ };
+
+ partition@400000 {
+ label = "goldfw";
+ reg = <0x400000 0x3c00000>;
+ };
+
+ partition@4010000 {
+ label = "fwmap";
+ reg = <0x4010000 0x20000>;
+ };
+
+ partition@4030000 {
+ label = "fwsel";
+ reg = <0x4030000 0x20000>;
+ };
+
+ partition@4090000 {
+ label = "bootlog";
+ reg = <0x4090000 0x20000>;
+ };
+
+ partition@40b0000 {
+ label = "panicbuf";
+ reg = <0x40b0000 0x20000>;
+ };
+
+ partition@40d0000 {
+ label = "uservars";
+ reg = <0x40d0000 0x20000>;
+ };
+
+ partition@4200000 {
+ label = "uboota";
+ reg = <0x4200000 0x400000>;
+ };
+
+ partition@4600000 {
+ label = "ubootb";
+ reg = <0x4600000 0x400000>;
+ };
+
+ partition@4a00000 {
+ label = "mainfwa";
+ reg = <0x4a00000 0x1000000>;
+ };
+
+ partition@5a00000 {
+ label = "mainfwb";
+ reg = <0x5a00000 0x1000000>;
+ };
+
+ partition@6a00000 {
+ label = "diaguboot";
+ reg = <0x6a00000 0x400000>;
+ };
+
+ partition@6e00000 {
+ label = "spare";
+ reg = <0x6e00000 0x1200000>;
+ };
+
+ partition@8000000 {
+ label = "diagfw";
+ reg = <0x8000000 0x7fe0000>;
+ };
+
+ partition@ffe0000 {
+ label = "ubootenv";
+ reg = <0xffe0000 0x10000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi
new file mode 100644
index 000000000000..674890cf2a34
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/elba.dtsi
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+/*
+ * Copyright 2020-2022 Advanced Micro Devices, Inc.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "dt-bindings/interrupt-controller/arm-gic.h"
+
+/ {
+ model = "Elba ASIC Board";
+ compatible = "amd,pensando-elba";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dma-coherent;
+
+ ahb_clk: oscillator0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ emmc_clk: oscillator2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ flash_clk: oscillator3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ ref_clk: oscillator4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ i2c0: i2c@400 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x400 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-sda-hold-time-ns = <480>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@1400 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x1400 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ qspi: spi@2400 {
+ compatible = "amd,pensando-elba-qspi", "cdns,qspi-nor";
+ reg = <0x0 0x2400 0x0 0x400>,
+ <0x0 0x7fff0000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&flash_clk>;
+ cdns,fifo-depth = <1024>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x7fff0000>;
+ status = "disabled";
+ };
+
+ spi0: spi@2800 {
+ compatible = "amd,pensando-elba-spi";
+ reg = <0x0 0x2800 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ amd,pensando-elba-syscon = <&syscon>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <2>;
+ status = "disabled";
+ };
+
+ gpio0: gpio@4000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x0 0x4000 0x0 0x78>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ porta: gpio-port@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ };
+
+ portb: gpio-port@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ };
+ };
+
+ uart0: serial@4800 {
+ compatible = "ns16550a";
+ reg = <0x0 0x4800 0x0 0x100>;
+ clocks = <&ref_clk>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ gic: interrupt-controller@800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x800000 0x0 0x200000>, /* GICD */
+ <0x0 0xa00000 0x0 0x200000>, /* GICR */
+ <0x0 0x60000000 0x0 0x2000>, /* GICC */
+ <0x0 0x60010000 0x0 0x1000>, /* GICH */
+ <0x0 0x60020000 0x0 0x2000>; /* GICV */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #interrupt-cells = <3>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ /*
+ * Elba specific pre-ITS is enabled using the
+ * existing property socionext,synquacer-pre-its
+ */
+ gic_its: msi-controller@820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x820000 0x0 0x10000>;
+ msi-controller;
+ #msi-cells = <1>;
+ socionext,synquacer-pre-its =
+ <0xc00000 0x1000000>;
+ };
+ };
+
+ emmc: mmc@30440000 {
+ compatible = "amd,pensando-elba-sd4hc", "cdns,sd4hc";
+ reg = <0x0 0x30440000 0x0 0x10000>,
+ <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */
+ clocks = <&emmc_clk>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,phy-input-delay-sd-highspeed = <0x4>;
+ cdns,phy-input-delay-legacy = <0x4>;
+ cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>;
+ cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
+ mmc-ddr-1_8v;
+ status = "disabled";
+ };
+
+ syscon: syscon@307c0000 {
+ compatible = "amd,pensando-elba-syscon", "syscon";
+ reg = <0x0 0x307c0000 0x0 0x3000>;
+ };
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v15 6/6] soc: amd: Add support for AMD Pensando SoC Controller
2023-08-11 18:05 [PATCH v15 0/6] Support AMD Pensando Elba SoC Brad Larson
` (4 preceding siblings ...)
2023-08-11 18:05 ` [PATCH v15 5/6] arm64: dts: Add AMD Pensando Elba SoC support Brad Larson
@ 2023-08-11 18:05 ` Brad Larson
5 siblings, 0 replies; 9+ messages in thread
From: Brad Larson @ 2023-08-11 18:05 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, linux-mmc, linux-spi, adrian.hunter, alcooperx,
andy.shevchenko, arnd, blarson, brendan.higgins, briannorris,
catalin.marinas, conor+dt, davidgow, gsomlo, gerg, hal.feng,
hasegawa-hitomi, j.neuschaefer, joel, kernel, krzk,
krzysztof.kozlowski+dt, lee, lee.jones, broonie, p.zabel, rdunlap,
robh+dt, samuel, fancer.lancer, skhan, suravee.suthikulpanit,
thomas.lendacky, tonyhuang.sunplus, ulf.hansson, vaishnav.a,
walker.chen, will, zhuyinbo, devicetree
The Pensando SoC controller is a SPI connected companion device
that is present in all Pensando SoC board designs. The essential
board management registers are accessed on chip select 0 with
board mgmt IO support accessed using additional chip selects.
Signed-off-by: Brad Larson <blarson@amd.com>
---
v15 changes:
- Drop custom ioctl and use existing miscdevice interface.
- Makefile change to only compile for ARCH_PENSANDO
v14 changes:
- Save 8 bytes of code size by swapping spi_device and reset_controller_dev
in penctrl_device
- Code simplification and clarity from review inputs
- Set penctrl_spi_driver.driver.name to match compatible pensando-elba-ctrl
- Remove unused include in amd-pensando-ctrl.h
- Rebase to linux-next 6.4.0-rc1 class_create() API change
v13 changes:
- Update include list in pensando-ctrl.c
- Change variable spi_dev to spi throughout
- Removed unneeded variable initialization, simplification of
error checks, remove extra castings, and use dev_err_probe()
- Sort the includes in amd-pensando-ctrl.h
- Updates to cleanup if there is an error in penctrl_spi_probe()
v12 changes:
- Fix gcc-12.1.0 warning
v11 changes:
- Fix the compatible to be specific 'amd,pensando-elba-ctrl'
v10 changes:
- Different driver implementation specific to this Pensando controller device.
- Moved to soc/amd directory under new name based on guidance. This driver is
of no use to any design other than all Pensando SoC based cards.
- Removed use of builtin_driver, can be built as a module.
v9 changes:
- Previously patch 14/17
- After the change to the device tree node and squashing
reset-cells into the parent simplified this to not use
any MFD API and move it to drivers/spi/pensando-sr.c.
- Change the naming to remove elba since this driver is common
for all Pensando SoC designs .
- Default yes SPI_PENSANDO_SR for ARCH_PENSANDO
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/amd/Kconfig | 16 ++
drivers/soc/amd/Makefile | 2 +
drivers/soc/amd/pensando-ctrl.c | 311 +++++++++++++++++++++++++
include/uapi/linux/amd-pensando-ctrl.h | 27 +++
6 files changed, 358 insertions(+)
create mode 100644 drivers/soc/amd/Kconfig
create mode 100644 drivers/soc/amd/Makefile
create mode 100644 drivers/soc/amd/pensando-ctrl.c
create mode 100644 include/uapi/linux/amd-pensando-ctrl.h
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 4e176280113a..4e9453fdcb2f 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -3,6 +3,7 @@ menu "SOC (System On Chip) specific Drivers"
source "drivers/soc/actions/Kconfig"
source "drivers/soc/amlogic/Kconfig"
+source "drivers/soc/amd/Kconfig"
source "drivers/soc/apple/Kconfig"
source "drivers/soc/aspeed/Kconfig"
source "drivers/soc/atmel/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 3b0f9fb3b5c8..1b2fc9caff8b 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -4,6 +4,7 @@
#
obj-$(CONFIG_ARCH_ACTIONS) += actions/
+obj-$(CONFIG_ARCH_PENSANDO) += amd/
obj-y += apple/
obj-y += aspeed/
obj-$(CONFIG_ARCH_AT91) += atmel/
diff --git a/drivers/soc/amd/Kconfig b/drivers/soc/amd/Kconfig
new file mode 100644
index 000000000000..011d5339d14e
--- /dev/null
+++ b/drivers/soc/amd/Kconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menu "AMD Pensando SoC drivers"
+
+config AMD_PENSANDO_CTRL
+ tristate "AMD Pensando SoC Controller"
+ depends on SPI_MASTER=y
+ depends on (ARCH_PENSANDO && OF) || COMPILE_TEST
+ default ARCH_PENSANDO
+ select REGMAP_SPI
+ select MFD_SYSCON
+ help
+ Enables AMD Pensando SoC controller device support. This is a SPI
+ attached companion device in all Pensando SoC board designs which
+ provides essential board control/status registers and management IO
+ support.
+endmenu
diff --git a/drivers/soc/amd/Makefile b/drivers/soc/amd/Makefile
new file mode 100644
index 000000000000..a2de0424f68d
--- /dev/null
+++ b/drivers/soc/amd/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_AMD_PENSANDO_CTRL) += pensando-ctrl.o
diff --git a/drivers/soc/amd/pensando-ctrl.c b/drivers/soc/amd/pensando-ctrl.c
new file mode 100644
index 000000000000..0b5a3a54d624
--- /dev/null
+++ b/drivers/soc/amd/pensando-ctrl.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * AMD Pensando SoC Controller
+ *
+ * Userspace interface and reset driver support for SPI connected Pensando SoC
+ * controller device. This device is present in all Pensando SoC designs and
+ * contains board control/status registers and management IO support.
+ *
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ */
+
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/miscdevice.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/reset-controller.h>
+#include <linux/spi/spi.h>
+#include <linux/uaccess.h>
+
+#include <linux/amd-pensando-ctrl.h>
+
+struct penctrl_device {
+ struct reset_controller_dev rcdev;
+ struct spi_device *spi;
+};
+
+static struct penctrl_device *penctrl;
+static DEFINE_MUTEX(spi_lock);
+
+static long
+penctrl_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ struct penctrl_device *penctrl;
+ u8 tx_buf[PENCTRL_MAX_MSG_LEN];
+ u8 rx_buf[PENCTRL_MAX_MSG_LEN];
+ struct spi_transfer t[2] = {};
+ struct penctrl_spi_xfer *msg;
+ struct spi_device *spi;
+ unsigned int num_msgs;
+ struct spi_message m;
+ u32 size;
+ int ret;
+
+ /* Get a reference to the SPI device */
+ penctrl = filp->private_data;
+ if (!penctrl)
+ return -ESHUTDOWN;
+
+ spi = spi_dev_get(penctrl->spi);
+ if (!spi)
+ return -ESHUTDOWN;
+
+ /* Verify and prepare SPI message */
+ size = _IOC_SIZE(cmd);
+ num_msgs = size / sizeof(struct penctrl_spi_xfer);
+ if (num_msgs > 2 || size == 0 || size % sizeof(struct penctrl_spi_xfer)) {
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+ msg = memdup_user((struct penctrl_spi_xfer *)arg, size);
+ if (IS_ERR(msg)) {
+ ret = PTR_ERR(msg);
+ goto out_unlock;
+ }
+ if (msg->len > PENCTRL_MAX_MSG_LEN) {
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+
+ t[0].tx_buf = tx_buf;
+ t[0].len = msg->len;
+ if (copy_from_user(tx_buf, (void __user *)msg->tx_buf, msg->len)) {
+ ret = -EFAULT;
+ goto out_unlock;
+ }
+ if (num_msgs > 1) {
+ msg++;
+ if (msg->len > PENCTRL_MAX_MSG_LEN) {
+ ret = -EINVAL;
+ goto out_unlock;
+ }
+ t[1].rx_buf = rx_buf;
+ t[1].len = msg->len;
+ }
+ spi_message_init_with_transfers(&m, t, num_msgs);
+
+ /* Perform the transfer */
+ mutex_lock(&spi_lock);
+ ret = spi_sync(spi, &m);
+ mutex_unlock(&spi_lock);
+
+ if (ret || (num_msgs == 1))
+ goto out_unlock;
+
+ if (copy_to_user((void __user *)msg->rx_buf, rx_buf, msg->len))
+ ret = -EFAULT;
+
+out_unlock:
+ spi_dev_put(spi);
+ return ret;
+}
+
+static int penctrl_open(struct inode *inode, struct file *filp)
+{
+ struct spi_device *spi;
+ u8 current_cs;
+
+ filp->private_data = penctrl;
+ current_cs = iminor(inode);
+ spi = penctrl->spi;
+ spi->chip_select = current_cs;
+ spi_set_csgpiod(spi, 0, spi->controller->cs_gpiods[current_cs]);
+ spi_setup(spi);
+ return stream_open(inode, filp);
+}
+
+static int penctrl_release(struct inode *inode, struct file *filp)
+{
+ filp->private_data = NULL;
+ return 0;
+}
+
+static const struct file_operations penctrl_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = penctrl_ioctl,
+ .open = penctrl_open,
+ .release = penctrl_release,
+ .llseek = no_llseek,
+};
+
+static int penctrl_regs_read(struct penctrl_device *penctrl, u32 reg, u32 *val)
+{
+ struct spi_device *spi = penctrl->spi;
+ struct spi_transfer t[2] = {};
+ struct spi_message m;
+ u8 txbuf[3];
+ u8 rxbuf[1];
+ int ret;
+
+ txbuf[0] = PENCTRL_SPI_CMD_REGRD;
+ txbuf[1] = reg;
+ txbuf[2] = 0;
+ t[0].tx_buf = txbuf;
+ t[0].len = sizeof(txbuf);
+
+ rxbuf[0] = 0;
+ t[1].rx_buf = rxbuf;
+ t[1].len = sizeof(rxbuf);
+
+ spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
+ ret = spi_sync(spi, &m);
+ if (ret)
+ return ret;
+
+ *val = rxbuf[0];
+ return 0;
+}
+
+static int penctrl_regs_write(struct penctrl_device *penctrl, u32 reg, u32 val)
+{
+ struct spi_device *spi = penctrl->spi;
+ struct spi_transfer t = {};
+ struct spi_message m;
+ u8 txbuf[4];
+
+ txbuf[0] = PENCTRL_SPI_CMD_REGWR;
+ txbuf[1] = reg;
+ txbuf[2] = val;
+ txbuf[3] = 0;
+
+ t.tx_buf = txbuf;
+ t.len = sizeof(txbuf);
+ spi_message_init_with_transfers(&m, &t, 1);
+ return spi_sync(spi, &m);
+}
+
+static int penctrl_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct penctrl_device *penctrl =
+ container_of(rcdev, struct penctrl_device, rcdev);
+ struct spi_device *spi = penctrl->spi;
+ unsigned int val;
+ int ret;
+
+ mutex_lock(&spi_lock);
+ spi->chip_select = 0;
+ spi_set_csgpiod(spi, 0, spi->controller->cs_gpiods[0]);
+ spi_setup(spi);
+ ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val);
+ if (ret) {
+ dev_err(&spi->dev, "error reading ctrl0 reg\n");
+ goto out_unlock;
+ }
+
+ val |= BIT(6);
+ ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val);
+ if (ret)
+ dev_err(&spi->dev, "error writing ctrl0 reg\n");
+
+out_unlock:
+ mutex_unlock(&spi_lock);
+ return ret;
+}
+
+static int penctrl_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct penctrl_device *penctrl =
+ container_of(rcdev, struct penctrl_device, rcdev);
+ struct spi_device *spi = penctrl->spi;
+ unsigned int val;
+ int ret;
+
+ mutex_lock(&spi_lock);
+ spi->chip_select = 0;
+ spi_set_csgpiod(spi, 0, spi->controller->cs_gpiods[0]);
+ spi_setup(spi);
+ ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val);
+ if (ret) {
+ dev_err(&spi->dev, "error reading ctrl0 reg\n");
+ goto out_unlock;
+ }
+
+ val &= ~BIT(6);
+ ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val);
+ if (ret)
+ dev_err(&spi->dev, "error writing ctrl0 reg\n");
+
+out_unlock:
+ mutex_unlock(&spi_lock);
+ return ret;
+}
+
+static const struct reset_control_ops penctrl_reset_ops = {
+ .assert = penctrl_reset_assert,
+ .deassert = penctrl_reset_deassert,
+};
+
+static struct miscdevice penctrl_devices[] = {
+ { .minor = 0, .name = "penctrl.0", .fops = &penctrl_fops },
+ { .minor = 1, .name = "penctrl.1", .fops = &penctrl_fops },
+ { .minor = 2, .name = "penctrl.2", .fops = &penctrl_fops },
+ { .minor = 3, .name = "penctrl.3", .fops = &penctrl_fops },
+};
+
+static int penctrl_spi_probe(struct spi_device *spi)
+{
+ int i, ret;
+
+ /* Allocate driver data */
+ penctrl = kzalloc(sizeof(*penctrl), GFP_KERNEL);
+ if (!penctrl)
+ return -ENOMEM;
+
+ penctrl->spi = spi;
+ mutex_init(&spi_lock);
+
+ for (i = 0; i < ARRAY_SIZE(penctrl_devices); i++) {
+ ret = misc_register(&penctrl_devices[i]);
+ if (ret) {
+ dev_err(&spi->dev, "Failed to register device %s\n",
+ penctrl_devices[i].name);
+ goto cleanup;
+ }
+ }
+
+ /* Register reset controller */
+ penctrl->rcdev.dev = &spi->dev;
+ penctrl->rcdev.ops = &penctrl_reset_ops;
+ penctrl->rcdev.owner = THIS_MODULE;
+ penctrl->rcdev.of_node = spi->dev.of_node;
+ penctrl->rcdev.nr_resets = 1;
+ device_set_node(penctrl->rcdev.dev, dev_fwnode(&spi->dev));
+
+ ret = reset_controller_register(&penctrl->rcdev);
+ if (ret)
+ return dev_err_probe(&spi->dev, ret,
+ "failed to register reset controller\n");
+ return 0;
+
+cleanup:
+ for (i = 0; i < ARRAY_SIZE(penctrl_devices); i++) {
+ if (penctrl_devices[i].this_device)
+ misc_deregister(&penctrl_devices[i]);
+ }
+ return ret;
+}
+
+static const struct of_device_id penctrl_dt_match[] = {
+ { .compatible = "amd,pensando-elba-ctrl" },
+ { /* sentinel */ }
+};
+
+static struct spi_driver penctrl_spi_driver = {
+ .probe = penctrl_spi_probe,
+ .driver = {
+ .name = "pensando-elba-ctrl",
+ .of_match_table = penctrl_dt_match,
+ },
+};
+module_spi_driver(penctrl_spi_driver);
+
+MODULE_AUTHOR("Brad Larson <blarson@amd.com>");
+MODULE_DESCRIPTION("AMD Pensando SoC Controller via SPI");
+MODULE_LICENSE("GPL");
diff --git a/include/uapi/linux/amd-pensando-ctrl.h b/include/uapi/linux/amd-pensando-ctrl.h
new file mode 100644
index 000000000000..46958271c5dd
--- /dev/null
+++ b/include/uapi/linux/amd-pensando-ctrl.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Userspace interface for /dev/penctrl
+ *
+ * This file can be used by applications that need to communicate
+ * with the AMD Pensando SoC controller device via the ioctl interface.
+ */
+#ifndef _UAPI_LINUX_AMD_PENSANDO_CTRL_H
+#define _UAPI_LINUX_AMD_PENSANDO_CTRL_H
+
+#include <linux/types.h>
+
+#define PENCTRL_SPI_CMD_REGRD 0x0b
+#define PENCTRL_SPI_CMD_REGWR 0x02
+#define PENCTRL_MAX_MSG_LEN 16
+#define PENCTRL_MAX_REG 0xff
+#define PENCTRL_REG_CTRL0 0x10
+
+struct penctrl_spi_xfer {
+ __u64 tx_buf;
+ __u64 rx_buf;
+ __u32 len;
+ __u32 speed_hz;
+ __u64 compat;
+};
+
+#endif /* _UAPI_LINUX_AMD_PENSANDO_CTRL_H */
--
2.17.1
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