From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5D29C2FC1A for ; Thu, 17 Aug 2023 08:48:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349075AbjHQIrd (ORCPT ); Thu, 17 Aug 2023 04:47:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349121AbjHQIrS (ORCPT ); Thu, 17 Aug 2023 04:47:18 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 496EB173F for ; Thu, 17 Aug 2023 01:47:17 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-4ff88239785so3901622e87.0 for ; Thu, 17 Aug 2023 01:47:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692262035; x=1692866835; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7t4knoTgcpMAoiThrLCBlOztZFf+DUVrX+KwaoYfcMU=; b=KIyLDk/dvBbBr+oi6aL3Qh4GCX9z/AZi32P1SZ2JWWozSRLdTLU3rpxWYMthUOU8cF 5dnyfyMQOFx2RD7hpOKHeWg6b+OLqC5JjoAfHQOmBDsRFnC4PlTOgOWWYPXs5ToER3KE nYMxDCRo0lfkG9EbBUAVkrk94rh9lpf1KYX1/nQ4jRcFuxv4Plep1z5Yl3J/n/T9KO0U t+cQ/JoaskgiuFVnCN/mpT3anPVkfgHCC+5Kh3jezxrWMAy9vYTgLf8IsdFabD2gOrpN S7355qWe1LWuvngCyZt5WIy2Lk/OQLaf3OWlXUxBThCUUqy02xH9qYEDiPwsjpbEfSUq Jx4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692262035; x=1692866835; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7t4knoTgcpMAoiThrLCBlOztZFf+DUVrX+KwaoYfcMU=; b=G3sLGNcf+QYqmSM+cKKRG9B+ObyCENARQ9I6o5DUfNXPagVGTRZX1vdPSgPNr5SeQH caP6H+qvgyltRcGy0qrV7wQN77IV9uV3/rCyEOmzBdCO8AcYCGP2N+Z3xOS5+bnh7Q7V mD0ZUaZ1WuAgTdJXBRfZ7LWuxHKoxiws6fYZnJSjpsGEtgwAEJC1D1ve7Q1TzlAuPLoK kZX4GXSR2zDNZGpll4SA7KRCpdCcWKRiEbZb/UWXrHHEeNKhuy4cUD3cWHQbsoy4m8Gk /AWUszc6MV0cs6MoLaPenTXGWn0+pMXyVkJXj7cSFRjK6z5H1O8N82KIoS8A25r7JixX ctIg== X-Gm-Message-State: AOJu0YwutrGA4If/1oI2JDEexZ/oCsh3gmJDg5tPwWITkw5ZWFQ6qrE3 1KOuw/i4U6hZVO7l3gnZDhE05w== X-Google-Smtp-Source: AGHT+IG6u5+6Wn1fn5uJ/gKC/iV1OP++u+3oO9FHrOsaeIxWT5kYxSQBPhf86/MysuEQZPUDuVryPQ== X-Received: by 2002:a05:6512:3c87:b0:4fa:f96c:745f with SMTP id h7-20020a0565123c8700b004faf96c745fmr4347010lfv.38.1692262035479; Thu, 17 Aug 2023 01:47:15 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id m9-20020a05600c280900b003fe539b83f2sm2117285wmb.42.2023.08.17.01.47.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Aug 2023 01:47:15 -0700 (PDT) From: Neil Armstrong Date: Thu, 17 Aug 2023 10:47:06 +0200 Subject: [PATCH v3 1/2] arm64: dts: qcom: sm8550: add UART14 nodes MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20230817-topic-sm8550-upstream-bt-v3-1-33f386e7b461@linaro.org> References: <20230817-topic-sm8550-upstream-bt-v3-0-33f386e7b461@linaro.org> In-Reply-To: <20230817-topic-sm8550-upstream-bt-v3-0-33f386e7b461@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1815; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=tbcjsIAk9XwFHFpbOFCyqYsyyRsIObVh70p79lbsc44=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBk3d6QRCrxwV0Islpz/NTs+7AAEoluPNwqi8xMOTNu djmLQueJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZN3ekAAKCRB33NvayMhJ0Y5IEA DM58GC0KqJ6bccbUKVYJ29ocQyPZx5tdw1xVu5EUE3SOb5lmYlC/uNQbVvDo9+c9evu3UwfFqiUPZN WxsXOYYzTDwni3CUthKtZO0X0AEDU7PEywshrLqvu5rlOkxYDtL6aFg+tBCCe5WcsIPXRBG09hgLyL hIqaLNEuc7mBdrfy0m6BxsOiq2q+k5NmulpuLkRP7F10cWF5OZJxpBvyDyPSv4W51FWluBRHYbiaWq jjQq76EhgU68nythnMzULqGUXnkwEmdrqbKZ2l9v4qryp3B+ibgbmV3yrC0qKZFojsLD0+2OnrQat8 GMZsu1qfiacURY2aL71sdLkZYHmFIJ5cu3whj1ztETh4bbUchxt4PynHgWH0t+2a854cHw7oPkrCr8 uY5ROCoa9VD4A9gTDk0X1JN0r+U3xoziJhIWT5igbRwdB5J9HdWqCj/OqhWZSb0h31emBr42wB40Ci aqIMYakietssBD7dsb6jluiWWsY67FG3/cU6my8FxebAUonGFXCZ+84NUhaqrgVehbcOCSPDHzugxP oS1PHCURurCZ/iHrjIGMK/GPgQXlrVRUUnC+DIvxntMZ5I7F7+2UDZeKnso0LEOXnESNvZiAVfGZ4v ZiBGFQiJoQUhs0QxzGqTsx6oklUhJM2rr+rqjbYLrJfaQydytK4E9yVMSG+A== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the Geni High Speed UART QUP instance 2 element 6 node and associated default pinctrl. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index d115960bdeec..4be10a9bf933 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1054,6 +1054,20 @@ spi13: spi@894000 { status = "disabled"; }; + uart14: uart@898000 { + compatible = "qcom,geni-uart"; + reg = <0 0x898000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + i2c15: i2c@89c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0089c000 0 0x4000>; @@ -3498,6 +3512,22 @@ qup_uart7_default: qup-uart7-default-state { bias-disable; }; + qup_uart14_default: qup-uart14-default-state { + /* TX, RX */ + pins = "gpio78", "gpio79"; + function = "qup2_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart14_cts_rts: qup-uart14-cts-rts-state { + /* CTS, RTS */ + pins = "gpio76", "gpio77"; + function = "qup2_se6"; + drive-strength = <2>; + bias-pull-down; + }; + sdc2_sleep: sdc2-sleep-state { clk-pins { pins = "sdc2_clk"; -- 2.34.1