From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4EA0C3DA66 for ; Thu, 17 Aug 2023 17:10:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353672AbjHQRJ5 (ORCPT ); Thu, 17 Aug 2023 13:09:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353906AbjHQRJz (ORCPT ); Thu, 17 Aug 2023 13:09:55 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D38C121; Thu, 17 Aug 2023 10:09:50 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 52C90675BF; Thu, 17 Aug 2023 17:09:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 10155C43397; Thu, 17 Aug 2023 17:09:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692292189; bh=H6r17igTApBMtumIbML4/Pv00+k0irJssUyt+I4FyfE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LYpTTr3Bt7kUAgHnD+wrvXcht/aMFZ37ye8zlLZaCbzamr0O075RyZSz23otSW+/I YFbZfGI1uQnLMW1zyJXqdY2ItxEqCvwT36UV+ZpL6i3HM075xn/Bb0ODnzp7m6m2qb 8BF9OrUBbp8v3a7qFxGj7P0Aeqf8r9+l7R2uda486x8Xj9bU7QjTFnkHAqOWXTaTev zjlp4hZGZU8Dh6dEM9P+GxiEtVMPcT67RfeTmSpAxS487TbFmfTwomQiK5dL5Hp0sS wUt/gT5Ilg0hZf+ZJDnYE2IkyF+fXx+E77ZRbtsCNwx21b89C+eFzMYdk5t2UgK9NC Nu3sUuN2du5OQ== From: Jisheng Zhang To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v5 5/9] net: stmmac: xgmac: support per-channel irq Date: Fri, 18 Aug 2023 00:57:45 +0800 Message-Id: <20230817165749.672-6-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230817165749.672-1-jszhang@kernel.org> References: <20230817165749.672-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The IP supports per channel interrupt, add support for this usage case. Signed-off-by: Jisheng Zhang --- .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 ++ .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 33 +++++++++++-------- 2 files changed, 22 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index 7f68bef456b7..18a042834d75 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -340,6 +340,8 @@ /* DMA Registers */ #define XGMAC_DMA_MODE 0x00003000 +#define XGMAC_INTM GENMASK(13, 12) +#define XGMAC_INTM_MODE1 0x1 #define XGMAC_SWR BIT(0) #define XGMAC_DMA_SYSBUS_MODE 0x00003004 #define XGMAC_WR_OSR_LMT GENMASK(29, 24) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 1ef8fc132c2d..ce228c362403 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -31,6 +31,13 @@ static void dwxgmac2_dma_init(void __iomem *ioaddr, value |= XGMAC_EAME; writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); + + if (dma_cfg->perch_irq_en) { + value = readl(ioaddr + XGMAC_DMA_MODE); + value &= ~XGMAC_INTM; + value |= FIELD_PREP(XGMAC_INTM, XGMAC_INTM_MODE1); + writel(value, ioaddr + XGMAC_DMA_MODE); + } } static void dwxgmac2_dma_init_chan(struct stmmac_priv *priv, @@ -365,20 +372,20 @@ static int dwxgmac2_dma_interrupt(struct stmmac_priv *priv, } /* TX/RX NORMAL interrupts */ - if (likely(intr_status & XGMAC_NIS)) { - if (likely(intr_status & XGMAC_RI)) { - u64_stats_update_begin(&rx_q->rxq_stats.syncp); - rx_q->rxq_stats.rx_normal_irq_n++; - u64_stats_update_end(&rx_q->rxq_stats.syncp); - ret |= handle_rx; - } - if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) { - u64_stats_update_begin(&tx_q->txq_stats.syncp); - tx_q->txq_stats.tx_normal_irq_n++; - u64_stats_update_end(&tx_q->txq_stats.syncp); - ret |= handle_tx; - } + if (likely(intr_status & XGMAC_RI)) { + u64_stats_update_begin(&rx_q->rxq_stats.syncp); + rx_q->rxq_stats.rx_normal_irq_n++; + u64_stats_update_end(&rx_q->rxq_stats.syncp); + ret |= handle_rx; + } + if (likely(intr_status & XGMAC_TI)) { + u64_stats_update_begin(&tx_q->txq_stats.syncp); + tx_q->txq_stats.tx_normal_irq_n++; + u64_stats_update_end(&tx_q->txq_stats.syncp); + ret |= handle_tx; } + if (unlikely(intr_status & XGMAC_TBU)) + ret |= handle_tx; /* Clear interrupts */ writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan)); -- 2.40.1