Re: [PATCH v2 1/3] dt-bindings: clock: versaclock3: Document clock-output-names

[Conor Dooley <conor@kernel.org>]

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On Thu, Aug 17, 2023 at 10:08:08AM +0100, Biju Das wrote:
> Document clock-output-names property and fix the "assigned-clock-rates"
> for each clock output in the example based on Table 3. ("Output Source")
> in the 5P35023 datasheet(ie: {REF,SE1,SE2,SE3,DIFF1,DIFF2}).
> 
> While at it, replace clocks phandle in the example from x1_x2->x1 as
> X2 is a different 32768 kHz crystal.
> 
> Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Closes: https://lore.kernel.org/all/CAMuHMdUHD+bEco=WYTYWsTAyRt3dTQQt4Xpaejss0Y2ZpLCMNg@mail.gmail.com/
> Fixes: a03d23f860eb ("dt-bindings: clock: Add Renesas versa3 clock generator bindings")
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> ---
> v1->v2:
>  * Updated commit description to make it clear it fixes
>    "assigned-clock-rates" in the example based on 5P35023 datasheet.
> ---
>  .../devicetree/bindings/clock/renesas,5p35023.yaml | 14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
> index 839648e753d4..db8d01b291dd 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
> @@ -49,6 +49,9 @@ properties:
>      $ref: /schemas/types.yaml#/definitions/uint8-array
>      maxItems: 37
>  
> +  clock-output-names:
> +    maxItems: 6
> +
>  required:
>    - compatible
>    - reg
> @@ -68,7 +71,7 @@ examples:
>              reg = <0x68>;
>              #clock-cells = <1>;
>  
> -            clocks = <&x1_x2>;
> +            clocks = <&x1>;
>  
>              renesas,settings = [
>                  80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
> @@ -76,11 +79,14 @@ examples:
>                  80 b0 45 c4 95
>              ];
>  
> +            clock-output-names = "ref", "se1", "se2", "se3",
> +                                 "diff1", "diff2";
> +
>              assigned-clocks = <&versa3 0>, <&versa3 1>,
>                                <&versa3 2>, <&versa3 3>,
>                                <&versa3 4>, <&versa3 5>;
> -            assigned-clock-rates = <12288000>, <25000000>,
> -                                   <12000000>, <11289600>,
> -                                   <11289600>, <24000000>;
> +            assigned-clock-rates = <24000000>, <11289600>,
> +                                   <11289600>, <12000000>,
> +                                   <25000000>, <12288000>;
>          };
>      };
> -- 
> 2.25.1
> 

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