From: Liu Ying <victor.liu@nxp.com>
To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: andrzej.hajda@intel.com, neil.armstrong@linaro.org,
rfoss@kernel.org, Laurent.pinchart@ideasonboard.com,
jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com,
daniel@ffwll.ch, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
alexander.stein@ew.tq-group.com, sam@ravnborg.org,
jagan@amarulasolutions.com, yannick.fertre@foss.st.com,
raphael.gallais-pou@foss.st.com, philippe.cornu@foss.st.com,
hjc@rock-chips.com, heiko@sntech.de, zyw@rock-chips.com
Subject: [PATCH v3 RESEND 5/9] drm/bridge: synopsys: dw-mipi-dsi: Use pixel clock rate to calculate lbcc
Date: Mon, 21 Aug 2023 11:40:04 +0800 [thread overview]
Message-ID: <20230821034008.3876938-6-victor.liu@nxp.com> (raw)
In-Reply-To: <20230821034008.3876938-1-victor.liu@nxp.com>
To get better accuration, use pixel clock rate to calculate lbcc instead of
lane_mbps since the pixel clock rate is in KHz while lane_mbps is in MHz.
Without this, distorted image can be seen on a HDMI monitor connected with
i.MX93 11x11 EVK through ADV7535 DSI to HDMI bridge in 1920x1080p@60 video
mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
v2->v3:
* Add Neil's R-b tag from v1.
v1->v2:
* No change.
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index b2da803c9de7..18e7d64b0216 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -12,6 +12,7 @@
#include <linux/component.h>
#include <linux/debugfs.h>
#include <linux/iopoll.h>
+#include <linux/math64.h>
#include <linux/media-bus-format.h>
#include <linux/module.h>
#include <linux/platform_device.h>
@@ -764,8 +765,15 @@ static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
u32 hcomponent)
{
u32 frac, lbcc;
+ int bpp;
- lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
+ bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
+ if (bpp < 0) {
+ dev_err(dsi->dev, "failed to get bpp\n");
+ return 0;
+ }
+
+ lbcc = div_u64((u64)hcomponent * mode->clock * bpp, dsi->lanes * 8);
frac = lbcc % mode->clock;
lbcc = lbcc / mode->clock;
--
2.37.1
next prev parent reply other threads:[~2023-08-21 3:38 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-21 3:39 [PATCH v3 RESEND 0/9] drm/bridge: imx: Add i.MX93 MIPI DSI support Liu Ying
2023-08-21 3:40 ` [PATCH v3 RESEND 1/9] drm/bridge: synopsys: dw-mipi-dsi: Add dw_mipi_dsi_get_bridge() helper Liu Ying
2023-10-16 9:34 ` Robert Foss
2023-08-21 3:40 ` [PATCH v3 RESEND 2/9] drm/bridge: synopsys: dw-mipi-dsi: Add input bus format negotiation support Liu Ying
2023-10-16 9:34 ` Robert Foss
2023-08-21 3:40 ` [PATCH v3 RESEND 3/9] drm/bridge: synopsys: dw-mipi-dsi: Force input bus flags Liu Ying
2023-10-16 9:33 ` Robert Foss
2023-08-21 3:40 ` [PATCH v3 RESEND 4/9] drm/bridge: synopsys: dw-mipi-dsi: Add mode fixup support Liu Ying
2023-10-16 9:31 ` Robert Foss
2023-08-21 3:40 ` Liu Ying [this message]
2023-08-21 3:40 ` [PATCH v3 RESEND 6/9] drm/bridge: synopsys: dw-mipi-dsi: Set minimum lane byte clock cycles for HSA and HBP Liu Ying
2023-08-21 3:40 ` [PATCH v3 RESEND 7/9] drm/bridge: synopsys: dw-mipi-dsi: Disable HSTX and LPRX timeout check Liu Ying
2023-08-21 3:40 ` [PATCH v3 RESEND 8/9] dt-bindings: display: bridge: Document Freescale i.MX93 MIPI DSI Liu Ying
2023-08-21 3:40 ` [PATCH v3 RESEND 9/9] drm/bridge: imx: Add i.MX93 MIPI DSI support Liu Ying
2023-10-16 9:36 ` Robert Foss
2023-10-16 9:42 ` [PATCH v3 RESEND 0/9] " Robert Foss
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