* [PATCH V1 0/2] Add UFS host controller and Phy nodes for sc7280 @ 2023-08-21 9:49 Nitin Rawat 2023-08-21 9:49 ` [PATCH V1 1/2] scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string Nitin Rawat 2023-08-21 9:49 ` [PATCH V1 2/2] arm64: dts: qcom: sc7280: Add UFS host controller and phy nodes Nitin Rawat 0 siblings, 2 replies; 9+ messages in thread From: Nitin Rawat @ 2023-08-21 9:49 UTC (permalink / raw) To: mani, agross, andersson, konrad.dybcio, alim.akhtar, bvanassche, robh+dt, avri.altman, cros-qcom-dts-watchers, krzysztof.kozlowski+dt, conor+dt Cc: linux-arm-msm, linux-scsi, linux-kernel, devicetree, Nitin Rawat This patch adds UFS host controller and Phy nodes for Qualcomm SC7280 SOC. This patch is dependent on below patch- "dt-bindings: phy: Add QMP UFS PHY comptible for SC7280" (https://lore.kernel.org/lkml/481ac6b3-1dda-1e9e-7339-e39a17d2eed9@linaro.org/) Nitin Rawat (2): scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string arm64: dts: qcom: sc7280: Add UFS host controller and phy nodes .../devicetree/bindings/ufs/qcom,ufs.yaml | 2 + arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 ++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 64 +++++++++++++++++++ 3 files changed, 85 insertions(+) -- 2.17.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH V1 1/2] scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string 2023-08-21 9:49 [PATCH V1 0/2] Add UFS host controller and Phy nodes for sc7280 Nitin Rawat @ 2023-08-21 9:49 ` Nitin Rawat 2023-08-21 12:14 ` Krzysztof Kozlowski ` (2 more replies) 2023-08-21 9:49 ` [PATCH V1 2/2] arm64: dts: qcom: sc7280: Add UFS host controller and phy nodes Nitin Rawat 1 sibling, 3 replies; 9+ messages in thread From: Nitin Rawat @ 2023-08-21 9:49 UTC (permalink / raw) To: mani, agross, andersson, konrad.dybcio, alim.akhtar, bvanassche, robh+dt, avri.altman, cros-qcom-dts-watchers, krzysztof.kozlowski+dt, conor+dt Cc: linux-arm-msm, linux-scsi, linux-kernel, devicetree, Nitin Rawat Document the compatible string for the UFS found on SC7280. Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> --- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml index bdfa86a0cc98..861bbf6a57f6 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -27,6 +27,7 @@ properties: - qcom,msm8996-ufshc - qcom,msm8998-ufshc - qcom,sa8775p-ufshc + - qcom,sc7280-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6350-ufshc @@ -111,6 +112,7 @@ allOf: enum: - qcom,msm8998-ufshc - qcom,sa8775p-ufshc + - qcom,sc7280-ufshc - qcom,sc8280xp-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc -- 2.17.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH V1 1/2] scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string 2023-08-21 9:49 ` [PATCH V1 1/2] scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string Nitin Rawat @ 2023-08-21 12:14 ` Krzysztof Kozlowski 2023-08-21 14:15 ` Bao D. Nguyen 2023-08-22 7:09 ` Manivannan Sadhasivam 2 siblings, 0 replies; 9+ messages in thread From: Krzysztof Kozlowski @ 2023-08-21 12:14 UTC (permalink / raw) To: Nitin Rawat, mani, agross, andersson, konrad.dybcio, alim.akhtar, bvanassche, robh+dt, avri.altman, cros-qcom-dts-watchers, krzysztof.kozlowski+dt, conor+dt Cc: linux-arm-msm, linux-scsi, linux-kernel, devicetree On 21/08/2023 11:49, Nitin Rawat wrote: > Document the compatible string for the UFS found on SC7280. > > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > --- > Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH V1 1/2] scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string 2023-08-21 9:49 ` [PATCH V1 1/2] scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string Nitin Rawat 2023-08-21 12:14 ` Krzysztof Kozlowski @ 2023-08-21 14:15 ` Bao D. Nguyen 2023-08-22 7:09 ` Manivannan Sadhasivam 2 siblings, 0 replies; 9+ messages in thread From: Bao D. Nguyen @ 2023-08-21 14:15 UTC (permalink / raw) To: Nitin Rawat, mani, agross, andersson, konrad.dybcio, alim.akhtar, bvanassche, robh+dt, avri.altman, cros-qcom-dts-watchers, krzysztof.kozlowski+dt, conor+dt Cc: linux-arm-msm, linux-scsi, linux-kernel, devicetree On 8/21/2023 2:49 AM, Nitin Rawat wrote: > Document the compatible string for the UFS found on SC7280. > > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > --- > Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > index bdfa86a0cc98..861bbf6a57f6 100644 > --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > @@ -27,6 +27,7 @@ properties: > - qcom,msm8996-ufshc > - qcom,msm8998-ufshc > - qcom,sa8775p-ufshc > + - qcom,sc7280-ufshc > - qcom,sc8280xp-ufshc > - qcom,sdm845-ufshc > - qcom,sm6350-ufshc > @@ -111,6 +112,7 @@ allOf: > enum: > - qcom,msm8998-ufshc > - qcom,sa8775p-ufshc > + - qcom,sc7280-ufshc > - qcom,sc8280xp-ufshc > - qcom,sm8250-ufshc > - qcom,sm8350-ufshc > -- > 2.17.1 > Reviewed-by: Bao D. Nguyen <quic_nguyenb@quicinc.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH V1 1/2] scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string 2023-08-21 9:49 ` [PATCH V1 1/2] scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string Nitin Rawat 2023-08-21 12:14 ` Krzysztof Kozlowski 2023-08-21 14:15 ` Bao D. Nguyen @ 2023-08-22 7:09 ` Manivannan Sadhasivam 2 siblings, 0 replies; 9+ messages in thread From: Manivannan Sadhasivam @ 2023-08-22 7:09 UTC (permalink / raw) To: Nitin Rawat Cc: agross, andersson, konrad.dybcio, alim.akhtar, bvanassche, robh+dt, avri.altman, cros-qcom-dts-watchers, krzysztof.kozlowski+dt, conor+dt, linux-arm-msm, linux-scsi, linux-kernel, devicetree On Mon, Aug 21, 2023 at 03:19:36PM +0530, Nitin Rawat wrote: > Document the compatible string for the UFS found on SC7280. > > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> - Mani > --- > Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > index bdfa86a0cc98..861bbf6a57f6 100644 > --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > @@ -27,6 +27,7 @@ properties: > - qcom,msm8996-ufshc > - qcom,msm8998-ufshc > - qcom,sa8775p-ufshc > + - qcom,sc7280-ufshc > - qcom,sc8280xp-ufshc > - qcom,sdm845-ufshc > - qcom,sm6350-ufshc > @@ -111,6 +112,7 @@ allOf: > enum: > - qcom,msm8998-ufshc > - qcom,sa8775p-ufshc > + - qcom,sc7280-ufshc > - qcom,sc8280xp-ufshc > - qcom,sm8250-ufshc > - qcom,sm8350-ufshc > -- > 2.17.1 > -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH V1 2/2] arm64: dts: qcom: sc7280: Add UFS host controller and phy nodes 2023-08-21 9:49 [PATCH V1 0/2] Add UFS host controller and Phy nodes for sc7280 Nitin Rawat 2023-08-21 9:49 ` [PATCH V1 1/2] scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string Nitin Rawat @ 2023-08-21 9:49 ` Nitin Rawat 2023-08-22 7:08 ` Manivannan Sadhasivam 1 sibling, 1 reply; 9+ messages in thread From: Nitin Rawat @ 2023-08-21 9:49 UTC (permalink / raw) To: mani, agross, andersson, konrad.dybcio, alim.akhtar, bvanassche, robh+dt, avri.altman, cros-qcom-dts-watchers, krzysztof.kozlowski+dt, conor+dt Cc: linux-arm-msm, linux-scsi, linux-kernel, devicetree, Nitin Rawat Add UFS host controller and PHY nodes for sc7280. Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 +++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 64 ++++++++++++++++++++++++ 2 files changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 2ff549f4dc7a..c60cdd511222 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -451,6 +451,25 @@ status = "okay"; }; +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l7b_2p9>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c_0p8>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + &sdhc_1 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 925428a5f6ae..d4a15d56b384 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -908,6 +908,70 @@ }; }; + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sc7280-qmp-ufs-phy"; + reg = <0x0 0x01d87000 0x0 0xe00>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_1_CLKREF_EN>; + clock-names = "ref", "ref_aux", "qref"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + + }; + + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sc7280-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x80 0x0>; + dma-coherent; + + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + sdhc_1: mmc@7c4000 { compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; pinctrl-names = "default", "sleep"; -- 2.17.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH V1 2/2] arm64: dts: qcom: sc7280: Add UFS host controller and phy nodes 2023-08-21 9:49 ` [PATCH V1 2/2] arm64: dts: qcom: sc7280: Add UFS host controller and phy nodes Nitin Rawat @ 2023-08-22 7:08 ` Manivannan Sadhasivam 2023-09-26 16:24 ` Nitin Rawat 0 siblings, 1 reply; 9+ messages in thread From: Manivannan Sadhasivam @ 2023-08-22 7:08 UTC (permalink / raw) To: Nitin Rawat Cc: mani, agross, andersson, konrad.dybcio, alim.akhtar, bvanassche, robh+dt, avri.altman, cros-qcom-dts-watchers, krzysztof.kozlowski+dt, conor+dt, linux-arm-msm, linux-scsi, linux-kernel, devicetree On Mon, Aug 21, 2023 at 03:19:37PM +0530, Nitin Rawat wrote: > Add UFS host controller and PHY nodes for sc7280. > You should split this patch into 2. One for SoC and another for board. > Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 +++++++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 64 ++++++++++++++++++++++++ > 2 files changed, 83 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > index 2ff549f4dc7a..c60cdd511222 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi > @@ -451,6 +451,25 @@ > status = "okay"; > }; > > +&ufs_mem_hc { > + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; > + vcc-supply = <&vreg_l7b_2p9>; > + vcc-max-microamp = <800000>; > + vccq-supply = <&vreg_l9b_1p2>; > + vccq-max-microamp = <900000>; > + vccq2-supply = <&vreg_l9b_1p2>; > + vccq2-max-microamp = <900000>; > + > + status = "okay"; > +}; > + > +&ufs_mem_phy { > + vdda-phy-supply = <&vreg_l10c_0p8>; > + vdda-pll-supply = <&vreg_l6b_1p2>; > + > + status = "okay"; > +}; > + > &sdhc_1 { > status = "okay"; > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 925428a5f6ae..d4a15d56b384 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -908,6 +908,70 @@ > }; > }; > > + ufs_mem_phy: phy@1d87000 { Please sort the nodes in ascending order. > + compatible = "qcom,sc7280-qmp-ufs-phy"; > + reg = <0x0 0x01d87000 0x0 0xe00>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, > + <&gcc GCC_UFS_1_CLKREF_EN>; > + clock-names = "ref", "ref_aux", "qref"; > + > + resets = <&ufs_mem_hc 0>; > + reset-names = "ufsphy"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + > + }; > + > + ufs_mem_hc: ufs@1d84000 { > + compatible = "qcom,sc7280-ufshc", "qcom,ufshc", > + "jedec,ufs-2.0"; > + reg = <0x0 0x01d84000 0x0 0x3000>; > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&ufs_mem_phy>; > + phy-names = "ufsphy"; > + lanes-per-direction = <2>; > + #reset-cells = <1>; > + resets = <&gcc GCC_UFS_PHY_BCR>; > + reset-names = "rst"; > + > + power-domains = <&gcc GCC_UFS_PHY_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; > + > + iommus = <&apps_smmu 0x80 0x0>; > + dma-coherent; > + > + clock-names = "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "rx_lane1_sync_clk"; "clocks" property should come first. - Mani > + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_UFS_PHY_AHB_CLK>, > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > + freq-table-hz = > + <75000000 300000000>, > + <0 0>, > + <0 0>, > + <75000000 300000000>, > + <0 0>, > + <0 0>, > + <0 0>, > + <0 0>; > + status = "disabled"; > + }; > + > sdhc_1: mmc@7c4000 { > compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; > pinctrl-names = "default", "sleep"; > -- > 2.17.1 > -- மணிவண்ணன் சதாசிவம் ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH V1 2/2] arm64: dts: qcom: sc7280: Add UFS host controller and phy nodes 2023-08-22 7:08 ` Manivannan Sadhasivam @ 2023-09-26 16:24 ` Nitin Rawat 2023-09-26 17:29 ` Konrad Dybcio 0 siblings, 1 reply; 9+ messages in thread From: Nitin Rawat @ 2023-09-26 16:24 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: agross, andersson, konrad.dybcio, alim.akhtar, bvanassche, robh+dt, avri.altman, cros-qcom-dts-watchers, krzysztof.kozlowski+dt, conor+dt, linux-arm-msm, linux-scsi, linux-kernel, devicetree On 8/22/2023 12:38 PM, Manivannan Sadhasivam wrote: > On Mon, Aug 21, 2023 at 03:19:37PM +0530, Nitin Rawat wrote: >> Add UFS host controller and PHY nodes for sc7280. >> > > You should split this patch into 2. One for SoC and another for board. Updated in Latest Patchset. > >> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 +++++++ >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 64 ++++++++++++++++++++++++ >> 2 files changed, 83 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >> index 2ff549f4dc7a..c60cdd511222 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >> @@ -451,6 +451,25 @@ >> status = "okay"; >> }; >> >> +&ufs_mem_hc { >> + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; >> + vcc-supply = <&vreg_l7b_2p9>; >> + vcc-max-microamp = <800000>; >> + vccq-supply = <&vreg_l9b_1p2>; >> + vccq-max-microamp = <900000>; >> + vccq2-supply = <&vreg_l9b_1p2>; >> + vccq2-max-microamp = <900000>; >> + >> + status = "okay"; >> +}; >> + >> +&ufs_mem_phy { >> + vdda-phy-supply = <&vreg_l10c_0p8>; >> + vdda-pll-supply = <&vreg_l6b_1p2>; >> + >> + status = "okay"; >> +}; >> + >> &sdhc_1 { >> status = "okay"; >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 925428a5f6ae..d4a15d56b384 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -908,6 +908,70 @@ >> }; >> }; >> >> + ufs_mem_phy: phy@1d87000 { > > Please sort the nodes in ascending order. Updated in Latest Patchset. > >> + compatible = "qcom,sc7280-qmp-ufs-phy"; >> + reg = <0x0 0x01d87000 0x0 0xe00>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, >> + <&gcc GCC_UFS_1_CLKREF_EN>; >> + clock-names = "ref", "ref_aux", "qref"; >> + >> + resets = <&ufs_mem_hc 0>; >> + reset-names = "ufsphy"; >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + >> + }; >> + >> + ufs_mem_hc: ufs@1d84000 { >> + compatible = "qcom,sc7280-ufshc", "qcom,ufshc", >> + "jedec,ufs-2.0"; >> + reg = <0x0 0x01d84000 0x0 0x3000>; >> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; >> + phys = <&ufs_mem_phy>; >> + phy-names = "ufsphy"; >> + lanes-per-direction = <2>; >> + #reset-cells = <1>; >> + resets = <&gcc GCC_UFS_PHY_BCR>; >> + reset-names = "rst"; >> + >> + power-domains = <&gcc GCC_UFS_PHY_GDSC>; >> + required-opps = <&rpmhpd_opp_nom>; >> + >> + iommus = <&apps_smmu 0x80 0x0>; >> + dma-coherent; >> + >> + clock-names = "core_clk", >> + "bus_aggr_clk", >> + "iface_clk", >> + "core_clk_unipro", >> + "ref_clk", >> + "tx_lane0_sync_clk", >> + "rx_lane0_sync_clk", >> + "rx_lane1_sync_clk"; > > "clocks" property should come first. DT binding shows clock-names first followed by clocks. Let me know if see still see concern, would update . > > - Mani > >> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_UFS_PHY_AHB_CLK>, >> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, >> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, >> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; >> + freq-table-hz = >> + <75000000 300000000>, >> + <0 0>, >> + <0 0>, >> + <75000000 300000000>, >> + <0 0>, >> + <0 0>, >> + <0 0>, >> + <0 0>; >> + status = "disabled"; >> + }; >> + >> sdhc_1: mmc@7c4000 { >> compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; >> pinctrl-names = "default", "sleep"; >> -- >> 2.17.1 >> > Thanks, Nitin ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH V1 2/2] arm64: dts: qcom: sc7280: Add UFS host controller and phy nodes 2023-09-26 16:24 ` Nitin Rawat @ 2023-09-26 17:29 ` Konrad Dybcio 0 siblings, 0 replies; 9+ messages in thread From: Konrad Dybcio @ 2023-09-26 17:29 UTC (permalink / raw) To: Nitin Rawat, Manivannan Sadhasivam Cc: agross, andersson, alim.akhtar, bvanassche, robh+dt, avri.altman, cros-qcom-dts-watchers, krzysztof.kozlowski+dt, conor+dt, linux-arm-msm, linux-scsi, linux-kernel, devicetree On 26.09.2023 18:24, Nitin Rawat wrote: > > > On 8/22/2023 12:38 PM, Manivannan Sadhasivam wrote: >> On Mon, Aug 21, 2023 at 03:19:37PM +0530, Nitin Rawat wrote: >>> Add UFS host controller and PHY nodes for sc7280. >>> >> >> You should split this patch into 2. One for SoC and another for board. > Updated in Latest Patchset. > >> >>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 +++++++ >>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 64 ++++++++++++++++++++++++ >>> 2 files changed, 83 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >>> index 2ff549f4dc7a..c60cdd511222 100644 >>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi >>> @@ -451,6 +451,25 @@ >>> status = "okay"; >>> }; >>> >>> +&ufs_mem_hc { >>> + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; >>> + vcc-supply = <&vreg_l7b_2p9>; >>> + vcc-max-microamp = <800000>; >>> + vccq-supply = <&vreg_l9b_1p2>; >>> + vccq-max-microamp = <900000>; >>> + vccq2-supply = <&vreg_l9b_1p2>; >>> + vccq2-max-microamp = <900000>; >>> + >>> + status = "okay"; >>> +}; >>> + >>> +&ufs_mem_phy { >>> + vdda-phy-supply = <&vreg_l10c_0p8>; >>> + vdda-pll-supply = <&vreg_l6b_1p2>; >>> + >>> + status = "okay"; >>> +}; >>> + >>> &sdhc_1 { >>> status = "okay"; >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> index 925428a5f6ae..d4a15d56b384 100644 >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> @@ -908,6 +908,70 @@ >>> }; >>> }; >>> >>> + ufs_mem_phy: phy@1d87000 { >> >> Please sort the nodes in ascending order. > Updated in Latest Patchset. > >> >>> + compatible = "qcom,sc7280-qmp-ufs-phy"; >>> + reg = <0x0 0x01d87000 0x0 0xe00>; >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, >>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, >>> + <&gcc GCC_UFS_1_CLKREF_EN>; >>> + clock-names = "ref", "ref_aux", "qref"; >>> + >>> + resets = <&ufs_mem_hc 0>; >>> + reset-names = "ufsphy"; >>> + >>> + #clock-cells = <1>; >>> + #phy-cells = <0>; >>> + >>> + status = "disabled"; >>> + >>> + }; >>> + >>> + ufs_mem_hc: ufs@1d84000 { >>> + compatible = "qcom,sc7280-ufshc", "qcom,ufshc", >>> + "jedec,ufs-2.0"; >>> + reg = <0x0 0x01d84000 0x0 0x3000>; >>> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; >>> + phys = <&ufs_mem_phy>; >>> + phy-names = "ufsphy"; >>> + lanes-per-direction = <2>; >>> + #reset-cells = <1>; >>> + resets = <&gcc GCC_UFS_PHY_BCR>; >>> + reset-names = "rst"; >>> + >>> + power-domains = <&gcc GCC_UFS_PHY_GDSC>; >>> + required-opps = <&rpmhpd_opp_nom>; >>> + >>> + iommus = <&apps_smmu 0x80 0x0>; >>> + dma-coherent; >>> + >>> + clock-names = "core_clk", >>> + "bus_aggr_clk", >>> + "iface_clk", >>> + "core_clk_unipro", >>> + "ref_clk", >>> + "tx_lane0_sync_clk", >>> + "rx_lane0_sync_clk", >>> + "rx_lane1_sync_clk"; >> >> "clocks" property should come first. > DT binding shows clock-names first followed by clocks. > Let me know if see still see concern, would update . The dt bindings example is rarely useful.. perhaps we should change that.. The general consensus there is to have property property-names Konrad ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-09-26 17:29 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-08-21 9:49 [PATCH V1 0/2] Add UFS host controller and Phy nodes for sc7280 Nitin Rawat 2023-08-21 9:49 ` [PATCH V1 1/2] scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string Nitin Rawat 2023-08-21 12:14 ` Krzysztof Kozlowski 2023-08-21 14:15 ` Bao D. Nguyen 2023-08-22 7:09 ` Manivannan Sadhasivam 2023-08-21 9:49 ` [PATCH V1 2/2] arm64: dts: qcom: sc7280: Add UFS host controller and phy nodes Nitin Rawat 2023-08-22 7:08 ` Manivannan Sadhasivam 2023-09-26 16:24 ` Nitin Rawat 2023-09-26 17:29 ` Konrad Dybcio
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