* [PATCH 0/5] arm64: dts: imx8qxp add emda support
@ 2023-08-22 15:53 Frank Li
2023-08-22 15:53 ` [PATCH 1/5] firmware: imx: scu-pd: added missing edma channel power domain Frank Li
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Frank Li @ 2023-08-22 15:53 UTC (permalink / raw)
To: frank.li, shawnguo, joy.zou, shenwei.wang, sherry.sun
Cc: clin, conor+dt, devicetree, eagle.zhou, festevam, imx, kernel,
krzysztof.kozlowski+dt, leoyang.li, linux-arm-kernel, linux-imx,
linux-kernel, pierre.gondois, robh+dt, s.hauer
eDMAv3 patch was accepted.
https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git/log/?h=next
This is dts parts.
Add 8qxp edma support and enable lpuart1..3 dma support.
Frank Li (5):
firmware: imx: scu-pd: added missing edma channel power domain
arm64: dts: imx8: add edma[0..3]
arm64: dts: imx8: Add edma for uart[1..3]
arm64: dts: imx8: update lpuart[0..3] irq number
arm64: dts: imx8qxp-mek: enable 8qxp lpuart2 and lpuart3
.../boot/dts/freescale/imx8-ss-audio.dtsi | 88 +++++++++++++++++++
.../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 76 +++++++++++++++-
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 30 +++++++
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 26 ++++++
drivers/firmware/imx/scu-pd.c | 6 +-
5 files changed, 220 insertions(+), 6 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/5] firmware: imx: scu-pd: added missing edma channel power domain
2023-08-22 15:53 [PATCH 0/5] arm64: dts: imx8qxp add emda support Frank Li
@ 2023-08-22 15:53 ` Frank Li
2023-09-25 0:27 ` Shawn Guo
2023-08-22 15:53 ` [PATCH 2/5] arm64: dts: imx8: add edma[0..3] Frank Li
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Frank Li @ 2023-08-22 15:53 UTC (permalink / raw)
To: frank.li, shawnguo, joy.zou, shenwei.wang, sherry.sun
Cc: clin, conor+dt, devicetree, eagle.zhou, festevam, imx, kernel,
krzysztof.kozlowski+dt, leoyang.li, linux-arm-kernel, linux-imx,
linux-kernel, pierre.gondois, robh+dt, s.hauer
There are more power resources for dma channel at 8qxp and 8qm.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/firmware/imx/scu-pd.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c
index 84b673427073..7d80eabd7941 100644
--- a/drivers/firmware/imx/scu-pd.c
+++ b/drivers/firmware/imx/scu-pd.c
@@ -121,9 +121,11 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = {
{ "audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, false, 0 },
{ "audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, false, 0 },
{ "audio-clk-1", IMX_SC_R_AUDIO_CLK_1, 1, false, 0 },
- { "dma0-ch", IMX_SC_R_DMA_0_CH0, 16, true, 0 },
+ { "dma0-ch", IMX_SC_R_DMA_0_CH0, 32, true, 0 },
{ "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 },
- { "dma2-ch", IMX_SC_R_DMA_2_CH0, 5, true, 0 },
+ { "dma2-ch-0", IMX_SC_R_DMA_2_CH0, 5, true, 0 },
+ { "dma2-ch-1", IMX_SC_R_DMA_2_CH5, 27, true, 0 },
+ { "dma3-ch", IMX_SC_R_DMA_3_CH0, 32, true, 0 },
{ "asrc0", IMX_SC_R_ASRC_0, 1, false, 0 },
{ "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 },
{ "esai0", IMX_SC_R_ESAI_0, 1, false, 0 },
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/5] arm64: dts: imx8: add edma[0..3]
2023-08-22 15:53 [PATCH 0/5] arm64: dts: imx8qxp add emda support Frank Li
2023-08-22 15:53 ` [PATCH 1/5] firmware: imx: scu-pd: added missing edma channel power domain Frank Li
@ 2023-08-22 15:53 ` Frank Li
2023-09-25 0:29 ` Shawn Guo
2023-08-22 15:53 ` [PATCH 3/5] arm64: dts: imx8: Add edma for uart[1..3] Frank Li
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Frank Li @ 2023-08-22 15:53 UTC (permalink / raw)
To: frank.li, shawnguo, joy.zou, shenwei.wang, sherry.sun
Cc: clin, conor+dt, devicetree, eagle.zhou, festevam, imx, kernel,
krzysztof.kozlowski+dt, leoyang.li, linux-arm-kernel, linux-imx,
linux-kernel, pierre.gondois, robh+dt, s.hauer
edma<n> is missed, add them
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../boot/dts/freescale/imx8-ss-audio.dtsi | 88 +++++++++++++++++++
.../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 62 +++++++++++++
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 30 +++++++
3 files changed, 180 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
index 6c8d75ef9250..8870acf8f743 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
@@ -20,6 +20,63 @@ audio_ipg_clk: clock-audio-ipg {
clock-output-names = "audio_ipg_clk";
};
+ edma0: dma-controller@591F0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x591f0000 0x190000>;
+ #dma-cells = <3>;
+ shared-interrupt;
+ dma-channels = <24>;
+ dma-channel-mask = <0x5c0c00>;
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 0 */
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, /* 1 */
+ <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, /* 2 */
+ <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, /* 3 */
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, /* 4 */
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, /* 5 */
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 6 esai0 */
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 7 */
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* 8 spdif0 */
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, /* 9 */
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 10 unused */
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 11 unused */
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 12 sai0 */
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 13 */
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 14 sai1 */
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 15 */
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* 16 sai2 */
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* 17 sai3 */
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 18 unused */
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 19 unused */
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 20 unused */
+ <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, /* 21 */
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 22 unused */
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; /* 23 unused */
+ power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
+ <&pd IMX_SC_R_DMA_0_CH1>,
+ <&pd IMX_SC_R_DMA_0_CH2>,
+ <&pd IMX_SC_R_DMA_0_CH3>,
+ <&pd IMX_SC_R_DMA_0_CH4>,
+ <&pd IMX_SC_R_DMA_0_CH5>,
+ <&pd IMX_SC_R_DMA_0_CH6>,
+ <&pd IMX_SC_R_DMA_0_CH7>,
+ <&pd IMX_SC_R_DMA_0_CH8>,
+ <&pd IMX_SC_R_DMA_0_CH9>,
+ <&pd IMX_SC_R_DMA_0_CH10>,
+ <&pd IMX_SC_R_DMA_0_CH11>,
+ <&pd IMX_SC_R_DMA_0_CH12>,
+ <&pd IMX_SC_R_DMA_0_CH13>,
+ <&pd IMX_SC_R_DMA_0_CH14>,
+ <&pd IMX_SC_R_DMA_0_CH15>,
+ <&pd IMX_SC_R_DMA_0_CH16>,
+ <&pd IMX_SC_R_DMA_0_CH17>,
+ <&pd IMX_SC_R_DMA_0_CH18>,
+ <&pd IMX_SC_R_DMA_0_CH19>,
+ <&pd IMX_SC_R_DMA_0_CH20>,
+ <&pd IMX_SC_R_DMA_0_CH21>,
+ <&pd IMX_SC_R_DMA_0_CH22>,
+ <&pd IMX_SC_R_DMA_0_CH23>;
+ };
+
dsp_lpcg: clock-controller@59580000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59580000 0x10000>;
@@ -65,4 +122,35 @@ dsp: dsp@596e8000 {
memory-region = <&dsp_reserved>;
status = "disabled";
};
+
+ edma1: dma-controller@599f0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x599f0000 0xc0000>;
+ #dma-cells = <3>;
+ shared-interrupt;
+ dma-channels = <11>;
+ dma-channel-mask = <0xc0>;
+ interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 1 */
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, /* 1 */
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, /* 2 */
+ <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, /* 3 */
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, /* 4 */
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, /* 5 */
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 6 unused */
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 7 unused */
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
+ power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
+ <&pd IMX_SC_R_DMA_1_CH1>,
+ <&pd IMX_SC_R_DMA_1_CH2>,
+ <&pd IMX_SC_R_DMA_1_CH3>,
+ <&pd IMX_SC_R_DMA_1_CH4>,
+ <&pd IMX_SC_R_DMA_1_CH5>,
+ <&pd IMX_SC_R_DMA_1_CH6>,
+ <&pd IMX_SC_R_DMA_1_CH7>,
+ <&pd IMX_SC_R_DMA_1_CH8>,
+ <&pd IMX_SC_R_DMA_1_CH9>,
+ <&pd IMX_SC_R_DMA_1_CH10>;
+ };
};
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index adb98a72bdfd..76e4aaaf307f 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -132,6 +132,68 @@ lpuart3: serial@5a090000 {
status = "disabled";
};
+ edma2: dma-controller@5a1f0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x5a1f0000 0x170000>;
+ #dma-cells = <3>;
+ dma-channels = <16>;
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
+ <&pd IMX_SC_R_DMA_2_CH1>,
+ <&pd IMX_SC_R_DMA_2_CH2>,
+ <&pd IMX_SC_R_DMA_2_CH3>,
+ <&pd IMX_SC_R_DMA_2_CH4>,
+ <&pd IMX_SC_R_DMA_2_CH5>,
+ <&pd IMX_SC_R_DMA_2_CH6>,
+ <&pd IMX_SC_R_DMA_2_CH7>,
+ <&pd IMX_SC_R_DMA_2_CH8>,
+ <&pd IMX_SC_R_DMA_2_CH9>,
+ <&pd IMX_SC_R_DMA_2_CH10>,
+ <&pd IMX_SC_R_DMA_2_CH11>,
+ <&pd IMX_SC_R_DMA_2_CH12>,
+ <&pd IMX_SC_R_DMA_2_CH13>,
+ <&pd IMX_SC_R_DMA_2_CH14>,
+ <&pd IMX_SC_R_DMA_2_CH15>;
+ };
+
+ edma3: dma-controller@5a9f0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x5a9f0000 0x90000>;
+ #dma-cells = <3>;
+ dma-channels = <8>;
+ interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
+ <&pd IMX_SC_R_DMA_3_CH1>,
+ <&pd IMX_SC_R_DMA_3_CH2>,
+ <&pd IMX_SC_R_DMA_3_CH3>,
+ <&pd IMX_SC_R_DMA_3_CH4>,
+ <&pd IMX_SC_R_DMA_3_CH5>,
+ <&pd IMX_SC_R_DMA_3_CH6>,
+ <&pd IMX_SC_R_DMA_3_CH7>;
+ };
+
spi0_lpcg: clock-controller@5a400000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a400000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
index 6881330ab4c6..7e98c5e5624b 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -15,6 +15,36 @@ &adc0 {
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
};
+&edma2 {
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&edma3 {
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&i2c0 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/5] arm64: dts: imx8: Add edma for uart[1..3]
2023-08-22 15:53 [PATCH 0/5] arm64: dts: imx8qxp add emda support Frank Li
2023-08-22 15:53 ` [PATCH 1/5] firmware: imx: scu-pd: added missing edma channel power domain Frank Li
2023-08-22 15:53 ` [PATCH 2/5] arm64: dts: imx8: add edma[0..3] Frank Li
@ 2023-08-22 15:53 ` Frank Li
2023-08-22 15:53 ` [PATCH 4/5] arm64: dts: imx8: update lpuart[0..3] irq number Frank Li
2023-08-22 15:53 ` [PATCH 5/5] arm64: dts: imx8qxp-mek: enable 8qxp lpuart2 and lpuart3 Frank Li
4 siblings, 0 replies; 8+ messages in thread
From: Frank Li @ 2023-08-22 15:53 UTC (permalink / raw)
To: frank.li, shawnguo, joy.zou, shenwei.wang, sherry.sun
Cc: clin, conor+dt, devicetree, eagle.zhou, festevam, imx, kernel,
krzysztof.kozlowski+dt, leoyang.li, linux-arm-kernel, linux-imx,
linux-kernel, pierre.gondois, robh+dt, s.hauer
Add dma support uart[1..3].
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index 76e4aaaf307f..92ed02e6048c 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -105,6 +105,8 @@ lpuart1: serial@5a070000 {
assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_1>;
+ dma-names = "tx","rx";
+ dmas = <&edma2 11 0 0>, <&edma2 10 0 1>;
status = "disabled";
};
@@ -117,6 +119,8 @@ lpuart2: serial@5a080000 {
assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_2>;
+ dma-names = "tx","rx";
+ dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
status = "disabled";
};
@@ -129,6 +133,8 @@ lpuart3: serial@5a090000 {
assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <80000000>;
power-domains = <&pd IMX_SC_R_UART_3>;
+ dma-names = "tx","rx";
+ dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
status = "disabled";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/5] arm64: dts: imx8: update lpuart[0..3] irq number
2023-08-22 15:53 [PATCH 0/5] arm64: dts: imx8qxp add emda support Frank Li
` (2 preceding siblings ...)
2023-08-22 15:53 ` [PATCH 3/5] arm64: dts: imx8: Add edma for uart[1..3] Frank Li
@ 2023-08-22 15:53 ` Frank Li
2023-08-22 15:53 ` [PATCH 5/5] arm64: dts: imx8qxp-mek: enable 8qxp lpuart2 and lpuart3 Frank Li
4 siblings, 0 replies; 8+ messages in thread
From: Frank Li @ 2023-08-22 15:53 UTC (permalink / raw)
To: frank.li, shawnguo, joy.zou, shenwei.wang, sherry.sun
Cc: clin, conor+dt, devicetree, eagle.zhou, festevam, imx, kernel,
krzysztof.kozlowski+dt, leoyang.li, linux-arm-kernel, linux-imx,
linux-kernel, pierre.gondois, robh+dt, s.hauer
Original irq number combined UART irq and DMA irq. These doesn't match
uart driver and dma engine's expection.
Update to the irq numbers, which just uart can trigger.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index 92ed02e6048c..f26f8ee5d2f1 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -86,7 +86,7 @@ lpspi3: spi@5a030000 {
lpuart0: serial@5a060000 {
reg = <0x5a060000 0x1000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
<&uart0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
@@ -98,7 +98,7 @@ lpuart0: serial@5a060000 {
lpuart1: serial@5a070000 {
reg = <0x5a070000 0x1000>;
- interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
<&uart1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
@@ -112,7 +112,7 @@ lpuart1: serial@5a070000 {
lpuart2: serial@5a080000 {
reg = <0x5a080000 0x1000>;
- interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
<&uart2_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
@@ -126,7 +126,7 @@ lpuart2: serial@5a080000 {
lpuart3: serial@5a090000 {
reg = <0x5a090000 0x1000>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
<&uart3_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 5/5] arm64: dts: imx8qxp-mek: enable 8qxp lpuart2 and lpuart3
2023-08-22 15:53 [PATCH 0/5] arm64: dts: imx8qxp add emda support Frank Li
` (3 preceding siblings ...)
2023-08-22 15:53 ` [PATCH 4/5] arm64: dts: imx8: update lpuart[0..3] irq number Frank Li
@ 2023-08-22 15:53 ` Frank Li
4 siblings, 0 replies; 8+ messages in thread
From: Frank Li @ 2023-08-22 15:53 UTC (permalink / raw)
To: frank.li, shawnguo, joy.zou, shenwei.wang, sherry.sun
Cc: clin, conor+dt, devicetree, eagle.zhou, festevam, imx, kernel,
krzysztof.kozlowski+dt, leoyang.li, linux-arm-kernel, linux-imx,
linux-kernel, pierre.gondois, robh+dt, s.hauer
Enable uart2 and uart5 for imx8qxp-mek board.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 7924b0969ad8..99611729943c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -187,6 +187,18 @@ &lpuart0 {
status = "okay";
};
+&lpuart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart2>;
+ status = "okay";
+};
+
+&lpuart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart3>;
+ status = "okay";
+};
+
&mu_m0 {
status = "okay";
};
@@ -340,6 +352,20 @@ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
+ pinctrl_lpuart2: lpuart2grp {
+ fsl,pins = <
+ IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020
+ IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020
+ >;
+ };
+
+ pinctrl_lpuart3: lpuart3grp {
+ fsl,pins = <
+ IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
+ IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
+ >;
+ };
+
pinctrl_typec: typecgrp {
fsl,pins = <
IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/5] firmware: imx: scu-pd: added missing edma channel power domain
2023-08-22 15:53 ` [PATCH 1/5] firmware: imx: scu-pd: added missing edma channel power domain Frank Li
@ 2023-09-25 0:27 ` Shawn Guo
0 siblings, 0 replies; 8+ messages in thread
From: Shawn Guo @ 2023-09-25 0:27 UTC (permalink / raw)
To: Frank Li
Cc: joy.zou, shenwei.wang, sherry.sun, clin, conor+dt, devicetree,
eagle.zhou, festevam, imx, kernel, krzysztof.kozlowski+dt,
leoyang.li, linux-arm-kernel, linux-imx, linux-kernel,
pierre.gondois, robh+dt, s.hauer
On Tue, Aug 22, 2023 at 11:53:29AM -0400, Frank Li wrote:
> There are more power resources for dma channel at 8qxp and 8qm.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
Could you rebase on v6.6-rc1?
Shawn
> ---
> drivers/firmware/imx/scu-pd.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c
> index 84b673427073..7d80eabd7941 100644
> --- a/drivers/firmware/imx/scu-pd.c
> +++ b/drivers/firmware/imx/scu-pd.c
> @@ -121,9 +121,11 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = {
> { "audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, false, 0 },
> { "audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, false, 0 },
> { "audio-clk-1", IMX_SC_R_AUDIO_CLK_1, 1, false, 0 },
> - { "dma0-ch", IMX_SC_R_DMA_0_CH0, 16, true, 0 },
> + { "dma0-ch", IMX_SC_R_DMA_0_CH0, 32, true, 0 },
> { "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 },
> - { "dma2-ch", IMX_SC_R_DMA_2_CH0, 5, true, 0 },
> + { "dma2-ch-0", IMX_SC_R_DMA_2_CH0, 5, true, 0 },
> + { "dma2-ch-1", IMX_SC_R_DMA_2_CH5, 27, true, 0 },
> + { "dma3-ch", IMX_SC_R_DMA_3_CH0, 32, true, 0 },
> { "asrc0", IMX_SC_R_ASRC_0, 1, false, 0 },
> { "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 },
> { "esai0", IMX_SC_R_ESAI_0, 1, false, 0 },
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/5] arm64: dts: imx8: add edma[0..3]
2023-08-22 15:53 ` [PATCH 2/5] arm64: dts: imx8: add edma[0..3] Frank Li
@ 2023-09-25 0:29 ` Shawn Guo
0 siblings, 0 replies; 8+ messages in thread
From: Shawn Guo @ 2023-09-25 0:29 UTC (permalink / raw)
To: Frank Li
Cc: joy.zou, shenwei.wang, sherry.sun, clin, conor+dt, devicetree,
eagle.zhou, festevam, imx, kernel, krzysztof.kozlowski+dt,
leoyang.li, linux-arm-kernel, linux-imx, linux-kernel,
pierre.gondois, robh+dt, s.hauer
On Tue, Aug 22, 2023 at 11:53:30AM -0400, Frank Li wrote:
> edma<n> is missed, add them
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> .../boot/dts/freescale/imx8-ss-audio.dtsi | 88 +++++++++++++++++++
> .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 62 +++++++++++++
> .../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 30 +++++++
> 3 files changed, 180 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> index 6c8d75ef9250..8870acf8f743 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> @@ -20,6 +20,63 @@ audio_ipg_clk: clock-audio-ipg {
> clock-output-names = "audio_ipg_clk";
> };
>
> + edma0: dma-controller@591F0000 {
Lowercase for hex value.
> + compatible = "fsl,imx8qm-edma";
> + reg = <0x591f0000 0x190000>;
One space after =
> + #dma-cells = <3>;
> + shared-interrupt;
> + dma-channels = <24>;
> + dma-channel-mask = <0x5c0c00>;
> + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 0 */
> + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, /* 1 */
> + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, /* 2 */
> + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, /* 3 */
> + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, /* 4 */
> + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, /* 5 */
> + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 6 esai0 */
> + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 7 */
> + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* 8 spdif0 */
> + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, /* 9 */
> + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 10 unused */
> + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 11 unused */
> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 12 sai0 */
> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 13 */
> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 14 sai1 */
> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 15 */
> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* 16 sai2 */
> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* 17 sai3 */
> + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 18 unused */
> + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 19 unused */
> + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 20 unused */
> + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, /* 21 */
> + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 22 unused */
> + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; /* 23 unused */
> + power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
> + <&pd IMX_SC_R_DMA_0_CH1>,
> + <&pd IMX_SC_R_DMA_0_CH2>,
> + <&pd IMX_SC_R_DMA_0_CH3>,
> + <&pd IMX_SC_R_DMA_0_CH4>,
> + <&pd IMX_SC_R_DMA_0_CH5>,
> + <&pd IMX_SC_R_DMA_0_CH6>,
> + <&pd IMX_SC_R_DMA_0_CH7>,
> + <&pd IMX_SC_R_DMA_0_CH8>,
> + <&pd IMX_SC_R_DMA_0_CH9>,
> + <&pd IMX_SC_R_DMA_0_CH10>,
> + <&pd IMX_SC_R_DMA_0_CH11>,
> + <&pd IMX_SC_R_DMA_0_CH12>,
> + <&pd IMX_SC_R_DMA_0_CH13>,
> + <&pd IMX_SC_R_DMA_0_CH14>,
> + <&pd IMX_SC_R_DMA_0_CH15>,
> + <&pd IMX_SC_R_DMA_0_CH16>,
> + <&pd IMX_SC_R_DMA_0_CH17>,
> + <&pd IMX_SC_R_DMA_0_CH18>,
> + <&pd IMX_SC_R_DMA_0_CH19>,
> + <&pd IMX_SC_R_DMA_0_CH20>,
> + <&pd IMX_SC_R_DMA_0_CH21>,
> + <&pd IMX_SC_R_DMA_0_CH22>,
> + <&pd IMX_SC_R_DMA_0_CH23>;
> + };
> +
> dsp_lpcg: clock-controller@59580000 {
> compatible = "fsl,imx8qxp-lpcg";
> reg = <0x59580000 0x10000>;
> @@ -65,4 +122,35 @@ dsp: dsp@596e8000 {
> memory-region = <&dsp_reserved>;
> status = "disabled";
> };
> +
> + edma1: dma-controller@599f0000 {
> + compatible = "fsl,imx8qm-edma";
> + reg = <0x599f0000 0xc0000>;
Ditto
Shawn
> + #dma-cells = <3>;
> + shared-interrupt;
> + dma-channels = <11>;
> + dma-channel-mask = <0xc0>;
> + interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 1 */
> + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, /* 1 */
> + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, /* 2 */
> + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, /* 3 */
> + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, /* 4 */
> + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, /* 5 */
> + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 6 unused */
> + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 7 unused */
> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
> + power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
> + <&pd IMX_SC_R_DMA_1_CH1>,
> + <&pd IMX_SC_R_DMA_1_CH2>,
> + <&pd IMX_SC_R_DMA_1_CH3>,
> + <&pd IMX_SC_R_DMA_1_CH4>,
> + <&pd IMX_SC_R_DMA_1_CH5>,
> + <&pd IMX_SC_R_DMA_1_CH6>,
> + <&pd IMX_SC_R_DMA_1_CH7>,
> + <&pd IMX_SC_R_DMA_1_CH8>,
> + <&pd IMX_SC_R_DMA_1_CH9>,
> + <&pd IMX_SC_R_DMA_1_CH10>;
> + };
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> index adb98a72bdfd..76e4aaaf307f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> @@ -132,6 +132,68 @@ lpuart3: serial@5a090000 {
> status = "disabled";
> };
>
> + edma2: dma-controller@5a1f0000 {
> + compatible = "fsl,imx8qm-edma";
> + reg = <0x5a1f0000 0x170000>;
> + #dma-cells = <3>;
> + dma-channels = <16>;
> + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
> + <&pd IMX_SC_R_DMA_2_CH1>,
> + <&pd IMX_SC_R_DMA_2_CH2>,
> + <&pd IMX_SC_R_DMA_2_CH3>,
> + <&pd IMX_SC_R_DMA_2_CH4>,
> + <&pd IMX_SC_R_DMA_2_CH5>,
> + <&pd IMX_SC_R_DMA_2_CH6>,
> + <&pd IMX_SC_R_DMA_2_CH7>,
> + <&pd IMX_SC_R_DMA_2_CH8>,
> + <&pd IMX_SC_R_DMA_2_CH9>,
> + <&pd IMX_SC_R_DMA_2_CH10>,
> + <&pd IMX_SC_R_DMA_2_CH11>,
> + <&pd IMX_SC_R_DMA_2_CH12>,
> + <&pd IMX_SC_R_DMA_2_CH13>,
> + <&pd IMX_SC_R_DMA_2_CH14>,
> + <&pd IMX_SC_R_DMA_2_CH15>;
> + };
> +
> + edma3: dma-controller@5a9f0000 {
> + compatible = "fsl,imx8qm-edma";
> + reg = <0x5a9f0000 0x90000>;
> + #dma-cells = <3>;
> + dma-channels = <8>;
> + interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
> + <&pd IMX_SC_R_DMA_3_CH1>,
> + <&pd IMX_SC_R_DMA_3_CH2>,
> + <&pd IMX_SC_R_DMA_3_CH3>,
> + <&pd IMX_SC_R_DMA_3_CH4>,
> + <&pd IMX_SC_R_DMA_3_CH5>,
> + <&pd IMX_SC_R_DMA_3_CH6>,
> + <&pd IMX_SC_R_DMA_3_CH7>;
> + };
> +
> spi0_lpcg: clock-controller@5a400000 {
> compatible = "fsl,imx8qxp-lpcg";
> reg = <0x5a400000 0x10000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> index 6881330ab4c6..7e98c5e5624b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> @@ -15,6 +15,36 @@ &adc0 {
> interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> +&edma2 {
> + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&edma3 {
> + interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> &i2c0 {
> compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-09-25 0:30 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-08-22 15:53 [PATCH 0/5] arm64: dts: imx8qxp add emda support Frank Li
2023-08-22 15:53 ` [PATCH 1/5] firmware: imx: scu-pd: added missing edma channel power domain Frank Li
2023-09-25 0:27 ` Shawn Guo
2023-08-22 15:53 ` [PATCH 2/5] arm64: dts: imx8: add edma[0..3] Frank Li
2023-09-25 0:29 ` Shawn Guo
2023-08-22 15:53 ` [PATCH 3/5] arm64: dts: imx8: Add edma for uart[1..3] Frank Li
2023-08-22 15:53 ` [PATCH 4/5] arm64: dts: imx8: update lpuart[0..3] irq number Frank Li
2023-08-22 15:53 ` [PATCH 5/5] arm64: dts: imx8qxp-mek: enable 8qxp lpuart2 and lpuart3 Frank Li
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