[PATCH v5 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[PATCH v5 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[Jim Quinlan]

v5 -- Remove DT property "brcm,completion-timeout-us" from	 
      "DT bindings" commit.  Although this error may be reported	 
      as a completion timeout, its cause was traced to an	 
      internal bus timeout which may occur even when there is	 
      no PCIe access being processed.  We set a timeout of four	 
      seconds only if we are operating in "L1SS CLKREQ#" mode.
   -- Correct CEM 2.0 reference provided by HW engineer,
      s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
   -- Add newline to dev_info() string (Stefan)
   -- Change variable rval to unsigned (Stefan)
   -- s/implementaion/implementation/ (Bjorn)
   -- s/superpowersave/powersupersave/ (Bjorn)
   -- Slightly modify message on "PERST#" commit.
   -- Rebase to torvalds master

v4 -- New commit that asserts PERST# for 2711/RPi SOCs at PCIe RC
      driver probe() time.  This is done in Raspian Linux and its
      absence may be the cause of a failing test case.
   -- New commit that removes stale comment.

v3 -- Rewrote commit msgs and comments refering panics if L1SS
      is enabled/disabled; the code snippet that unadvertises L1SS
      eliminates the panic scenario. (Bjorn)
   -- Add reference for "400ns of CLKREQ# assertion" blurb (Bjorn)
   -- Put binding names in DT commit Subject (Bjorn)
   -- Add a verb to a commit's subject line (Bjorn)
   -- s/accomodat(\w+)/accommodat$1/g (Bjorn)
   -- Rewrote commit msgs and comments refering panics if L1SS
      is enabled/disabled; the code snippet that unadvertises L1SS
      eliminates the panic scenario. (Bjorn)

v2 -- Changed binding property 'brcm,completion-timeout-msec' to
      'brcm,completion-timeout-us'.  (StefanW for standard suffix).
   -- Warn when clamping timeout value, and include clamped
      region in message. Also add min and max in YAML. (StefanW)
   -- Qualify description of "brcm,completion-timeout-us" so that
      it refers to PCIe transactions. (StefanW)
   -- Remvove mention of Linux specifics in binding description. (StefanW)
   -- s/clkreq#/CLKREQ#/g (Bjorn)
   -- Refactor completion-timeout-us code to compare max and min to
      value given by the property (as opposed to the computed value).

v1 -- The current driver assumes the downstream devices can
      provide CLKREQ# for ASPM.  These commits accomodate devices
      w/ or w/o clkreq# and also handle L1SS-capable devices.

   -- The Raspian Linux folks have already been using a PCIe RC
      property "brcm,enable-l1ss".  These commits use the same
      property, in a backward-compatible manner, and the implementaion
      adds more detail and also automatically identifies devices w/o
      a clkreq# signal, i.e. most devices plugged into an RPi CM4
      IO board.

Jim Quinlan (5):
  dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property
  PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream
    device
  PCI: brcmstb: Set higher value for internal bus timeout
  PCI: brcmstb: Don't assume 2711 bootloader leaves PERST# asserted
  PCI: brcmstb: Remove stale comment

 .../bindings/pci/brcm,stb-pcie.yaml           |  9 ++
 drivers/pci/controller/pcie-brcmstb.c         | 91 ++++++++++++++++---
 2 files changed, 89 insertions(+), 11 deletions(-)


base-commit: ac9a78681b921877518763ba0e89202254349d1b
-- 
2.17.1

[PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Jim Quinlan]

This commit adds the boolean "brcm,enable-l1ss" property:

  The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
  requires the driver probe() to deliberately place the HW one of three
  CLKREQ# modes:

  (a) CLKREQ# driven by the RC unconditionally
  (b) CLKREQ# driven by the EP for ASPM L0s, L1
  (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).

  The HW+driver can tell the difference between downstream devices that
  need (a) and (b), but does not know when to configure (c).  All devices
  should work fine when the driver chooses (a) or (b), but (c) may be
  desired to realize the extra power savings that L1SS offers.  So we
  introduce the boolean "brcm,enable-l1ss" property to inform the driver
  that (c) is desired.  Setting this property only makes sense when the
  downstream device is L1SS-capable and the OS is configured to activate
  this mode (e.g. policy==powersupersave).

  This property is already present in the Raspian version of Linux, but the
  upstream driver implementation that follows adds more details and
  discerns between (a) and (b).

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 7e15aae7d69e..8b61c2179608 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -64,6 +64,15 @@ properties:
 
   aspm-no-l0s: true
 
+  brcm,enable-l1ss:
+    description: Indicates that PCIe L1SS power savings
+      are desired, the downstream device is L1SS-capable, and the
+      OS has been configured to enable this mode.  For boards
+      using a mini-card connector, this mode may not meet the
+      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
+      of the PCI Express Mini CEM 2.0 specification.
+    type: boolean
+
   brcm,scb-sizes:
     description: u64 giving the 64bit PCIe memory
       viewport size of a memory controller.  There may be up to
-- 
2.17.1

Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Manivannan Sadhasivam]

On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> This commit adds the boolean "brcm,enable-l1ss" property:
> 
>   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
>   requires the driver probe() to deliberately place the HW one of three
>   CLKREQ# modes:
> 
>   (a) CLKREQ# driven by the RC unconditionally
>   (b) CLKREQ# driven by the EP for ASPM L0s, L1
>   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> 
>   The HW+driver can tell the difference between downstream devices that
>   need (a) and (b), but does not know when to configure (c).  All devices
>   should work fine when the driver chooses (a) or (b), but (c) may be
>   desired to realize the extra power savings that L1SS offers.  So we
>   introduce the boolean "brcm,enable-l1ss" property to inform the driver
>   that (c) is desired.  Setting this property only makes sense when the
>   downstream device is L1SS-capable and the OS is configured to activate
>   this mode (e.g. policy==powersupersave).
> 
>   This property is already present in the Raspian version of Linux, but the
>   upstream driver implementation that follows adds more details and
>   discerns between (a) and (b).
> 
> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> index 7e15aae7d69e..8b61c2179608 100644
> --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> @@ -64,6 +64,15 @@ properties:
>  
>    aspm-no-l0s: true
>  
> +  brcm,enable-l1ss:
> +    description: Indicates that PCIe L1SS power savings
> +      are desired, the downstream device is L1SS-capable, and the
> +      OS has been configured to enable this mode.  For boards
> +      using a mini-card connector, this mode may not meet the
> +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> +      of the PCI Express Mini CEM 2.0 specification.

As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
the hardware capability and not system/OS behavior. If this flag specifies
whether the PCIe controller supports L1SS or not, then it is fine but apparantly
this specifies that all downstream devices are L1SS capable which you cannot
guarantee unless you poke into their LNKCAP during runtime.

You should handle this in the driver itself.

- Mani

> +    type: boolean
> +
>    brcm,scb-sizes:
>      description: u64 giving the 64bit PCIe memory
>        viewport size of a memory controller.  There may be up to
> -- 
> 2.17.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Manivannan Sadhasivam]

On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > This commit adds the boolean "brcm,enable-l1ss" property:
> > >
> > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > >   requires the driver probe() to deliberately place the HW one of three
> > >   CLKREQ# modes:
> > >
> > >   (a) CLKREQ# driven by the RC unconditionally
> > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > >
> > >   The HW+driver can tell the difference between downstream devices that
> > >   need (a) and (b), but does not know when to configure (c).  All devices
> > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > >   desired to realize the extra power savings that L1SS offers.  So we
> > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > >   that (c) is desired.  Setting this property only makes sense when the
> > >   downstream device is L1SS-capable and the OS is configured to activate
> > >   this mode (e.g. policy==powersupersave).
> > >
> > >   This property is already present in the Raspian version of Linux, but the
> > >   upstream driver implementation that follows adds more details and
> > >   discerns between (a) and (b).
> > >
> > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > ---
> > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > index 7e15aae7d69e..8b61c2179608 100644
> > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > @@ -64,6 +64,15 @@ properties:
> > >
> > >    aspm-no-l0s: true
> > >
> > > +  brcm,enable-l1ss:
> > > +    description: Indicates that PCIe L1SS power savings
> > > +      are desired, the downstream device is L1SS-capable, and the
> > > +      OS has been configured to enable this mode.  For boards
> > > +      using a mini-card connector, this mode may not meet the
> > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > +      of the PCI Express Mini CEM 2.0 specification.
> >
> > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > the hardware capability and not system/OS behavior.
> 
> The "brcm,enable-l1ss" does NOT configure the OS behavior.
> It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> configured for L1SS.
> It compensates for a problem in the PCIe core: the HW is not capable
> of dynamically
> switching between ASPM modes powersave and superpowersave.  I am actively
> advocating for our HW to change but that will take years.
> 

Okay, then I would say that the property name and commit message were a bit
misleading. 

I had briefly gone through the driver patch now. As per my understanding, you
have 2 modes in hw:

1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
the device (driving high) when the link is in L1.

2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.

Till now the driver only supported Clock PM through mode (1) but for supporting
L1SS you need to enable mode (2). And you are using this property to select mode
(2) when the L1SS supported devices are connected to the slot. Also, by
selecting this mode, you are loosing the benefit of mode (1) as both are not
compatible.

My suggestion would be to just drop mode (1) and use mode (2) in the driver as
most of the recent devices should support L1SS (ofc there are exemptions).

But moving that decision to DT still doesn't seem right to me as the hardware
supports both modes and you are (ab)using DT to choose one or the other.

- Mani

> If this flag specifies
> > whether the PCIe controller supports L1SS or not, then it is fine but apparantly
> > this specifies that all downstream devices are L1SS capable which you cannot
> > guarantee unless you poke into their LNKCAP during runtime.
> Not true at all.  This setting affects only RC and whatever device is
> connected to its single downstream
> port.
> 
> >
> > You should handle this in the driver itself.
> 
> The driver has no way of knowing if the PCI subsystem is going from power_save
> to power_supersave or vice-versa -- there is no notification chain for this.  So
> what you say is not currently possible from the driver's perspective.
> 
> Perhaps you would be happy if we changed it to "l1ss-support" in the
> spirit of the
> existing "clkreq-support" PCI parameter?
> 
> Regards,
> Jim Quinlan
> Broadcom STB/CMi
> 
> >
> > - Mani
> >
> > > +    type: boolean
> > > +
> > >    brcm,scb-sizes:
> > >      description: u64 giving the 64bit PCIe memory
> > >        viewport size of a memory controller.  There may be up to
> > > --
> > > 2.17.1
> > >
> >
> > --
> > மணிவண்ணன் சதாசிவம்

> Date: Tue, 22 Aug 2023 21:01:47 +0000 (UTC)
> From: Florian Fainelli <messenger@webex.com>
> To: james.quinlan@broadcom.com
> Subject: Join me now in my Personal Room
> 
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> Join me now in my Personal Room. 
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Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Lorenzo Pieralisi]

On Wed, Aug 23, 2023 at 11:46:50PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> > On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > >
> > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > >   requires the driver probe() to deliberately place the HW one of three
> > > >   CLKREQ# modes:
> > > >
> > > >   (a) CLKREQ# driven by the RC unconditionally
> > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > >
> > > >   The HW+driver can tell the difference between downstream devices that
> > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > >   that (c) is desired.  Setting this property only makes sense when the
> > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > >   this mode (e.g. policy==powersupersave).
> > > >
> > > >   This property is already present in the Raspian version of Linux, but the
> > > >   upstream driver implementation that follows adds more details and
> > > >   discerns between (a) and (b).
> > > >
> > > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > ---
> > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > >  1 file changed, 9 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > @@ -64,6 +64,15 @@ properties:
> > > >
> > > >    aspm-no-l0s: true
> > > >
> > > > +  brcm,enable-l1ss:
> > > > +    description: Indicates that PCIe L1SS power savings
> > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > +      OS has been configured to enable this mode.  For boards
> > > > +      using a mini-card connector, this mode may not meet the
> > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > +      of the PCI Express Mini CEM 2.0 specification.
> > >
> > > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > > the hardware capability and not system/OS behavior.
> > 
> > The "brcm,enable-l1ss" does NOT configure the OS behavior.
> > It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> > configured for L1SS.
> > It compensates for a problem in the PCIe core: the HW is not capable
> > of dynamically
> > switching between ASPM modes powersave and superpowersave.  I am actively
> > advocating for our HW to change but that will take years.
> > 
> 
> Okay, then I would say that the property name and commit message were a bit
> misleading. 
> 
> I had briefly gone through the driver patch now. As per my understanding, you
> have 2 modes in hw:
> 
> 1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
> the device (driving high) when the link is in L1.
> 
> 2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.
> 
> Till now the driver only supported Clock PM through mode (1) but for supporting
> L1SS you need to enable mode (2). And you are using this property to select mode
> (2) when the L1SS supported devices are connected to the slot. Also, by
> selecting this mode, you are loosing the benefit of mode (1) as both are not
> compatible.
> 
> My suggestion would be to just drop mode (1) and use mode (2) in the driver as
> most of the recent devices should support L1SS (ofc there are exemptions).
> 
> But moving that decision to DT still doesn't seem right to me as the hardware
> supports both modes and you are (ab)using DT to choose one or the other.

Jim ? We need to queue this series as soon as possible, if we don't
reach consensus by this evening I will queue the last three patches
only.

Lorenzo

> - Mani
> 
> > If this flag specifies
> > > whether the PCIe controller supports L1SS or not, then it is fine but apparantly
> > > this specifies that all downstream devices are L1SS capable which you cannot
> > > guarantee unless you poke into their LNKCAP during runtime.
> > Not true at all.  This setting affects only RC and whatever device is
> > connected to its single downstream
> > port.
> > 
> > >
> > > You should handle this in the driver itself.
> > 
> > The driver has no way of knowing if the PCI subsystem is going from power_save
> > to power_supersave or vice-versa -- there is no notification chain for this.  So
> > what you say is not currently possible from the driver's perspective.
> > 
> > Perhaps you would be happy if we changed it to "l1ss-support" in the
> > spirit of the
> > existing "clkreq-support" PCI parameter?
> > 
> > Regards,
> > Jim Quinlan
> > Broadcom STB/CMi
> > 
> > >
> > > - Mani
> > >
> > > > +    type: boolean
> > > > +
> > > >    brcm,scb-sizes:
> > > >      description: u64 giving the 64bit PCIe memory
> > > >        viewport size of a memory controller.  There may be up to
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
> 
> > Date: Tue, 22 Aug 2023 21:01:47 +0000 (UTC)
> > From: Florian Fainelli <messenger@webex.com>
> > To: james.quinlan@broadcom.com
> > Subject: Join me now in my Personal Room
> > 
> > Hello,
> > 
> > Join me now in my Personal Room. 
> > 
> > JOIN WEBEX MEETING
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> > 
> > 
> > JOIN FROM A VIDEO CONFERENCING SYSTEM OR APPLICATION
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> > You can also dial 173.243.2.68 and enter your meeting number.
> > 
> > 
> > 
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> >         - Use Call Me when you are using office phone or Jabber.
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> > 
> > In Office Calls:
> > 	- From Broadcom Office: 1-MEETING (1-6338464)
> > 
> > Offsite Numbers Toll (Local) Calls:
> > 	- Canada, Richmond: +1-778-308-4007
> > 	- China: +86-400-819-1044
> > 	- Germany, Munich: +49-892-312-9611
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> >         - India: 00-080-0050-1631
> > 	- Israel: +97-239-786-477
> >         - Japan, Tokyo: +81-366-344-937
> >         - Malaysia: +603-2053-5189
> > 	- Singapore: +65-6349-2439
> > 	- South Korea, Seoul: +82-70-4732-0218
> > 	- Taiwan, Taipei: +886-277-047-765
> > 	- US, Denver: +1-720-726-9995
> >         - US, Los Angeles: +1-310-616-5312
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Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Jim Quinlan]

[-- Attachment #1: Type: text/plain, Size: 8694 bytes --]

On Wed, Aug 23, 2023 at 2:17 PM Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> > On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > >
> > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > >   requires the driver probe() to deliberately place the HW one of three
> > > >   CLKREQ# modes:
> > > >
> > > >   (a) CLKREQ# driven by the RC unconditionally
> > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > >
> > > >   The HW+driver can tell the difference between downstream devices that
> > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > >   that (c) is desired.  Setting this property only makes sense when the
> > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > >   this mode (e.g. policy==powersupersave).
> > > >
> > > >   This property is already present in the Raspian version of Linux, but the
> > > >   upstream driver implementation that follows adds more details and
> > > >   discerns between (a) and (b).
> > > >
> > > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > ---
> > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > >  1 file changed, 9 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > @@ -64,6 +64,15 @@ properties:
> > > >
> > > >    aspm-no-l0s: true
> > > >
> > > > +  brcm,enable-l1ss:
> > > > +    description: Indicates that PCIe L1SS power savings
> > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > +      OS has been configured to enable this mode.  For boards
> > > > +      using a mini-card connector, this mode may not meet the
> > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > +      of the PCI Express Mini CEM 2.0 specification.
> > >
> > > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > > the hardware capability and not system/OS behavior.
> >
> > The "brcm,enable-l1ss" does NOT configure the OS behavior.
> > It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> > configured for L1SS.
> > It compensates for a problem in the PCIe core: the HW is not capable
> > of dynamically
> > switching between ASPM modes powersave and superpowersave.  I am actively
> > advocating for our HW to change but that will take years.
> >
>
> Okay, then I would say that the property name and commit message were a bit
> misleading.
>
> I had briefly gone through the driver patch now. As per my understanding, you
> have 2 modes in hw:
>
> 1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
> the device (driving high) when the link is in L1.
>
> 2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.

No, there are three, as enumerated in the commit message of
"PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device"

>
> Till now the driver only supported Clock PM through mode (1) but for supporting
> L1SS you need to enable mode (2). And you are using this property to select mode
> (2) when the L1SS supported devices are connected to the slot. Also, by
> selecting this mode, you are loosing the benefit of mode (1) as both are not
> compatible.
>
> My suggestion would be to just drop mode (1) and use mode (2) in the driver as
> most of the recent devices should support L1SS (ofc there are exemptions).
The disadvantage of this, as stated by the PCIe core HW designer, was
that "doing so means
we cannot enable the Cock Power Management capability since it may run afoul of
the Tclron requirement."

I will attempt to press him on exactly what configurations and form
factors would be
vulnerable to this -- he was so convinced that it was a danger that he
is against
making L1SS mode the default.

>
> But moving that decision to DT still doesn't seem right to me as the hardware
> supports both modes and you are (ab)using DT to choose one or the other.

May be true, but there does not appear to be a Linux upstream-acceptable
way of doing this on the command line either; please see my recent post
on why this is so.

There will be cases where we want to override the default setting, either by
command line or DT, but you folks have to give me a viable path on
how to do this with it actually being accepted.

Regards,
Jim Quinlan
Broadcom STB/CM

>
> - Mani
>
> > If this flag specifies
> > > whether the PCIe controller supports L1SS or not, then it is fine but apparantly
> > > this specifies that all downstream devices are L1SS capable which you cannot
> > > guarantee unless you poke into their LNKCAP during runtime.
> > Not true at all.  This setting affects only RC and whatever device is
> > connected to its single downstream
> > port.
> >
> > >
> > > You should handle this in the driver itself.
> >
> > The driver has no way of knowing if the PCI subsystem is going from power_save
> > to power_supersave or vice-versa -- there is no notification chain for this.  So
> > what you say is not currently possible from the driver's perspective.
> >
> > Perhaps you would be happy if we changed it to "l1ss-support" in the
> > spirit of the
> > existing "clkreq-support" PCI parameter?
> >
> > Regards,
> > Jim Quinlan
> > Broadcom STB/CMi
> >
> > >
> > > - Mani
> > >
> > > > +    type: boolean
> > > > +
> > > >    brcm,scb-sizes:
> > > >      description: u64 giving the 64bit PCIe memory
> > > >        viewport size of a memory controller.  There may be up to
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
>
> > Date: Tue, 22 Aug 2023 21:01:47 +0000 (UTC)
> > From: Florian Fainelli <messenger@webex.com>
> > To: james.quinlan@broadcom.com
> > Subject: Join me now in my Personal Room
> >
> > Hello,
> >
> > Join me now in my Personal Room.
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[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4210 bytes --]

Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Manivannan Sadhasivam]

On Thu, Aug 24, 2023 at 10:55:02AM -0400, Jim Quinlan wrote:
> On Wed, Aug 23, 2023 at 2:17 PM Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> > > On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > >
> > > > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > >
> > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > >   CLKREQ# modes:
> > > > >
> > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > >
> > > > >   The HW+driver can tell the difference between downstream devices that
> > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > >   this mode (e.g. policy==powersupersave).
> > > > >
> > > > >   This property is already present in the Raspian version of Linux, but the
> > > > >   upstream driver implementation that follows adds more details and
> > > > >   discerns between (a) and (b).
> > > > >
> > > > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > ---
> > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > >  1 file changed, 9 insertions(+)
> > > > >
> > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > @@ -64,6 +64,15 @@ properties:
> > > > >
> > > > >    aspm-no-l0s: true
> > > > >
> > > > > +  brcm,enable-l1ss:
> > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > +      OS has been configured to enable this mode.  For boards
> > > > > +      using a mini-card connector, this mode may not meet the
> > > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > > +      of the PCI Express Mini CEM 2.0 specification.
> > > >
> > > > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > > > the hardware capability and not system/OS behavior.
> > >
> > > The "brcm,enable-l1ss" does NOT configure the OS behavior.
> > > It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> > > configured for L1SS.
> > > It compensates for a problem in the PCIe core: the HW is not capable
> > > of dynamically
> > > switching between ASPM modes powersave and superpowersave.  I am actively
> > > advocating for our HW to change but that will take years.
> > >
> >
> > Okay, then I would say that the property name and commit message were a bit
> > misleading.
> >
> > I had briefly gone through the driver patch now. As per my understanding, you
> > have 2 modes in hw:
> >
> > 1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
> > the device (driving high) when the link is in L1.
> >
> > 2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.
> 
> No, there are three, as enumerated in the commit message of
> "PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device"
> 

Yeah, another one is refclk always on.

> >
> > Till now the driver only supported Clock PM through mode (1) but for supporting
> > L1SS you need to enable mode (2). And you are using this property to select mode
> > (2) when the L1SS supported devices are connected to the slot. Also, by
> > selecting this mode, you are loosing the benefit of mode (1) as both are not
> > compatible.
> >
> > My suggestion would be to just drop mode (1) and use mode (2) in the driver as
> > most of the recent devices should support L1SS (ofc there are exemptions).
> The disadvantage of this, as stated by the PCIe core HW designer, was
> that "doing so means
> we cannot enable the Cock Power Management capability since it may run afoul of
> the Tclron requirement."
> 

Ok.

> I will attempt to press him on exactly what configurations and form
> factors would be
> vulnerable to this -- he was so convinced that it was a danger that he
> is against
> making L1SS mode the default.
> 

Hmm. After looking at this problem in detail, it looks to me that you can still
use DT but not with the property you proposed. Since these are hardware modes,
you can have a single DT property that specifies the mode that the driver can
use to configure the hw. It is similar to "phy-mode" property we have for the
network controllers.

So you should have the property defined as below in binding:

brcm,clkreq-mode:
  $ref: /schemas/types.yaml#/definitions/uint32
  enum: [ 0, 1, 2 ]

Then create definition for each mode in "include/dt-bindings/pci/brcm,stb.h".

#define BRCM_STB_CLKREQ_CLOCK_PM	0
#define BRCM_STB_CLKREQ_L1SS		1
#define BRCM_STB_CLKREQ_ON		2

If the property is not specified, the driver should use "Clock PM" as the
default mode as it was doing earlier.

Also, I think you can get rid of other checks in the driver (like PCIEASPM
Kconfig, clkreq_seen etc...) and solely rely on this property to set the mode.

What do you think?

- Mani

> >
> > But moving that decision to DT still doesn't seem right to me as the hardware
> > supports both modes and you are (ab)using DT to choose one or the other.
> 
> May be true, but there does not appear to be a Linux upstream-acceptable
> way of doing this on the command line either; please see my recent post
> on why this is so.
> 
> There will be cases where we want to override the default setting, either by
> command line or DT, but you folks have to give me a viable path on
> how to do this with it actually being accepted.
> 
> Regards,
> Jim Quinlan
> Broadcom STB/CM
> 
> >
> > - Mani
> >
> > > If this flag specifies
> > > > whether the PCIe controller supports L1SS or not, then it is fine but apparantly
> > > > this specifies that all downstream devices are L1SS capable which you cannot
> > > > guarantee unless you poke into their LNKCAP during runtime.
> > > Not true at all.  This setting affects only RC and whatever device is
> > > connected to its single downstream
> > > port.
> > >
> > > >
> > > > You should handle this in the driver itself.
> > >
> > > The driver has no way of knowing if the PCI subsystem is going from power_save
> > > to power_supersave or vice-versa -- there is no notification chain for this.  So
> > > what you say is not currently possible from the driver's perspective.
> > >
> > > Perhaps you would be happy if we changed it to "l1ss-support" in the
> > > spirit of the
> > > existing "clkreq-support" PCI parameter?
> > >
> > > Regards,
> > > Jim Quinlan
> > > Broadcom STB/CMi
> > >
> > > >
> > > > - Mani
> > > >
> > > > > +    type: boolean
> > > > > +
> > > > >    brcm,scb-sizes:
> > > > >      description: u64 giving the 64bit PCIe memory
> > > > >        viewport size of a memory controller.  There may be up to
> > > > > --
> > > > > 2.17.1
> > > > >
> > > >
> > > > --
> > > > மணிவண்ணன் சதாசிவம்
> >
> > > Date: Tue, 22 Aug 2023 21:01:47 +0000 (UTC)
> > > From: Florian Fainelli <messenger@webex.com>
> > > To: james.quinlan@broadcom.com
> > > Subject: Join me now in my Personal Room
> > >
> > > Hello,
> > >
> > > Join me now in my Personal Room.
> > >
> > > JOIN WEBEX MEETING
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> > >
> > > JOIN FROM A VIDEO CONFERENCING SYSTEM OR APPLICATION
> > > Dial sip:florian.fainelli@broadcom.webex.com
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> > >
> > >
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> > >
> > > Offsite Numbers Toll (Local) Calls:
> > >       - Canada, Richmond: +1-778-308-4007
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> > >       - Germany, Munich: +49-892-312-9611
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> > >         - Malaysia: +603-2053-5189
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> > மணிவண்ணன் சதாசிவம்



-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Jim Quinlan]

[-- Attachment #1: Type: text/plain, Size: 8919 bytes --]

On Fri, Aug 25, 2023 at 2:45 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Thu, Aug 24, 2023 at 10:55:02AM -0400, Jim Quinlan wrote:
> > On Wed, Aug 23, 2023 at 2:17 PM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> > > > On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > >
> > > > > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > >
> > > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > > >   CLKREQ# modes:
> > > > > >
> > > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > >
> > > > > >   The HW+driver can tell the difference between downstream devices that
> > > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > > >   this mode (e.g. policy==powersupersave).
> > > > > >
> > > > > >   This property is already present in the Raspian version of Linux, but the
> > > > > >   upstream driver implementation that follows adds more details and
> > > > > >   discerns between (a) and (b).
> > > > > >
> > > > > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > > ---
> > > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > >  1 file changed, 9 insertions(+)
> > > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > >
> > > > > >    aspm-no-l0s: true
> > > > > >
> > > > > > +  brcm,enable-l1ss:
> > > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > > +      OS has been configured to enable this mode.  For boards
> > > > > > +      using a mini-card connector, this mode may not meet the
> > > > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > > > +      of the PCI Express Mini CEM 2.0 specification.
> > > > >
> > > > > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > > > > the hardware capability and not system/OS behavior.
> > > >
> > > > The "brcm,enable-l1ss" does NOT configure the OS behavior.
> > > > It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> > > > configured for L1SS.
> > > > It compensates for a problem in the PCIe core: the HW is not capable
> > > > of dynamically
> > > > switching between ASPM modes powersave and superpowersave.  I am actively
> > > > advocating for our HW to change but that will take years.
> > > >
> > >
> > > Okay, then I would say that the property name and commit message were a bit
> > > misleading.
> > >
> > > I had briefly gone through the driver patch now. As per my understanding, you
> > > have 2 modes in hw:
> > >
> > > 1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
> > > the device (driving high) when the link is in L1.
> > >
> > > 2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.
> >
> > No, there are three, as enumerated in the commit message of
> > "PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device"
> >
>
> Yeah, another one is refclk always on.
>
> > >
> > > Till now the driver only supported Clock PM through mode (1) but for supporting
> > > L1SS you need to enable mode (2). And you are using this property to select mode
> > > (2) when the L1SS supported devices are connected to the slot. Also, by
> > > selecting this mode, you are loosing the benefit of mode (1) as both are not
> > > compatible.
> > >
> > > My suggestion would be to just drop mode (1) and use mode (2) in the driver as
> > > most of the recent devices should support L1SS (ofc there are exemptions).
> > The disadvantage of this, as stated by the PCIe core HW designer, was
> > that "doing so means
> > we cannot enable the Cock Power Management capability since it may run afoul of
> > the Tclron requirement."
> >
>
> Ok.
>
> > I will attempt to press him on exactly what configurations and form
> > factors would be
> > vulnerable to this -- he was so convinced that it was a danger that he
> > is against
> > making L1SS mode the default.
> >
>
> Hmm. After looking at this problem in detail, it looks to me that you can still
> use DT but not with the property you proposed. Since these are hardware modes,
> you can have a single DT property that specifies the mode that the driver can
> use to configure the hw. It is similar to "phy-mode" property we have for the
> network controllers.
>
> So you should have the property defined as below in binding:
>
> brcm,clkreq-mode:
>   $ref: /schemas/types.yaml#/definitions/uint32
>   enum: [ 0, 1, 2 ]
>
> Then create definition for each mode in "include/dt-bindings/pci/brcm,stb.h".
>
> #define BRCM_STB_CLKREQ_CLOCK_PM        0
> #define BRCM_STB_CLKREQ_L1SS            1
> #define BRCM_STB_CLKREQ_ON              2
>
> If the property is not specified, the driver should use "Clock PM" as the
> default mode as it was doing earlier.
>
> Also, I think you can get rid of other checks in the driver (like PCIEASPM
> Kconfig, clkreq_seen etc...) and solely rely on this property to set the mode.
>
> What do you think?

Hi Mani,

I'm all for it; in fact this is quite similar to  my original design.
But then I decided to be backwards
compatible with RaspianOS's "brcm,enable-l1ss".

I will go in this direction for V7 and the only remaining issue is
what the default mode should
be and I will try my best to get time with the HW designer to weigh
the pros and cons.

Regards,
Jim Quinlan
Broadcom STB/CM

>
>
> - Mani
>
> > >
> > > But moving that decision to DT still doesn't seem right to me as the hardware
> > > supports both modes and you are (ab)using DT to choose one or the other.
> >
> > May be true, but there does not appear to be a Linux upstream-acceptable
> > way of doing this on the command line either; please see my recent post
> > on why this is so.
> >
> > There will be cases where we want to override the default setting, either by
> > command line or DT, but you folks have to give me a viable path on
> > how to do this with it actually being accepted.
> >
> > Regards,
> > Jim Quinlan
> > Broadcom STB/CM
> >
> > >
> > > - Mani
> > >
> > > > If this flag specifies
> > > > > whether the PCIe controller supports L1SS or not, then it is fine but apparantly
> > > > > this specifies that all downstream devices are L1SS capable which you cannot
> > > > > guarantee unless you poke into their LNKCAP during runtime.
> > > > Not true at all.  This setting affects only RC and whatever device is
> > > > connected to its single downstream
> > > > port.
> > > >
> > > > >
> > > > > You should handle this in the driver itself.
> > > >
> > > > The driver has no way of knowing if the PCI subsystem is going from power_save
> > > > to power_supersave or vice-versa -- there is no notification chain for this.  So
> > > > what you say is not currently possible from the driver's perspective.
> > > >
> > > > Perhaps you would be happy if we changed it to "l1ss-support" in the
> > > > spirit of the
> > > > existing "clkreq-support" PCI parameter?
> > > >
> > > > Regards,
> > > > Jim Quinlan
> > > > Broadcom STB/CMi
> > > >
> > > > >
> > > > > - Mani
> > > > >
> > > > > > +    type: boolean
> > > > > > +
> > > > > >    brcm,scb-sizes:
> > > > > >      description: u64 giving the 64bit PCIe memory
> > > > > >        viewport size of a memory controller.  There may be up to
> > > > > > --
> > > > > > 2.17.1
> > > > > >
> > > > >
> > > > > --
> > > > > மணிவண்ணன் சதாசிவம்
> > >
>

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Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Rob Herring]

On Fri, Aug 25, 2023 at 1:45 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Thu, Aug 24, 2023 at 10:55:02AM -0400, Jim Quinlan wrote:
> > On Wed, Aug 23, 2023 at 2:17 PM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> > > > On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > >
> > > > > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > >
> > > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > > >   CLKREQ# modes:
> > > > > >
> > > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > >
> > > > > >   The HW+driver can tell the difference between downstream devices that
> > > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > > >   this mode (e.g. policy==powersupersave).
> > > > > >
> > > > > >   This property is already present in the Raspian version of Linux, but the
> > > > > >   upstream driver implementation that follows adds more details and
> > > > > >   discerns between (a) and (b).
> > > > > >
> > > > > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > > ---
> > > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > >  1 file changed, 9 insertions(+)
> > > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > >
> > > > > >    aspm-no-l0s: true
> > > > > >
> > > > > > +  brcm,enable-l1ss:
> > > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > > +      OS has been configured to enable this mode.  For boards
> > > > > > +      using a mini-card connector, this mode may not meet the
> > > > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > > > +      of the PCI Express Mini CEM 2.0 specification.
> > > > >
> > > > > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > > > > the hardware capability and not system/OS behavior.
> > > >
> > > > The "brcm,enable-l1ss" does NOT configure the OS behavior.
> > > > It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> > > > configured for L1SS.
> > > > It compensates for a problem in the PCIe core: the HW is not capable
> > > > of dynamically
> > > > switching between ASPM modes powersave and superpowersave.  I am actively
> > > > advocating for our HW to change but that will take years.
> > > >
> > >
> > > Okay, then I would say that the property name and commit message were a bit
> > > misleading.
> > >
> > > I had briefly gone through the driver patch now. As per my understanding, you
> > > have 2 modes in hw:
> > >
> > > 1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
> > > the device (driving high) when the link is in L1.
> > >
> > > 2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.
> >
> > No, there are three, as enumerated in the commit message of
> > "PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device"
> >
>
> Yeah, another one is refclk always on.
>
> > >
> > > Till now the driver only supported Clock PM through mode (1) but for supporting
> > > L1SS you need to enable mode (2). And you are using this property to select mode
> > > (2) when the L1SS supported devices are connected to the slot. Also, by
> > > selecting this mode, you are loosing the benefit of mode (1) as both are not
> > > compatible.
> > >
> > > My suggestion would be to just drop mode (1) and use mode (2) in the driver as
> > > most of the recent devices should support L1SS (ofc there are exemptions).
> > The disadvantage of this, as stated by the PCIe core HW designer, was
> > that "doing so means
> > we cannot enable the Cock Power Management capability since it may run afoul of
> > the Tclron requirement."
> >
>
> Ok.
>
> > I will attempt to press him on exactly what configurations and form
> > factors would be
> > vulnerable to this -- he was so convinced that it was a danger that he
> > is against
> > making L1SS mode the default.
> >
>
> Hmm. After looking at this problem in detail, it looks to me that you can still
> use DT but not with the property you proposed. Since these are hardware modes,
> you can have a single DT property that specifies the mode that the driver can
> use to configure the hw. It is similar to "phy-mode" property we have for the
> network controllers.
>
> So you should have the property defined as below in binding:
>
> brcm,clkreq-mode:
>   $ref: /schemas/types.yaml#/definitions/uint32
>   enum: [ 0, 1, 2 ]

Is this really Broadcom specific?

Rob

Re: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property

[Manivannan Sadhasivam]

On Tue, Aug 29, 2023 at 07:22:18AM -0500, Rob Herring wrote:
> On Fri, Aug 25, 2023 at 1:45 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Thu, Aug 24, 2023 at 10:55:02AM -0400, Jim Quinlan wrote:
> > > On Wed, Aug 23, 2023 at 2:17 PM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > >
> > > > On Wed, Aug 23, 2023 at 09:09:25AM -0400, Jim Quinlan wrote:
> > > > > On Wed, Aug 23, 2023 at 3:43 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > >
> > > > > > On Mon, May 08, 2023 at 06:01:21PM -0400, Jim Quinlan wrote:
> > > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > > >
> > > > > > >   The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > > >   requires the driver probe() to deliberately place the HW one of three
> > > > > > >   CLKREQ# modes:
> > > > > > >
> > > > > > >   (a) CLKREQ# driven by the RC unconditionally
> > > > > > >   (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > > >   (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > > >
> > > > > > >   The HW+driver can tell the difference between downstream devices that
> > > > > > >   need (a) and (b), but does not know when to configure (c).  All devices
> > > > > > >   should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > > >   desired to realize the extra power savings that L1SS offers.  So we
> > > > > > >   introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > > >   that (c) is desired.  Setting this property only makes sense when the
> > > > > > >   downstream device is L1SS-capable and the OS is configured to activate
> > > > > > >   this mode (e.g. policy==powersupersave).
> > > > > > >
> > > > > > >   This property is already present in the Raspian version of Linux, but the
> > > > > > >   upstream driver implementation that follows adds more details and
> > > > > > >   discerns between (a) and (b).
> > > > > > >
> > > > > > > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > > > > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > > > > ---
> > > > > > >  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > > >  1 file changed, 9 insertions(+)
> > > > > > >
> > > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > > >
> > > > > > >    aspm-no-l0s: true
> > > > > > >
> > > > > > > +  brcm,enable-l1ss:
> > > > > > > +    description: Indicates that PCIe L1SS power savings
> > > > > > > +      are desired, the downstream device is L1SS-capable, and the
> > > > > > > +      OS has been configured to enable this mode.  For boards
> > > > > > > +      using a mini-card connector, this mode may not meet the
> > > > > > > +      TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > > > > > +      of the PCI Express Mini CEM 2.0 specification.
> > > > > >
> > > > > > As Lorenzo said, this property doesn't belong in DT. DT is supposed to specify
> > > > > > the hardware capability and not system/OS behavior.
> > > > >
> > > > > The "brcm,enable-l1ss" does NOT configure the OS behavior.
> > > > > It sets or not a mode bit to enable l1SS HW, whether or not the OS is
> > > > > configured for L1SS.
> > > > > It compensates for a problem in the PCIe core: the HW is not capable
> > > > > of dynamically
> > > > > switching between ASPM modes powersave and superpowersave.  I am actively
> > > > > advocating for our HW to change but that will take years.
> > > > >
> > > >
> > > > Okay, then I would say that the property name and commit message were a bit
> > > > misleading.
> > > >
> > > > I had briefly gone through the driver patch now. As per my understanding, you
> > > > have 2 modes in hw:
> > > >
> > > > 1. Clock PM - Refclk will be turned off by the host if CLKREQ# is deasserted by
> > > > the device (driving high) when the link is in L1.
> > > >
> > > > 2. L1SS - CLKREQ# will be used to decide L1SS entry and exit by the host.
> > >
> > > No, there are three, as enumerated in the commit message of
> > > "PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device"
> > >
> >
> > Yeah, another one is refclk always on.
> >
> > > >
> > > > Till now the driver only supported Clock PM through mode (1) but for supporting
> > > > L1SS you need to enable mode (2). And you are using this property to select mode
> > > > (2) when the L1SS supported devices are connected to the slot. Also, by
> > > > selecting this mode, you are loosing the benefit of mode (1) as both are not
> > > > compatible.
> > > >
> > > > My suggestion would be to just drop mode (1) and use mode (2) in the driver as
> > > > most of the recent devices should support L1SS (ofc there are exemptions).
> > > The disadvantage of this, as stated by the PCIe core HW designer, was
> > > that "doing so means
> > > we cannot enable the Cock Power Management capability since it may run afoul of
> > > the Tclron requirement."
> > >
> >
> > Ok.
> >
> > > I will attempt to press him on exactly what configurations and form
> > > factors would be
> > > vulnerable to this -- he was so convinced that it was a danger that he
> > > is against
> > > making L1SS mode the default.
> > >
> >
> > Hmm. After looking at this problem in detail, it looks to me that you can still
> > use DT but not with the property you proposed. Since these are hardware modes,
> > you can have a single DT property that specifies the mode that the driver can
> > use to configure the hw. It is similar to "phy-mode" property we have for the
> > network controllers.
> >
> > So you should have the property defined as below in binding:
> >
> > brcm,clkreq-mode:
> >   $ref: /schemas/types.yaml#/definitions/uint32
> >   enum: [ 0, 1, 2 ]
> 
> Is this really Broadcom specific?
> 

AFAIU, rest of the controllers do not have issues supporting Clock PM and L1SS
in hw. Neither does the spec define any incompatibility. So to me, this looks
like Broadcom specific.

- Mani

> Rob

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v5 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[Cyril Brulebois]

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Hi Jim,

Jim Quinlan <jim2101024@gmail.com> (2023-05-08):
> v5 -- Remove DT property "brcm,completion-timeout-us" from	 
>       "DT bindings" commit.  Although this error may be reported	 
>       as a completion timeout, its cause was traced to an	 
>       internal bus timeout which may occur even when there is	 
>       no PCIe access being processed.  We set a timeout of four	 
>       seconds only if we are operating in "L1SS CLKREQ#" mode.
>    -- Correct CEM 2.0 reference provided by HW engineer,
>       s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
>    -- Add newline to dev_info() string (Stefan)
>    -- Change variable rval to unsigned (Stefan)
>    -- s/implementaion/implementation/ (Bjorn)
>    -- s/superpowersave/powersupersave/ (Bjorn)
>    -- Slightly modify message on "PERST#" commit.
>    -- Rebase to torvalds master

Same results as with v4: looks good to me!

Using an official CM4 IO Board, I've successfully tested the same 9
setups as before, combining each:
 - CM4 Lite Rev 1.0
 - CM4 8/32 Rev 1.0
 - CM4 4/32 Rev 1.1

with each off-the-shelf PCIe/USB adapter at my disposal:
 - SupaHub PCE6U1C-R02, VER 006
 - SupaHub PCE6U1C-R02, VER 006S
 - Waveshare based on VIA VL805/806

Each system boots successfully, exposes the Kingston memory stick
plugged onto the PCIe/USB adapter, and happily reads data from it.

Note: I only tested each CM4 with the upgraded EEPROM (2023-01-11),
and without tweaking the DTB (i.e. without adding brcm,enable-l1ss).


Tested-By: Cyril Brulebois <cyril@debamax.com>


Cheers,
-- 
Cyril Brulebois (kibi@debian.org)            <https://debamax.com/>
D-I release manager -- Release team member -- Freelance Consultant

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Re: [PATCH v5 0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

[Jim Quinlan]

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On Tue, May 9, 2023 at 3:47 AM Cyril Brulebois <kibi@debian.org> wrote:
>
> Hi Jim,
>
> Jim Quinlan <jim2101024@gmail.com> (2023-05-08):
> > v5 -- Remove DT property "brcm,completion-timeout-us" from
> >       "DT bindings" commit.  Although this error may be reported
> >       as a completion timeout, its cause was traced to an
> >       internal bus timeout which may occur even when there is
> >       no PCIe access being processed.  We set a timeout of four
> >       seconds only if we are operating in "L1SS CLKREQ#" mode.
> >    -- Correct CEM 2.0 reference provided by HW engineer,
> >       s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
> >    -- Add newline to dev_info() string (Stefan)
> >    -- Change variable rval to unsigned (Stefan)
> >    -- s/implementaion/implementation/ (Bjorn)
> >    -- s/superpowersave/powersupersave/ (Bjorn)
> >    -- Slightly modify message on "PERST#" commit.
> >    -- Rebase to torvalds master
>
> Same results as with v4: looks good to me!
>
> Using an official CM4 IO Board, I've successfully tested the same 9
> setups as before, combining each:
>  - CM4 Lite Rev 1.0
>  - CM4 8/32 Rev 1.0
>  - CM4 4/32 Rev 1.1
>
> with each off-the-shelf PCIe/USB adapter at my disposal:
>  - SupaHub PCE6U1C-R02, VER 006
>  - SupaHub PCE6U1C-R02, VER 006S
>  - Waveshare based on VIA VL805/806
>
> Each system boots successfully, exposes the Kingston memory stick
> plugged onto the PCIe/USB adapter, and happily reads data from it.
>
> Note: I only tested each CM4 with the upgraded EEPROM (2023-01-11),
> and without tweaking the DTB (i.e. without adding brcm,enable-l1ss).
>
>
> Tested-By: Cyril Brulebois <cyril@debamax.com>

Thanks a lot for doing this Cyril!
>
>
> Cheers,
> --
> Cyril Brulebois (kibi@debian.org)            <https://debamax.com/>
> D-I release manager -- Release team member -- Freelance Consultant

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