* [PATCH 0/3] arm: dts: imx93: add edmav3 support
@ 2023-08-23 18:00 Frank Li
2023-08-23 18:00 ` [PATCH 1/3] arm64: dts: imx93: add edma1 and edma2 Frank Li
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Frank Li @ 2023-08-23 18:00 UTC (permalink / raw)
To: frank.li
Cc: clin, conor+dt, devicetree, eagle.zhou, festevam, imx, joy.zou,
kernel, krzysztof.kozlowski+dt, leoyang.li, linux-arm-kernel,
linux-imx, linux-kernel, pierre.gondois, robh+dt, s.hauer,
shawnguo, shenwei.wang, sherry.sun
edmav3 patch already accepted.
https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git/log/?h=next
Add dts part for imx93
Frank Li (3):
arm64: dts: imx93: add edma1 and edma2
arm64: dts: imx93: add dma support for lpuart[2..9]
arm64: dts: imx93-evk: add uart5
.../boot/dts/freescale/imx93-11x11-evk.dts | 15 ++
arch/arm64/boot/dts/freescale/imx93.dtsi | 130 ++++++++++++++++++
2 files changed, 145 insertions(+)
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/3] arm64: dts: imx93: add edma1 and edma2 2023-08-23 18:00 [PATCH 0/3] arm: dts: imx93: add edmav3 support Frank Li @ 2023-08-23 18:00 ` Frank Li 2023-09-25 0:33 ` Shawn Guo 2023-08-23 18:00 ` [PATCH 2/3] arm64: dts: imx93: add dma support for lpuart[2..9] Frank Li 2023-08-23 18:00 ` [PATCH 3/3] arm64: dts: imx93-evk: add uart5 Frank Li 2 siblings, 1 reply; 6+ messages in thread From: Frank Li @ 2023-08-23 18:00 UTC (permalink / raw) To: frank.li Cc: clin, conor+dt, devicetree, eagle.zhou, festevam, imx, joy.zou, kernel, krzysztof.kozlowski+dt, leoyang.li, linux-arm-kernel, linux-imx, linux-kernel, pierre.gondois, robh+dt, s.hauer, shawnguo, shenwei.wang, sherry.sun Add edma<n> nodes. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- arch/arm64/boot/dts/freescale/imx93.dtsi | 116 +++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 6f85a05ee7e1..acdca18673b7 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -185,6 +185,46 @@ aips1: bus@44000000 { #size-cells = <1>; ranges; + edma1: dma-controller@44000000{ + compatible = "fsl,imx93-edma3"; + reg = <0x44000000 0x200000>; + #dma-cells = <3>; + dma-channels = <31>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, // 1: CANFD1 + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, // 3: GPIO1 CH0 + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, // 4: GPIO1 CH1 + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, // 5: I3C1 TO Bus + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, // 6: I3C1 From Bus + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, // 7: LPI2C1 M TX + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, // 8: LPI2C1 S TX + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, // 9: LPI2C2 M RX + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400 + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2 + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3 + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; // 30: ADC1 + clocks = <&clk IMX93_CLK_EDMA1_GATE>; + clock-names = "dma"; + }; + anomix_ns_gpr: syscon@44210000 { compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; reg = <0x44210000 0x1000>; @@ -423,6 +463,82 @@ aips2: bus@42000000 { #size-cells = <1>; ranges; + edma2: dma-controller@42000000{ + compatible = "fsl,imx93-edma4"; + reg = <0x42000000 0x210000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <64>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_EDMA2_GATE>; + clock-names = "dma"; + fsl,edma-axi; + status = "okay"; + }; + wakeupmix_gpr: syscon@42420000 { compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; reg = <0x42420000 0x1000>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] arm64: dts: imx93: add edma1 and edma2 2023-08-23 18:00 ` [PATCH 1/3] arm64: dts: imx93: add edma1 and edma2 Frank Li @ 2023-09-25 0:33 ` Shawn Guo 0 siblings, 0 replies; 6+ messages in thread From: Shawn Guo @ 2023-09-25 0:33 UTC (permalink / raw) To: Frank Li Cc: clin, conor+dt, devicetree, eagle.zhou, festevam, imx, joy.zou, kernel, krzysztof.kozlowski+dt, leoyang.li, linux-arm-kernel, linux-imx, linux-kernel, pierre.gondois, robh+dt, s.hauer, shenwei.wang, sherry.sun On Wed, Aug 23, 2023 at 02:00:53PM -0400, Frank Li wrote: > Add edma<n> nodes. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx93.dtsi | 116 +++++++++++++++++++++++ > 1 file changed, 116 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi > index 6f85a05ee7e1..acdca18673b7 100644 > --- a/arch/arm64/boot/dts/freescale/imx93.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi > @@ -185,6 +185,46 @@ aips1: bus@44000000 { > #size-cells = <1>; > ranges; > > + edma1: dma-controller@44000000{ > + compatible = "fsl,imx93-edma3"; > + reg = <0x44000000 0x200000>; > + #dma-cells = <3>; > + dma-channels = <31>; > + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved > + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, // 1: CANFD1 > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, // 3: GPIO1 CH0 > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, // 4: GPIO1 CH1 > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, // 5: I3C1 TO Bus > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, // 6: I3C1 From Bus > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, // 7: LPI2C1 M TX > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, // 8: LPI2C1 S TX > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, // 9: LPI2C2 M RX > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX > + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1 > + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX > + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX > + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX > + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX > + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400 > + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX > + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2 > + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3 > + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2 > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3 > + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow > + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM > + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; // 30: ADC1 > + clocks = <&clk IMX93_CLK_EDMA1_GATE>; > + clock-names = "dma"; > + }; > + > anomix_ns_gpr: syscon@44210000 { > compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; > reg = <0x44210000 0x1000>; > @@ -423,6 +463,82 @@ aips2: bus@42000000 { > #size-cells = <1>; > ranges; > > + edma2: dma-controller@42000000{ > + compatible = "fsl,imx93-edma4"; > + reg = <0x42000000 0x210000>; > + #dma-cells = <3>; > + shared-interrupt; > + dma-channels = <64>; > + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX93_CLK_EDMA2_GATE>; > + clock-names = "dma"; > + fsl,edma-axi; I do not find this property in bindings doc. > + status = "okay"; Unnecessary 'status'. Shawn > + }; > + > wakeupmix_gpr: syscon@42420000 { > compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; > reg = <0x42420000 0x1000>; > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/3] arm64: dts: imx93: add dma support for lpuart[2..9] 2023-08-23 18:00 [PATCH 0/3] arm: dts: imx93: add edmav3 support Frank Li 2023-08-23 18:00 ` [PATCH 1/3] arm64: dts: imx93: add edma1 and edma2 Frank Li @ 2023-08-23 18:00 ` Frank Li 2023-08-23 18:12 ` Fabio Estevam 2023-08-23 18:00 ` [PATCH 3/3] arm64: dts: imx93-evk: add uart5 Frank Li 2 siblings, 1 reply; 6+ messages in thread From: Frank Li @ 2023-08-23 18:00 UTC (permalink / raw) To: frank.li Cc: clin, conor+dt, devicetree, eagle.zhou, festevam, imx, joy.zou, kernel, krzysztof.kozlowski+dt, leoyang.li, linux-arm-kernel, linux-imx, linux-kernel, pierre.gondois, robh+dt, s.hauer, shawnguo, shenwei.wang, sherry.sun Add dma support for lpuart[2..9]. The lpuart1 is debug console. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- arch/arm64/boot/dts/freescale/imx93.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index acdca18673b7..c731eca4b3b5 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -345,6 +345,8 @@ lpuart2: serial@44390000 { interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART2_GATE>; clock-names = "ipg"; + dmas = <&edma1 18 0 0>, <&edma1 19 0 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -666,6 +668,8 @@ lpuart3: serial@42570000 { interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART3_GATE>; clock-names = "ipg"; + dmas = <&edma2 17 0 0>, <&edma2 18 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -675,6 +679,8 @@ lpuart4: serial@42580000 { interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART4_GATE>; clock-names = "ipg"; + dmas = <&edma2 19 0 0>, <&edma2 20 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -684,6 +690,8 @@ lpuart5: serial@42590000 { interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART5_GATE>; clock-names = "ipg"; + dmas = <&edma2 21 0 0>, <&edma2 22 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -693,6 +701,8 @@ lpuart6: serial@425a0000 { interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART6_GATE>; clock-names = "ipg"; + dmas = <&edma2 23 0 0>, <&edma2 24 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -731,6 +741,8 @@ lpuart7: serial@42690000 { interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART7_GATE>; clock-names = "ipg"; + dmas = <&edma2 87 0 0>, <&edma2 88 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -740,6 +752,8 @@ lpuart8: serial@426a0000 { interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART8_GATE>; clock-names = "ipg"; + dmas = <&edma2 89 0 0>, <&edma2 90 0 1>; + dma-names = "tx","rx"; status = "disabled"; }; -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/3] arm64: dts: imx93: add dma support for lpuart[2..9] 2023-08-23 18:00 ` [PATCH 2/3] arm64: dts: imx93: add dma support for lpuart[2..9] Frank Li @ 2023-08-23 18:12 ` Fabio Estevam 0 siblings, 0 replies; 6+ messages in thread From: Fabio Estevam @ 2023-08-23 18:12 UTC (permalink / raw) To: Frank Li Cc: clin, conor+dt, devicetree, eagle.zhou, imx, joy.zou, kernel, krzysztof.kozlowski+dt, leoyang.li, linux-arm-kernel, linux-imx, linux-kernel, pierre.gondois, robh+dt, s.hauer, shawnguo, shenwei.wang, sherry.sun Hi Frank, On Wed, Aug 23, 2023 at 3:01 PM Frank Li <Frank.Li@nxp.com> wrote: > > Add dma support for lpuart[2..9]. The lpuart1 is debug console. LPUART1 is the debug console on a particular board, but nothing prevents someone to design an imx93 board that has another LPUART port as the debug console. I suggest enabling DMA for all ports. That's what we do with other i.MX devices. By the way, the fsl_lpuart driver disables DMA for the console: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/tty/serial/fsl_lpuart.c?h=v6.5-rc7#n1696 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/3] arm64: dts: imx93-evk: add uart5 2023-08-23 18:00 [PATCH 0/3] arm: dts: imx93: add edmav3 support Frank Li 2023-08-23 18:00 ` [PATCH 1/3] arm64: dts: imx93: add edma1 and edma2 Frank Li 2023-08-23 18:00 ` [PATCH 2/3] arm64: dts: imx93: add dma support for lpuart[2..9] Frank Li @ 2023-08-23 18:00 ` Frank Li 2 siblings, 0 replies; 6+ messages in thread From: Frank Li @ 2023-08-23 18:00 UTC (permalink / raw) To: frank.li Cc: clin, conor+dt, devicetree, eagle.zhou, festevam, imx, joy.zou, kernel, krzysztof.kozlowski+dt, leoyang.li, linux-arm-kernel, linux-imx, linux-kernel, pierre.gondois, robh+dt, s.hauer, shawnguo, shenwei.wang, sherry.sun Enable uart5 for imx93-evk board. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index cafd39130eb8..2b9d47716f75 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -149,6 +149,12 @@ &lpuart1 { /* console */ status = "okay"; }; +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -222,6 +228,15 @@ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e >; }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-09-25 0:33 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-08-23 18:00 [PATCH 0/3] arm: dts: imx93: add edmav3 support Frank Li 2023-08-23 18:00 ` [PATCH 1/3] arm64: dts: imx93: add edma1 and edma2 Frank Li 2023-09-25 0:33 ` Shawn Guo 2023-08-23 18:00 ` [PATCH 2/3] arm64: dts: imx93: add dma support for lpuart[2..9] Frank Li 2023-08-23 18:12 ` Fabio Estevam 2023-08-23 18:00 ` [PATCH 3/3] arm64: dts: imx93-evk: add uart5 Frank Li
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