From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Bjorn Andersson <andersson@kernel.org>,
Andy Gross <agross@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@linaro.org>
Subject: [PATCH 1/3] dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller
Date: Fri, 25 Aug 2023 20:13:15 +0200 [thread overview]
Message-ID: <20230825-topic-6115_lpasscc-v1-1-d4857be298e3@linaro.org> (raw)
In-Reply-To: <20230825-topic-6115_lpasscc-v1-0-d4857be298e3@linaro.org>
SM6115 (and its derivatives or similar SoCs) have a LPASS clock
controller block which provides audio-related resets.
Add bindings for it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../bindings/clock/qcom,sm6115-lpasscc.yaml | 53 ++++++++++++++++++++++
include/dt-bindings/clock/qcom,sm6115-lpasscc.h | 15 ++++++
2 files changed, 68 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml
new file mode 100644
index 000000000000..58ee84aed073
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS Core & Audio Clock Controller on SM6115
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ Qualcomm LPASS core and audio clock controllers provide audio-related resets
+ on SM6115 and its derivatives.
+
+ See also::
+ include/dt-bindings/clock/qcom,sm6115-lpasscc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm6115-lpassaudiocc
+ - qcom,sm6115-lpasscc
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ lpass_audiocc: clock-controller@a6a9000 {
+ compatible = "qcom,sm6115-lpassaudiocc";
+ reg = <0x0a6a9000 0x1000>;
+ #reset-cells = <1>;
+ };
+
+ - |
+ lpasscc: clock-controller@a7ec000 {
+ compatible = "qcom,sm6115-lpasscc";
+ reg = <0x0a7ec000 0x1000>;
+ #reset-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,sm6115-lpasscc.h b/include/dt-bindings/clock/qcom,sm6115-lpasscc.h
new file mode 100644
index 000000000000..799274517c9a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm6115-lpasscc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Linaro Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H
+#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H
+
+/* LPASS CC */
+#define LPASS_SWR_TX_CONFIG_CGCR 0
+
+/* LPASS_AUDIO CC */
+#define LPASS_AUDIO_SWR_RX_CGCR 0
+
+#endif
--
2.42.0
next prev parent reply other threads:[~2023-08-25 18:15 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-25 18:13 [PATCH 0/3] SM6115 LPASSCC Konrad Dybcio
2023-08-25 18:13 ` Konrad Dybcio [this message]
2023-08-26 9:28 ` [PATCH 1/3] dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller Krzysztof Kozlowski
2023-08-26 9:39 ` Konrad Dybcio
2023-08-26 9:46 ` Krzysztof Kozlowski
2023-08-25 18:13 ` [PATCH 2/3] clk: qcom: reset: Increase max reset delay Konrad Dybcio
2023-08-25 18:13 ` [PATCH 3/3] clk: qcom: Add SM6115 LPASSCC Konrad Dybcio
2023-08-26 9:22 ` Krzysztof Kozlowski
2023-08-26 14:09 ` Dmitry Baryshkov
2023-08-26 14:29 ` Krzysztof Kozlowski
2023-08-28 11:45 ` Konrad Dybcio
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