[PATCH] riscv: dts: allwinner: d1: Add PMU event node

[PATCH] riscv: dts: allwinner: d1: Add PMU event node

[Inochi Amaoto]

D1 has several pmu events supported by opensbi.
These events can be used by perf for profiling.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index 8275630af977..d9031ccdec89 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
@@ -72,5 +72,45 @@ plic: interrupt-controller@10000000 {
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 		};
+
+		pmu {
+			compatible = "riscv,pmu";
+			riscv,event-to-mhpmcounters =
+				<0x00003 0x00003 0x00000008>,
+				<0x00004 0x00004 0x00000010>,
+				<0x00005 0x00005 0x00000200>,
+				<0x00006 0x00006 0x00000100>,
+				<0x10000 0x10000 0x00004000>,
+				<0x10001 0x10001 0x00008000>,
+				<0x10002 0x10002 0x00010000>,
+				<0x10003 0x10003 0x00020000>,
+				<0x10019 0x10019 0x00000040>,
+				<0x10021 0x10021 0x00000020>;
+			riscv,event-to-mhpmevent =
+				<0x00003 0x00000000 0x00000001>,
+				<0x00004 0x00000000 0x00000002>,
+				<0x00005 0x00000000 0x00000007>,
+				<0x00006 0x00000000 0x00000006>,
+				<0x0000a 0x00000000 0x0000000b>,
+				<0x10000 0x00000000 0x0000000c>,
+				<0x10001 0x00000000 0x0000000d>,
+				<0x10002 0x00000000 0x0000000e>,
+				<0x10003 0x00000000 0x0000000f>,
+				<0x10019 0x00000000 0x00000004>,
+				<0x10021 0x00000000 0x00000003>;
+			riscv,raw-event-to-mhpmcounters =
+				<0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
+				<0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
+				<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
+				<0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
+				<0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
+				<0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
+				<0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
+				<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
+				<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
+				<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
+				<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
+				<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
+		};
 	};
 };
-- 
2.41.0

Re: [PATCH] riscv: dts: allwinner: d1: Add PMU event node

[Conor Dooley]

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On Sat, Aug 26, 2023 at 04:38:53PM +0800, Inochi Amaoto wrote:
> D1 has several pmu events supported by opensbi.
> These events can be used by perf for profiling.
> 
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>

Could you please include a link to some documentation as to where these
values came from? I know several people have had some trouble with
understanding the pmu DT stuff & having some documentation would make
this an in-tree end-to-end example.

Thanks,
Conor.

> ---
>  arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 40 +++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> index 8275630af977..d9031ccdec89 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -72,5 +72,45 @@ plic: interrupt-controller@10000000 {
>  			#address-cells = <0>;
>  			#interrupt-cells = <2>;
>  		};
> +
> +		pmu {
> +			compatible = "riscv,pmu";
> +			riscv,event-to-mhpmcounters =
> +				<0x00003 0x00003 0x00000008>,
> +				<0x00004 0x00004 0x00000010>,
> +				<0x00005 0x00005 0x00000200>,
> +				<0x00006 0x00006 0x00000100>,
> +				<0x10000 0x10000 0x00004000>,
> +				<0x10001 0x10001 0x00008000>,
> +				<0x10002 0x10002 0x00010000>,
> +				<0x10003 0x10003 0x00020000>,
> +				<0x10019 0x10019 0x00000040>,
> +				<0x10021 0x10021 0x00000020>;
> +			riscv,event-to-mhpmevent =
> +				<0x00003 0x00000000 0x00000001>,
> +				<0x00004 0x00000000 0x00000002>,
> +				<0x00005 0x00000000 0x00000007>,
> +				<0x00006 0x00000000 0x00000006>,
> +				<0x0000a 0x00000000 0x0000000b>,
> +				<0x10000 0x00000000 0x0000000c>,
> +				<0x10001 0x00000000 0x0000000d>,
> +				<0x10002 0x00000000 0x0000000e>,
> +				<0x10003 0x00000000 0x0000000f>,
> +				<0x10019 0x00000000 0x00000004>,
> +				<0x10021 0x00000000 0x00000003>;
> +			riscv,raw-event-to-mhpmcounters =
> +				<0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
> +				<0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
> +				<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
> +				<0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
> +				<0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
> +				<0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
> +				<0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
> +				<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
> +				<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
> +				<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
> +				<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
> +				<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
> +		};
>  	};
>  };
> -- 
> 2.41.0
> 

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Re: [PATCH] riscv: dts: allwinner: d1: Add PMU event node

[Inochi Amaoto]

The DT field of riscv,pmu for opensbi can be found on:
https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md

The value can be found in the R1S0 version of C906 documentation:
https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf

The meaning of T-HEAD events can be found in this patch:
https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com

The patch above also provides documentation for T-HEAD events and a example
that shows how to use perf with T-HEAD events.

>On Sat, Aug 26, 2023 at 04:38:53PM +0800, Inochi Amaoto wrote:
>> D1 has several pmu events supported by opensbi.
>> These events can be used by perf for profiling.
>>
>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>
>Could you please include a link to some documentation as to where these
>values came from? I know several people have had some trouble with
>understanding the pmu DT stuff & having some documentation would make
>this an in-tree end-to-end example.
>
>Thanks,
>Conor.
>

Re: [PATCH] riscv: dts: allwinner: d1: Add PMU event node

[Conor Dooley]

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On Sat, Aug 26, 2023 at 07:25:43PM +0800, Inochi Amaoto wrote:

> >On Sat, Aug 26, 2023 at 04:38:53PM +0800, Inochi Amaoto wrote:
> >> D1 has several pmu events supported by opensbi.
> >> These events can be used by perf for profiling.
> >>
> >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> >
> >Could you please include a link to some documentation as to where these
> >values came from? I know several people have had some trouble with
> >understanding the pmu DT stuff & having some documentation would make
> >this an in-tree end-to-end example.

> The DT field of riscv,pmu for opensbi can be found on:
> https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md

There's an actual dt-binding for this.

> The value can be found in the R1S0 version of C906 documentation:
> https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
> 
> The meaning of T-HEAD events can be found in this patch:
> https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com
> 
> The patch above also provides documentation for T-HEAD events and a example
> that shows how to use perf with T-HEAD events.

What I meant was can you provide links to this in the commit messages so
that people have a way to find the documentation.


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Re: [PATCH] riscv: dts: allwinner: d1: Add PMU event node

[Inochi Amaoto]

>>> On Sat, Aug 26, 2023 at 04:38:53PM +0800, Inochi Amaoto wrote:
>>>> D1 has several pmu events supported by opensbi.
>>>> These events can be used by perf for profiling.
>>>>
>>>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>>>
>>> Could you please include a link to some documentation as to where these
>>> values came from? I know several people have had some trouble with
>>> understanding the pmu DT stuff & having some documentation would make
>>> this an in-tree end-to-end example.
>
>> The DT field of riscv,pmu for opensbi can be found on:
>> https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md
>
>There's an actual dt-binding for this.
>
>> The value can be found in the R1S0 version of C906 documentation:
>> https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
>>
>> The meaning of T-HEAD events can be found in this patch:
>> https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com
>>
>> The patch above also provides documentation for T-HEAD events and a example
>> that shows how to use perf with T-HEAD events.
>
>What I meant was can you provide links to this in the commit messages so
>that people have a way to find the documentation.

OK, I will setup a new patch to cover these info.

Re: [PATCH v4] riscv: dts: allwinner: d1: Add PMU event node

[Conor Dooley]

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On Mon, Aug 28, 2023 at 12:30:22PM +0800, Inochi Amaoto wrote:
> D1 has several pmu events supported by opensbi.
> These events can be used by perf for profiling.
> 
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
> Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
> ---
> changed from v3:
> 1. remove wrong event mapping of 0x0000a
> 2. add reference url of c906 events implementation (D1 only support events
> described in R1S0 user manual, but event mapping is the same)

Why'd you drop my ack? There's nothing here that'd invalidate it AFAICT.
Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> 
> changed from v2:
> 1. move pmu node from /soc to / to avoid warnings when checking.
> 
> The meaning of T-HEAD events can be found in this pending patch:
> https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com
> 
> The patch above also provides a example that shows how to setup
> environment and use perf with T-HEAD events.
> ---
>  arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> index 8275630af977..53a984d78e3f 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -73,4 +73,43 @@ plic: interrupt-controller@10000000 {
>  			#interrupt-cells = <2>;
>  		};
>  	};
> +
> +	pmu {
> +		compatible = "riscv,pmu";
> +		riscv,event-to-mhpmcounters =
> +			<0x00003 0x00003 0x00000008>,
> +			<0x00004 0x00004 0x00000010>,
> +			<0x00005 0x00005 0x00000200>,
> +			<0x00006 0x00006 0x00000100>,
> +			<0x10000 0x10000 0x00004000>,
> +			<0x10001 0x10001 0x00008000>,
> +			<0x10002 0x10002 0x00010000>,
> +			<0x10003 0x10003 0x00020000>,
> +			<0x10019 0x10019 0x00000040>,
> +			<0x10021 0x10021 0x00000020>;
> +		riscv,event-to-mhpmevent =
> +			<0x00003 0x00000000 0x00000001>,
> +			<0x00004 0x00000000 0x00000002>,
> +			<0x00005 0x00000000 0x00000007>,
> +			<0x00006 0x00000000 0x00000006>,
> +			<0x10000 0x00000000 0x0000000c>,
> +			<0x10001 0x00000000 0x0000000d>,
> +			<0x10002 0x00000000 0x0000000e>,
> +			<0x10003 0x00000000 0x0000000f>,
> +			<0x10019 0x00000000 0x00000004>,
> +			<0x10021 0x00000000 0x00000003>;
> +		riscv,raw-event-to-mhpmcounters =
> +			<0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
> +			<0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
> +			<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
> +			<0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
> +			<0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
> +			<0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
> +			<0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
> +			<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
> +			<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
> +			<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
> +			<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
> +			<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
> +	};
>  };
> --
> 2.42.0
> 

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Re: [PATCH] riscv: dts: allwinner: d1: Add PMU event node

[Inochi Amaoto]

>On Mon, Aug 28, 2023 at 12:30:22PM +0800, Inochi Amaoto wrote:
>> D1 has several pmu events supported by opensbi.
>> These events can be used by perf for profiling.
>>
>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
>> Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
>> ---
>> changed from v3:
>> 1. remove wrong event mapping of 0x0000a
>> 2. add reference url of c906 events implementation (D1 only support events
>> described in R1S0 user manual, but event mapping is the same)
>
>Why'd you drop my ack? There's nothing here that'd invalidate it AFAICT.
>Acked-by: Conor Dooley <conor.dooley@microchip.com>
>
>Thanks,
>Conor.

Sorry for this, I am not sure whether to preserve the ack.
Thank you for your ack again, and I will reserve this if no big change
happens.

Re: [PATCH] riscv: dts: allwinner: d1: Add PMU event node

[Krzysztof Kozlowski]

On 28/08/2023 08:41, Inochi Amaoto wrote:
>> On Mon, Aug 28, 2023 at 12:30:22PM +0800, Inochi Amaoto wrote:
>>> D1 has several pmu events supported by opensbi.
>>> These events can be used by perf for profiling.
>>>
>>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>>> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
>>> Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
>>> ---
>>> changed from v3:
>>> 1. remove wrong event mapping of 0x0000a
>>> 2. add reference url of c906 events implementation (D1 only support events
>>> described in R1S0 user manual, but event mapping is the same)
>>
>> Why'd you drop my ack? There's nothing here that'd invalidate it AFAICT.
>> Acked-by: Conor Dooley <conor.dooley@microchip.com>
>>
>> Thanks,
>> Conor.
> 
> Sorry for this, I am not sure whether to preserve the ack.
> Thank you for your ack again, and I will reserve this if no big change
> happens.

https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577

Best regards,
Krzysztof