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From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
To: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konrad.dybcio@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
	Alex Elder <elder@linaro.org>,
	Srini Kandagatla <srinivas.kandagatla@linaro.org>
Cc: kernel@quicinc.com, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Subject: [PATCH 01/11] firmware: qcom-scm: drop unneeded 'extern' specifiers
Date: Mon, 28 Aug 2023 21:24:57 +0200	[thread overview]
Message-ID: <20230828192507.117334-2-bartosz.golaszewski@linaro.org> (raw)
In-Reply-To: <20230828192507.117334-1-bartosz.golaszewski@linaro.org>

The 'extern' specifier in front of a function declaration has no effect.
Remove all of them from the qcom-scm header.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
 include/linux/firmware/qcom/qcom_scm.h | 101 ++++++++++++-------------
 1 file changed, 48 insertions(+), 53 deletions(-)

diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h
index 250ea4efb7cb..0187fc54249e 100644
--- a/include/linux/firmware/qcom/qcom_scm.h
+++ b/include/linux/firmware/qcom/qcom_scm.h
@@ -59,12 +59,12 @@ enum qcom_scm_ice_cipher {
 #define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
 #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
 
-extern bool qcom_scm_is_available(void);
+bool qcom_scm_is_available(void);
 
-extern int qcom_scm_set_cold_boot_addr(void *entry);
-extern int qcom_scm_set_warm_boot_addr(void *entry);
-extern void qcom_scm_cpu_power_down(u32 flags);
-extern int qcom_scm_set_remote_state(u32 state, u32 id);
+int qcom_scm_set_cold_boot_addr(void *entry);
+int qcom_scm_set_warm_boot_addr(void *entry);
+void qcom_scm_cpu_power_down(u32 flags);
+int qcom_scm_set_remote_state(u32 state, u32 id);
 
 struct qcom_scm_pas_metadata {
 	void *ptr;
@@ -72,54 +72,49 @@ struct qcom_scm_pas_metadata {
 	ssize_t size;
 };
 
-extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
-				   size_t size,
-				   struct qcom_scm_pas_metadata *ctx);
+int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size,
+			    struct qcom_scm_pas_metadata *ctx);
 void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
-extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
-				  phys_addr_t size);
-extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
-extern int qcom_scm_pas_shutdown(u32 peripheral);
-extern bool qcom_scm_pas_supported(u32 peripheral);
-
-extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
-extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
-
-extern bool qcom_scm_restore_sec_cfg_available(void);
-extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
-extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
-extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
-extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);
-extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
-					  u32 cp_nonpixel_start,
-					  u32 cp_nonpixel_size);
-extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
-			       u64 *src,
-			       const struct qcom_scm_vmperm *newvm,
-			       unsigned int dest_cnt);
-
-extern bool qcom_scm_ocmem_lock_available(void);
-extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
-			       u32 size, u32 mode);
-extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
-				 u32 size);
-
-extern bool qcom_scm_ice_available(void);
-extern int qcom_scm_ice_invalidate_key(u32 index);
-extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
-				enum qcom_scm_ice_cipher cipher,
-				u32 data_unit_size);
-
-extern bool qcom_scm_hdcp_available(void);
-extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
-			     u32 *resp);
-
-extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
-extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
-
-extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
-			      u64 limit_node, u32 node_id, u64 version);
-extern int qcom_scm_lmh_profile_change(u32 profile_id);
-extern bool qcom_scm_lmh_dcvsh_available(void);
+int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);
+int qcom_scm_pas_auth_and_reset(u32 peripheral);
+int qcom_scm_pas_shutdown(u32 peripheral);
+bool qcom_scm_pas_supported(u32 peripheral);
+
+int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
+int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
+
+bool qcom_scm_restore_sec_cfg_available(void);
+int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
+int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
+int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
+int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);
+int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
+				   u32 cp_nonpixel_start,
+				   u32 cp_nonpixel_size);
+int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, u64 *src,
+			const struct qcom_scm_vmperm *newvm,
+			unsigned int dest_cnt);
+
+bool qcom_scm_ocmem_lock_available(void);
+int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
+			u32 size, u32 mode);
+int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size);
+
+bool qcom_scm_ice_available(void);
+int qcom_scm_ice_invalidate_key(u32 index);
+int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
+			 enum qcom_scm_ice_cipher cipher,
+			 u32 data_unit_size);
+
+bool qcom_scm_hdcp_available(void);
+int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
+
+int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
+int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
+
+int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
+		       u64 limit_node, u32 node_id, u64 version);
+int qcom_scm_lmh_profile_change(u32 profile_id);
+bool qcom_scm_lmh_dcvsh_available(void);
 
 #endif
-- 
2.39.2


  reply	other threads:[~2023-08-28 19:28 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-28 19:24 [PATCH 00/11] arm64: qcom: add and enable SHM Bridge support Bartosz Golaszewski
2023-08-28 19:24 ` Bartosz Golaszewski [this message]
2023-08-29  7:51   ` [PATCH 01/11] firmware: qcom-scm: drop unneeded 'extern' specifiers Krzysztof Kozlowski
2023-09-13 19:22   ` Bjorn Andersson
2023-08-28 19:24 ` [PATCH 02/11] firmware: qcom-scm: order includes alphabetically Bartosz Golaszewski
2023-08-29  7:52   ` Krzysztof Kozlowski
2023-08-28 19:24 ` [PATCH 03/11] firmware: qcom-scm: atomically assign and read the global __scm pointer Bartosz Golaszewski
2023-08-29  7:59   ` Krzysztof Kozlowski
2023-08-29 12:31     ` Bartosz Golaszewski
2023-08-29 12:48       ` Krzysztof Kozlowski
2023-10-17  8:24   ` Om Prakash Singh
2023-10-17  8:29     ` Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 04/11] firmware: qcom-scm: add support for SHM bridge operations Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 05/11] dt-bindings: document the Qualcomm TEE Shared Memory Bridge Bartosz Golaszewski
2023-08-29  8:02   ` Krzysztof Kozlowski
2023-08-29  9:30     ` Konrad Dybcio
2023-08-30 13:48       ` Bartosz Golaszewski
2023-08-30 14:31         ` Krzysztof Kozlowski
2023-08-30 14:39           ` Bartosz Golaszewski
2023-08-30 14:58             ` Krzysztof Kozlowski
2023-08-30 16:21               ` Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 06/11] firmware: qcom-shm-bridge: new driver Bartosz Golaszewski
2023-08-29  8:18   ` Krzysztof Kozlowski
2023-08-29 13:24     ` Bartosz Golaszewski
2023-08-29 16:47       ` Krzysztof Kozlowski
2023-08-30 13:09         ` Bartosz Golaszewski
2023-08-30 14:31           ` Krzysztof Kozlowski
2023-08-29  8:22   ` Krzysztof Kozlowski
2023-08-28 19:25 ` [PATCH 07/11] firmware: qcom-scm: use SHM bridge if available Bartosz Golaszewski
2023-08-29  5:32   ` kernel test robot
2023-08-29  5:43   ` kernel test robot
2023-08-28 19:25 ` [PATCH 08/11] arm64: defconfig: enable Qualcomm SHM bridge module Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 09/11] arm64: dts: qcom: sm8450: enable SHM bridge Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 10/11] arm64: dts: qcom: sa8775p: " Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 11/11] arm64: dts: qcom: sm8150: " Bartosz Golaszewski
2023-08-28 21:23 ` [PATCH 00/11] arm64: qcom: add and enable SHM Bridge support Dmitry Baryshkov
2023-08-29 19:03   ` Bartosz Golaszewski
2023-08-29 20:48     ` Dmitry Baryshkov
2023-09-14 19:36 ` (subset) " Bjorn Andersson

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