devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
To: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konrad.dybcio@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
	Alex Elder <elder@linaro.org>,
	Srini Kandagatla <srinivas.kandagatla@linaro.org>
Cc: kernel@quicinc.com, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Subject: [PATCH 04/11] firmware: qcom-scm: add support for SHM bridge operations
Date: Mon, 28 Aug 2023 21:25:00 +0200	[thread overview]
Message-ID: <20230828192507.117334-5-bartosz.golaszewski@linaro.org> (raw)
In-Reply-To: <20230828192507.117334-1-bartosz.golaszewski@linaro.org>

Add low-level primitives for enabling SHM bridge support, creating SHM
bridge pools and testing the availability of SHM bridges to qcom-scm. We
don't yet provide a way to destroy the bridges as the first user will
not require it.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
 drivers/firmware/qcom_scm.c            | 83 ++++++++++++++++++++++++++
 drivers/firmware/qcom_scm.h            |  3 +
 include/linux/firmware/qcom/qcom_scm.h |  8 +++
 3 files changed, 94 insertions(+)

diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 422de70faff8..f45d5a424424 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -31,6 +31,8 @@ module_param(download_mode, bool, 0);
 #define SCM_HAS_IFACE_CLK	BIT(1)
 #define SCM_HAS_BUS_CLK		BIT(2)
 
+#define SCM_SHM_BRIDGE_NOTSUPP	4
+
 struct qcom_scm {
 	struct device *dev;
 	struct clk *core_clk;
@@ -45,6 +47,8 @@ struct qcom_scm {
 	int scm_vote_count;
 
 	u64 dload_mode_addr;
+
+	bool shm_bridge_enabled;
 };
 
 struct qcom_scm_current_perm_info {
@@ -1248,6 +1252,85 @@ bool qcom_scm_lmh_dcvsh_available(void)
 }
 EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available);
 
+bool qcom_scm_shm_bridge_available(void)
+{
+	if (!qcom_scm_is_available())
+		return false;
+
+	return READ_ONCE(__scm->shm_bridge_enabled);
+}
+EXPORT_SYMBOL_GPL(qcom_scm_shm_bridge_available);
+
+/*
+ * Must not be called unless qcom_scm_shm_bridge_available() returned true
+ * first.
+ */
+int qcom_scm_enable_shm_bridge(void)
+{
+	struct qcom_scm_desc desc = {
+		.svc = QCOM_SCM_SVC_MP,
+		.cmd = QCOM_SCM_MP_SHM_BRIDGE_ENABLE,
+		.owner = ARM_SMCCC_OWNER_SIP
+	};
+
+	struct qcom_scm_res res;
+	int ret;
+
+	ret = qcom_scm_call(__scm->dev, &desc, &res);
+	if (!ret && !res.result[0])
+		WRITE_ONCE(__scm->shm_bridge_enabled, true);
+
+	if (res.result[0] == SCM_SHM_BRIDGE_NOTSUPP)
+		ret = -EOPNOTSUPP;
+
+	return ret ?: res.result[0];
+}
+EXPORT_SYMBOL_GPL(qcom_scm_enable_shm_bridge);
+
+int qcom_scm_create_shm_bridge(struct device *dev, u64 pfn_and_ns_perm_flags,
+			       u64 ipfn_and_s_perm_flags, u64 size_and_flags,
+			       u64 ns_vmids, u64 *handle)
+{
+	struct qcom_scm_desc desc = {
+		.svc = QCOM_SCM_SVC_MP,
+		.cmd = QCOM_SCM_MP_SHM_BRDIGE_CREATE,
+		.owner = ARM_SMCCC_OWNER_SIP
+	};
+
+	struct qcom_scm_res res;
+	int ret;
+
+	desc.args[0] = pfn_and_ns_perm_flags;
+	desc.args[1] = ipfn_and_s_perm_flags;
+	desc.args[2] = size_and_flags;
+	desc.args[3] = ns_vmids;
+
+	desc.arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_VAL, QCOM_SCM_VAL,
+				     QCOM_SCM_VAL, QCOM_SCM_VAL);
+
+	ret = qcom_scm_call(dev ?: __scm->dev, &desc, &res);
+
+	if (handle && !ret)
+		*handle = res.result[1];
+
+	return ret ?: res.result[0];
+}
+EXPORT_SYMBOL_GPL(qcom_scm_create_shm_bridge);
+
+int qcom_scm_delete_shm_bridge(struct device *dev, u64 handle)
+{
+	struct qcom_scm_desc desc = {
+		.svc = QCOM_SCM_SVC_MP,
+		.cmd = QCOM_SCM_MP_SHM_BRIDGE_DELETE,
+		.owner = ARM_SMCCC_OWNER_SIP,
+		.args[0] = handle,
+		.arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL),
+	};
+
+	return qcom_scm_call(dev ?: __scm->dev, &desc, NULL);
+}
+EXPORT_SYMBOL_GPL(qcom_scm_delete_shm_bridge);
+
 int qcom_scm_lmh_profile_change(u32 profile_id)
 {
 	struct qcom_scm_desc desc = {
diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h
index e6e512bd57d1..44d60d06344b 100644
--- a/drivers/firmware/qcom_scm.h
+++ b/drivers/firmware/qcom_scm.h
@@ -111,6 +111,9 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
 #define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE	0x05
 #define QCOM_SCM_MP_VIDEO_VAR			0x08
 #define QCOM_SCM_MP_ASSIGN			0x16
+#define QCOM_SCM_MP_SHM_BRIDGE_ENABLE		0x1c
+#define QCOM_SCM_MP_SHM_BRIDGE_DELETE		0x1d
+#define QCOM_SCM_MP_SHM_BRDIGE_CREATE		0x1e
 
 #define QCOM_SCM_SVC_OCMEM		0x0f
 #define QCOM_SCM_OCMEM_LOCK_CMD		0x01
diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h
index 0187fc54249e..100770380d97 100644
--- a/include/linux/firmware/qcom/qcom_scm.h
+++ b/include/linux/firmware/qcom/qcom_scm.h
@@ -5,6 +5,7 @@
 #ifndef __QCOM_SCM_H
 #define __QCOM_SCM_H
 
+#include <linux/device.h>
 #include <linux/err.h>
 #include <linux/types.h>
 #include <linux/cpumask.h>
@@ -117,4 +118,11 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
 int qcom_scm_lmh_profile_change(u32 profile_id);
 bool qcom_scm_lmh_dcvsh_available(void);
 
+bool qcom_scm_shm_bridge_available(void);
+int qcom_scm_enable_shm_bridge(void);
+int qcom_scm_create_shm_bridge(struct device *dev, u64 pfn_and_ns_perm_flags,
+			       u64 ipfn_and_s_perm_flags, u64 size_and_flags,
+			       u64 ns_vmids, u64 *handle);
+int qcom_scm_delete_shm_bridge(struct device *dev, u64 handle);
+
 #endif
-- 
2.39.2


  parent reply	other threads:[~2023-08-28 19:28 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-28 19:24 [PATCH 00/11] arm64: qcom: add and enable SHM Bridge support Bartosz Golaszewski
2023-08-28 19:24 ` [PATCH 01/11] firmware: qcom-scm: drop unneeded 'extern' specifiers Bartosz Golaszewski
2023-08-29  7:51   ` Krzysztof Kozlowski
2023-09-13 19:22   ` Bjorn Andersson
2023-08-28 19:24 ` [PATCH 02/11] firmware: qcom-scm: order includes alphabetically Bartosz Golaszewski
2023-08-29  7:52   ` Krzysztof Kozlowski
2023-08-28 19:24 ` [PATCH 03/11] firmware: qcom-scm: atomically assign and read the global __scm pointer Bartosz Golaszewski
2023-08-29  7:59   ` Krzysztof Kozlowski
2023-08-29 12:31     ` Bartosz Golaszewski
2023-08-29 12:48       ` Krzysztof Kozlowski
2023-10-17  8:24   ` Om Prakash Singh
2023-10-17  8:29     ` Bartosz Golaszewski
2023-08-28 19:25 ` Bartosz Golaszewski [this message]
2023-08-28 19:25 ` [PATCH 05/11] dt-bindings: document the Qualcomm TEE Shared Memory Bridge Bartosz Golaszewski
2023-08-29  8:02   ` Krzysztof Kozlowski
2023-08-29  9:30     ` Konrad Dybcio
2023-08-30 13:48       ` Bartosz Golaszewski
2023-08-30 14:31         ` Krzysztof Kozlowski
2023-08-30 14:39           ` Bartosz Golaszewski
2023-08-30 14:58             ` Krzysztof Kozlowski
2023-08-30 16:21               ` Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 06/11] firmware: qcom-shm-bridge: new driver Bartosz Golaszewski
2023-08-29  8:18   ` Krzysztof Kozlowski
2023-08-29 13:24     ` Bartosz Golaszewski
2023-08-29 16:47       ` Krzysztof Kozlowski
2023-08-30 13:09         ` Bartosz Golaszewski
2023-08-30 14:31           ` Krzysztof Kozlowski
2023-08-29  8:22   ` Krzysztof Kozlowski
2023-08-28 19:25 ` [PATCH 07/11] firmware: qcom-scm: use SHM bridge if available Bartosz Golaszewski
2023-08-29  5:32   ` kernel test robot
2023-08-29  5:43   ` kernel test robot
2023-08-28 19:25 ` [PATCH 08/11] arm64: defconfig: enable Qualcomm SHM bridge module Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 09/11] arm64: dts: qcom: sm8450: enable SHM bridge Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 10/11] arm64: dts: qcom: sa8775p: " Bartosz Golaszewski
2023-08-28 19:25 ` [PATCH 11/11] arm64: dts: qcom: sm8150: " Bartosz Golaszewski
2023-08-28 21:23 ` [PATCH 00/11] arm64: qcom: add and enable SHM Bridge support Dmitry Baryshkov
2023-08-29 19:03   ` Bartosz Golaszewski
2023-08-29 20:48     ` Dmitry Baryshkov
2023-09-14 19:36 ` (subset) " Bjorn Andersson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230828192507.117334-5-bartosz.golaszewski@linaro.org \
    --to=bartosz.golaszewski@linaro.org \
    --cc=agross@kernel.org \
    --cc=andersson@kernel.org \
    --cc=arnd@arndb.de \
    --cc=catalin.marinas@arm.com \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=elder@linaro.org \
    --cc=kernel@quicinc.com \
    --cc=konrad.dybcio@linaro.org \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=robh+dt@kernel.org \
    --cc=srinivas.kandagatla@linaro.org \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).