[PATCH 0/7] 8550 dma coherent and more

[PATCH 0/7] 8550 dma coherent and more

[Konrad Dybcio]

Qualcomm made some under-the-hood changes and made more peripherals
capable of coherent transfers with SM8550.

This series marks them as such and brings fixups to usb and psci-cpuidle.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (7):
      dt-bindings: dmaengine: qcom: gpi: Allow dma-coherent
      dt-bindings: qcom: geni-se: Allow dma-coherent
      arm64: dts: qcom: sm8550: Fix up CPU idle states
      arm64: dts: qcom: sm8550: Mark QUPs and GPI dma-coherent
      arm64: dts: qcom: sm8550: Mark APPS SMMU as dma-coherent
      arm64: dts: qcom: sm8550: Add missing DWC3 quirks
      arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent

 .../devicetree/bindings/dma/qcom,gpi.yaml          |  2 +
 .../devicetree/bindings/soc/qcom/qcom,geni-se.yaml |  2 +
 arch/arm64/boot/dts/qcom/sm8550.dtsi               | 52 ++++++++++++++++------
 3 files changed, 42 insertions(+), 14 deletions(-)
---
base-commit: 56585460cc2ec44fc5d66924f0a116f57080f0dc
change-id: 20230830-topic-8550_dmac2-7986d683d9bf

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@linaro.org>

[PATCH 1/7] dt-bindings: dmaengine: qcom: gpi: Allow dma-coherent

[Konrad Dybcio]

On SM8550, the GPI DMA controller is coherent with the CPU.
Allow specifying that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
index f61145c91b6d..88d0de3d1b46 100644
--- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
+++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
@@ -69,6 +69,8 @@ properties:
   dma-channel-mask:
     maxItems: 1
 
+  dma-coherent: true
+
 required:
   - compatible
   - reg

-- 
2.42.0

Re: [PATCH 1/7] dt-bindings: dmaengine: qcom: gpi: Allow dma-coherent

[Rob Herring]

On Wed, 30 Aug 2023 14:48:40 +0200, Konrad Dybcio wrote:
> On SM8550, the GPI DMA controller is coherent with the CPU.
> Allow specifying that.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 2/7] dt-bindings: qcom: geni-se: Allow dma-coherent

[Konrad Dybcio]

On SM8550, the QUP controller is coherent with the CPU.
Allow specifying that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
index 8a4b7ba3aaf6..7b031ef09669 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
@@ -52,6 +52,8 @@ properties:
   iommus:
     maxItems: 1
 
+  dma-coherent: true
+
 required:
   - compatible
   - reg

-- 
2.42.0

Re: [PATCH 2/7] dt-bindings: qcom: geni-se: Allow dma-coherent

[Rob Herring]

On Wed, 30 Aug 2023 14:48:41 +0200, Konrad Dybcio wrote:
> On SM8550, the QUP controller is coherent with the CPU.
> Allow specifying that.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 3/7] arm64: dts: qcom: sm8550: Fix up CPU idle states

[Konrad Dybcio]

The idle residency times are largely too low according to the vendor
kernel (maybe they came from an earlier release or something), especially
for the prime X2 core. Fix them.

Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 32 +++++++++++++++++++++-----------
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index d115960bdeec..c21ba6afa752 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -283,9 +283,9 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 				compatible = "arm,idle-state";
 				idle-state-name = "silver-rail-power-collapse";
 				arm,psci-suspend-param = <0x40000004>;
-				entry-latency-us = <800>;
+				entry-latency-us = <550>;
 				exit-latency-us = <750>;
-				min-residency-us = <4090>;
+				min-residency-us = <6700>;
 				local-timer-stop;
 			};
 
@@ -294,8 +294,18 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 				idle-state-name = "gold-rail-power-collapse";
 				arm,psci-suspend-param = <0x40000004>;
 				entry-latency-us = <600>;
-				exit-latency-us = <1550>;
-				min-residency-us = <4791>;
+				exit-latency-us = <1300>;
+				min-residency-us = <8136>;
+				local-timer-stop;
+			};
+
+			PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "gold-plus-rail-power-collapse";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <500>;
+				exit-latency-us = <1350>;
+				min-residency-us = <7480>;
 				local-timer-stop;
 			};
 		};
@@ -304,17 +314,17 @@ domain-idle-states {
 			CLUSTER_SLEEP_0: cluster-sleep-0 {
 				compatible = "domain-idle-state";
 				arm,psci-suspend-param = <0x41000044>;
-				entry-latency-us = <1050>;
-				exit-latency-us = <2500>;
-				min-residency-us = <5309>;
+				entry-latency-us = <750>;
+				exit-latency-us = <2350>;
+				min-residency-us = <9144>;
 			};
 
 			CLUSTER_SLEEP_1: cluster-sleep-1 {
 				compatible = "domain-idle-state";
 				arm,psci-suspend-param = <0x4100c344>;
-				entry-latency-us = <2700>;
-				exit-latency-us = <3500>;
-				min-residency-us = <13959>;
+				entry-latency-us = <2800>;
+				exit-latency-us = <4400>;
+				min-residency-us = <10150>;
 			};
 		};
 	};
@@ -398,7 +408,7 @@ CPU_PD6: power-domain-cpu6 {
 		CPU_PD7: power-domain-cpu7 {
 			#power-domain-cells = <0>;
 			power-domains = <&CLUSTER_PD>;
-			domain-idle-states = <&BIG_CPU_SLEEP_0>;
+			domain-idle-states = <&PRIME_CPU_SLEEP_0>;
 		};
 
 		CLUSTER_PD: power-domain-cluster {

-- 
2.42.0

Re: [PATCH 3/7] arm64: dts: qcom: sm8550: Fix up CPU idle states

[Dmitry Baryshkov]

On Wed, 30 Aug 2023 at 22:04, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> The idle residency times are largely too low according to the vendor
> kernel (maybe they came from an earlier release or something), especially
> for the prime X2 core. Fix them.
>
> Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 32 +++++++++++++++++++++-----------
>  1 file changed, 21 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index d115960bdeec..c21ba6afa752 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -283,9 +283,9 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
>                                 compatible = "arm,idle-state";
>                                 idle-state-name = "silver-rail-power-collapse";
>                                 arm,psci-suspend-param = <0x40000004>;
> -                               entry-latency-us = <800>;
> +                               entry-latency-us = <550>;
>                                 exit-latency-us = <750>;
> -                               min-residency-us = <4090>;
> +                               min-residency-us = <6700>;
>                                 local-timer-stop;
>                         };
>
> @@ -294,8 +294,18 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
>                                 idle-state-name = "gold-rail-power-collapse";
>                                 arm,psci-suspend-param = <0x40000004>;
>                                 entry-latency-us = <600>;
> -                               exit-latency-us = <1550>;
> -                               min-residency-us = <4791>;
> +                               exit-latency-us = <1300>;
> +                               min-residency-us = <8136>;
> +                               local-timer-stop;
> +                       };
> +
> +                       PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
> +                               compatible = "arm,idle-state";
> +                               idle-state-name = "gold-plus-rail-power-collapse";
> +                               arm,psci-suspend-param = <0x40000004>;
> +                               entry-latency-us = <500>;
> +                               exit-latency-us = <1350>;
> +                               min-residency-us = <7480>;
>                                 local-timer-stop;

This isn't only fixing the time properties, but also adds the whole
new sleep state!

>                         };
>                 };
> @@ -304,17 +314,17 @@ domain-idle-states {
>                         CLUSTER_SLEEP_0: cluster-sleep-0 {
>                                 compatible = "domain-idle-state";
>                                 arm,psci-suspend-param = <0x41000044>;
> -                               entry-latency-us = <1050>;
> -                               exit-latency-us = <2500>;
> -                               min-residency-us = <5309>;
> +                               entry-latency-us = <750>;
> +                               exit-latency-us = <2350>;
> +                               min-residency-us = <9144>;
>                         };
>
>                         CLUSTER_SLEEP_1: cluster-sleep-1 {
>                                 compatible = "domain-idle-state";
>                                 arm,psci-suspend-param = <0x4100c344>;
> -                               entry-latency-us = <2700>;
> -                               exit-latency-us = <3500>;
> -                               min-residency-us = <13959>;
> +                               entry-latency-us = <2800>;
> +                               exit-latency-us = <4400>;
> +                               min-residency-us = <10150>;
>                         };
>                 };
>         };
> @@ -398,7 +408,7 @@ CPU_PD6: power-domain-cpu6 {
>                 CPU_PD7: power-domain-cpu7 {
>                         #power-domain-cells = <0>;
>                         power-domains = <&CLUSTER_PD>;
> -                       domain-idle-states = <&BIG_CPU_SLEEP_0>;
> +                       domain-idle-states = <&PRIME_CPU_SLEEP_0>;
>                 };
>
>                 CLUSTER_PD: power-domain-cluster {
>
> --
> 2.42.0
>


-- 
With best wishes
Dmitry

Re: [PATCH 3/7] arm64: dts: qcom: sm8550: Fix up CPU idle states

[Konrad Dybcio]

On 30.08.2023 22:13, Dmitry Baryshkov wrote:
> On Wed, 30 Aug 2023 at 22:04, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>> The idle residency times are largely too low according to the vendor
>> kernel (maybe they came from an earlier release or something), especially
>> for the prime X2 core. Fix them.
>>
>> Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi")
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 32 +++++++++++++++++++++-----------
>>  1 file changed, 21 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> index d115960bdeec..c21ba6afa752 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> @@ -283,9 +283,9 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
>>                                 compatible = "arm,idle-state";
>>                                 idle-state-name = "silver-rail-power-collapse";
>>                                 arm,psci-suspend-param = <0x40000004>;
>> -                               entry-latency-us = <800>;
>> +                               entry-latency-us = <550>;
>>                                 exit-latency-us = <750>;
>> -                               min-residency-us = <4090>;
>> +                               min-residency-us = <6700>;
>>                                 local-timer-stop;
>>                         };
>>
>> @@ -294,8 +294,18 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
>>                                 idle-state-name = "gold-rail-power-collapse";
>>                                 arm,psci-suspend-param = <0x40000004>;
>>                                 entry-latency-us = <600>;
>> -                               exit-latency-us = <1550>;
>> -                               min-residency-us = <4791>;
>> +                               exit-latency-us = <1300>;
>> +                               min-residency-us = <8136>;
>> +                               local-timer-stop;
>> +                       };
>> +
>> +                       PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
>> +                               compatible = "arm,idle-state";
>> +                               idle-state-name = "gold-plus-rail-power-collapse";
>> +                               arm,psci-suspend-param = <0x40000004>;
>> +                               entry-latency-us = <500>;
>> +                               exit-latency-us = <1350>;
>> +                               min-residency-us = <7480>;
>>                                 local-timer-stop;
> 
> This isn't only fixing the time properties, but also adds the whole
> new sleep state!
It does add a "new" sleep state with the exact same parameters,
the only thing being that it's exclusive to the prime core and
the only thing that differs is the residencies.

Konrad

Re: [PATCH 3/7] arm64: dts: qcom: sm8550: Fix up CPU idle states

[Dmitry Baryshkov]

On Wed, 30 Aug 2023 at 23:35, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 30.08.2023 22:13, Dmitry Baryshkov wrote:
> > On Wed, 30 Aug 2023 at 22:04, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
> >>
> >> The idle residency times are largely too low according to the vendor
> >> kernel (maybe they came from an earlier release or something), especially
> >> for the prime X2 core. Fix them.
> >>
> >> Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi")
> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> >> ---
> >>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 32 +++++++++++++++++++++-----------
> >>  1 file changed, 21 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> >> index d115960bdeec..c21ba6afa752 100644
> >> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> >> @@ -283,9 +283,9 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
> >>                                 compatible = "arm,idle-state";
> >>                                 idle-state-name = "silver-rail-power-collapse";
> >>                                 arm,psci-suspend-param = <0x40000004>;
> >> -                               entry-latency-us = <800>;
> >> +                               entry-latency-us = <550>;
> >>                                 exit-latency-us = <750>;
> >> -                               min-residency-us = <4090>;
> >> +                               min-residency-us = <6700>;
> >>                                 local-timer-stop;
> >>                         };
> >>
> >> @@ -294,8 +294,18 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
> >>                                 idle-state-name = "gold-rail-power-collapse";
> >>                                 arm,psci-suspend-param = <0x40000004>;
> >>                                 entry-latency-us = <600>;
> >> -                               exit-latency-us = <1550>;
> >> -                               min-residency-us = <4791>;
> >> +                               exit-latency-us = <1300>;
> >> +                               min-residency-us = <8136>;
> >> +                               local-timer-stop;
> >> +                       };
> >> +
> >> +                       PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
> >> +                               compatible = "arm,idle-state";
> >> +                               idle-state-name = "gold-plus-rail-power-collapse";
> >> +                               arm,psci-suspend-param = <0x40000004>;
> >> +                               entry-latency-us = <500>;
> >> +                               exit-latency-us = <1350>;
> >> +                               min-residency-us = <7480>;
> >>                                 local-timer-stop;
> >
> > This isn't only fixing the time properties, but also adds the whole
> > new sleep state!
> It does add a "new" sleep state with the exact same parameters,
> the only thing being that it's exclusive to the prime core and
> the only thing that differs is the residencies.

Then it should be stated in the commit message.

With that fixed,

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>


-- 
With best wishes
Dmitry

[PATCH 4/7] arm64: dts: qcom: sm8550: Mark QUPs and GPI dma-coherent

[Konrad Dybcio]

These peripherals are DMA-coherent on 8550. Mark them as such.

Interestingly enough, the I2C master hubs are not.

Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index c21ba6afa752..d1911b2f0bf3 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -809,6 +809,7 @@ gpi_dma2: dma-controller@800000 {
 			dma-channels = <12>;
 			dma-channel-mask = <0x3e>;
 			iommus = <&apps_smmu 0x436 0>;
+			dma-coherent;
 			status = "disabled";
 		};
 
@@ -820,6 +821,7 @@ qupv3_id_1: geniqup@8c0000 {
 			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 			iommus = <&apps_smmu 0x423 0>;
+			dma-coherent;
 			#address-cells = <2>;
 			#size-cells = <2>;
 			status = "disabled";
@@ -1305,6 +1307,7 @@ gpi_dma1: dma-controller@a00000 {
 			dma-channels = <12>;
 			dma-channel-mask = <0x1e>;
 			iommus = <&apps_smmu 0xb6 0>;
+			dma-coherent;
 			status = "disabled";
 		};
 
@@ -1318,6 +1321,7 @@ qupv3_id_0: geniqup@ac0000 {
 			iommus = <&apps_smmu 0xa3 0>;
 			interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
 			interconnect-names = "qup-core";
+			dma-coherent;
 			#address-cells = <2>;
 			#size-cells = <2>;
 			status = "disabled";

-- 
2.42.0

[PATCH 5/7] arm64: dts: qcom: sm8550: Mark APPS SMMU as dma-coherent

[Konrad Dybcio]

Like on earlier flagship Qualcomm SoCs, the SMMU is dma-coherent.
Mark it as such.

Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index d1911b2f0bf3..944b4b8c95f5 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3655,6 +3655,7 @@ apps_smmu: iommu@15000000 {
 				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
 		};
 
 		intc: interrupt-controller@17100000 {

-- 
2.42.0

Re: [PATCH 5/7] arm64: dts: qcom: sm8550: Mark APPS SMMU as dma-coherent

[Dmitry Baryshkov]

On Wed, 30 Aug 2023 at 21:32, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> Like on earlier flagship Qualcomm SoCs, the SMMU is dma-coherent.
> Mark it as such.

On earlier SoCs we marked Adreno SMMU as dma-coherent, not the apps
one. Only on sm8250 you've added dma-coherent to the apps smmu.

>
> Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 +
>  1 file changed, 1 insertion(+)

-- 
With best wishes
Dmitry

Re: [PATCH 5/7] arm64: dts: qcom: sm8550: Mark APPS SMMU as dma-coherent

[Konrad Dybcio]

On 30.08.2023 22:04, Dmitry Baryshkov wrote:
> On Wed, 30 Aug 2023 at 21:32, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>> Like on earlier flagship Qualcomm SoCs, the SMMU is dma-coherent.
>> Mark it as such.
> 
> On earlier SoCs we marked Adreno SMMU as dma-coherent, not the apps
> one. Only on sm8250 you've added dma-coherent to the apps smmu.
Also applies to 83450, perhaps I just haven't sent them yet or
it's not been merged, don't remember

Konrad

[PATCH 6/7] arm64: dts: qcom: sm8550: Add missing DWC3 quirks

[Konrad Dybcio]

As expected, Qualcomm DWC3 implementation come with a sizable number
of quirks. Make sure to account for all of them.

Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 944b4b8c95f5..8ee61c9383ec 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2930,12 +2930,20 @@ usb_1_dwc3: usb@a600000 {
 				reg = <0x0 0x0a600000 0x0 0xcd00>;
 				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 				iommus = <&apps_smmu 0x40 0x0>;
-				snps,dis_u2_susphy_quirk;
-				snps,dis_enblslpm_quirk;
-				snps,usb3_lpm_capable;
 				phys = <&usb_1_hsphy>,
 				       <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,hird-threshold = /bits/ 8 <0x0>;
+				snps,usb2-gadget-lpm-disable;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
+				snps,is-utmi-l1-suspend;
+				snps,usb3_lpm_capable;
+				snps,usb2-lpm-disable;
+				snps,has-lpm-erratum;
+				tx-fifo-resize;
 
 				ports {
 					#address-cells = <1>;

-- 
2.42.0

Re: [PATCH 6/7] arm64: dts: qcom: sm8550: Add missing DWC3 quirks

[Abel Vesa]

On 23-08-30 14:48:45, Konrad Dybcio wrote:
> As expected, Qualcomm DWC3 implementation come with a sizable number
> of quirks. Make sure to account for all of them.
> 
> Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---

That is a lot of quirks I missed :D.

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>

>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 944b4b8c95f5..8ee61c9383ec 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -2930,12 +2930,20 @@ usb_1_dwc3: usb@a600000 {
>  				reg = <0x0 0x0a600000 0x0 0xcd00>;
>  				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>  				iommus = <&apps_smmu 0x40 0x0>;
> -				snps,dis_u2_susphy_quirk;
> -				snps,dis_enblslpm_quirk;
> -				snps,usb3_lpm_capable;
>  				phys = <&usb_1_hsphy>,
>  				       <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
>  				phy-names = "usb2-phy", "usb3-phy";
> +				snps,hird-threshold = /bits/ 8 <0x0>;
> +				snps,usb2-gadget-lpm-disable;
> +				snps,dis_u2_susphy_quirk;
> +				snps,dis_enblslpm_quirk;
> +				snps,dis-u1-entry-quirk;
> +				snps,dis-u2-entry-quirk;
> +				snps,is-utmi-l1-suspend;
> +				snps,usb3_lpm_capable;
> +				snps,usb2-lpm-disable;
> +				snps,has-lpm-erratum;
> +				tx-fifo-resize;
>  
>  				ports {
>  					#address-cells = <1>;
> 
> -- 
> 2.42.0
> 

[PATCH 7/7] arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent

[Konrad Dybcio]

In a fairly new development, Qualcomm somehow made the DWC3 block
cache-coherent. Annotate that.

Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 8ee61c9383ec..95ba9a9ac78e 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2944,6 +2944,7 @@ usb_1_dwc3: usb@a600000 {
 				snps,usb2-lpm-disable;
 				snps,has-lpm-erratum;
 				tx-fifo-resize;
+				dma-coherent;
 
 				ports {
 					#address-cells = <1>;

-- 
2.42.0

Re: (subset) [PATCH 0/7] 8550 dma coherent and more

[Bjorn Andersson]

On Wed, 30 Aug 2023 14:48:39 +0200, Konrad Dybcio wrote:
> Qualcomm made some under-the-hood changes and made more peripherals
> capable of coherent transfers with SM8550.
> 
> This series marks them as such and brings fixups to usb and psci-cpuidle.
> 
> 

Applied, thanks!

[2/7] dt-bindings: qcom: geni-se: Allow dma-coherent
      commit: 274707b773378f4ce8ba214002b3d67a4d0785ae

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: (subset) [PATCH 0/7] 8550 dma coherent and more

[Vinod Koul]

On Wed, 30 Aug 2023 14:48:39 +0200, Konrad Dybcio wrote:
> Qualcomm made some under-the-hood changes and made more peripherals
> capable of coherent transfers with SM8550.
> 
> This series marks them as such and brings fixups to usb and psci-cpuidle.
> 
> 

Applied, thanks!

[1/7] dt-bindings: dmaengine: qcom: gpi: Allow dma-coherent
      commit: 10c060edf581fdd0d8f23cab84e6c8546c2df8fc

Best regards,
-- 
~Vinod