* [PATCH 0/2] Add support for the phyGATE-Tauri-L IoT Gateway
@ 2023-09-01 9:26 Yannic Moog
2023-09-01 9:26 ` [PATCH 1/2] dt-bindings: arm: fsl: add phyGATE-Tauri-L board Yannic Moog
2023-09-01 9:26 ` [PATCH 2/2] arm64: dts: freescale: add phyGATE-Tauri i.MX 8M Mini Support Yannic Moog
0 siblings, 2 replies; 6+ messages in thread
From: Yannic Moog @ 2023-09-01 9:26 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Li Yang, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team
Cc: devicetree, linux-kernel, linux-arm-kernel, upstream, Yannic Moog
The phyGATE-Tauri-L is a SBC that uses the phyCORE-i.MX8MM SoM, but has
a different carrier board.
This series adds support for the board and most of its interfaces.
Notably, RS485 support is missing.
Signed-off-by: Yannic Moog <y.moog@phytec.de>
---
Yannic Moog (2):
dt-bindings: arm: fsl: add phyGATE-Tauri-L board
arm64: dts: freescale: add phyGATE-Tauri i.MX 8M Mini Support
Documentation/devicetree/bindings/arm/fsl.yaml | 4 +-
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/imx8mm-phygate-tauri-l.dts | 488 +++++++++++++++++++++
3 files changed, 492 insertions(+), 1 deletion(-)
---
base-commit: 2dde18cd1d8fac735875f2e4987f11817cc0bc2c
change-id: 20230828-tauri_upstream_support-08fac2175150
Best regards,
--
Yannic Moog <y.moog@phytec.de>
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/2] dt-bindings: arm: fsl: add phyGATE-Tauri-L board 2023-09-01 9:26 [PATCH 0/2] Add support for the phyGATE-Tauri-L IoT Gateway Yannic Moog @ 2023-09-01 9:26 ` Yannic Moog 2023-09-01 15:39 ` Conor Dooley 2023-09-01 9:26 ` [PATCH 2/2] arm64: dts: freescale: add phyGATE-Tauri i.MX 8M Mini Support Yannic Moog 1 sibling, 1 reply; 6+ messages in thread From: Yannic Moog @ 2023-09-01 9:26 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team Cc: devicetree, linux-kernel, linux-arm-kernel, upstream, Yannic Moog Add dt compatible for the phyGATE-Tauri-L board. It uses the phyCORE-i.MX8MM SoM Signed-off-by: Yannic Moog <y.moog@phytec.de> --- Documentation/devicetree/bindings/arm/fsl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 2510eaa8906d..570794ce2813 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -974,7 +974,9 @@ properties: - description: PHYTEC phyCORE-i.MX8MM SoM based boards items: - - const: phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK + - enum: + - phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK + - phytec,imx8mm-phygate-tauri-l # phyGATE-Tauri-L Gateway - const: phytec,imx8mm-phycore-som # phyCORE-i.MX8MM SoM - const: fsl,imx8mm -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm: fsl: add phyGATE-Tauri-L board 2023-09-01 9:26 ` [PATCH 1/2] dt-bindings: arm: fsl: add phyGATE-Tauri-L board Yannic Moog @ 2023-09-01 15:39 ` Conor Dooley 0 siblings, 0 replies; 6+ messages in thread From: Conor Dooley @ 2023-09-01 15:39 UTC (permalink / raw) To: Yannic Moog Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, devicetree, linux-kernel, linux-arm-kernel, upstream [-- Attachment #1: Type: text/plain, Size: 1185 bytes --] On Fri, Sep 01, 2023 at 11:26:16AM +0200, Yannic Moog wrote: > Add dt compatible for the phyGATE-Tauri-L board. It uses the > phyCORE-i.MX8MM SoM > > Signed-off-by: Yannic Moog <y.moog@phytec.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor. > --- > Documentation/devicetree/bindings/arm/fsl.yaml | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml > index 2510eaa8906d..570794ce2813 100644 > --- a/Documentation/devicetree/bindings/arm/fsl.yaml > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml > @@ -974,7 +974,9 @@ properties: > > - description: PHYTEC phyCORE-i.MX8MM SoM based boards > items: > - - const: phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK > + - enum: > + - phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK > + - phytec,imx8mm-phygate-tauri-l # phyGATE-Tauri-L Gateway > - const: phytec,imx8mm-phycore-som # phyCORE-i.MX8MM SoM > - const: fsl,imx8mm > > > -- > 2.34.1 > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] arm64: dts: freescale: add phyGATE-Tauri i.MX 8M Mini Support 2023-09-01 9:26 [PATCH 0/2] Add support for the phyGATE-Tauri-L IoT Gateway Yannic Moog 2023-09-01 9:26 ` [PATCH 1/2] dt-bindings: arm: fsl: add phyGATE-Tauri-L board Yannic Moog @ 2023-09-01 9:26 ` Yannic Moog 2023-09-25 1:26 ` Shawn Guo 1 sibling, 1 reply; 6+ messages in thread From: Yannic Moog @ 2023-09-01 9:26 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Li Yang, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team Cc: devicetree, linux-kernel, linux-arm-kernel, upstream, Yannic Moog phyGATE-Tauri uses a phyCORE-i.MX8MM SoM. Add device tree for the board. Signed-off-by: Yannic Moog <y.moog@phytec.de> --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mm-phygate-tauri-l.dts | 488 +++++++++++++++++++++ 2 files changed, 489 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a750be13ace8..68e5a878e359 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts new file mode 100644 index 000000000000..457b23aa57fd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include "imx8mm-phycore-som.dtsi" + +/ { + model = "PHYTEC phyGATE-Tauri-L-iMX8MM"; + compatible = "phytec,imx8mm-phygate-tauri-l", + "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + chosen { + stdout-path = &uart3; + }; + + can_osc_40m: can-clock { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "can_osc_40m"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + key { + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + label = "KEY-A"; + linux,code = <30>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-1 { + color = <LED_COLOR_ID_RED>; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + }; + + led-2 { + color = <LED_COLOR_ID_YELLOW>; + gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + }; + }; + + usdhc1_pwrseq: pwr-seq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <60>; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + }; + + reg_usb_hub_vbus: regulator-hub-otg1 { + compatible = "regulator-fixed"; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhubpwr>; + regulator-name = "usb_hub_vbus"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwr>; + regulator-name = "usb_otg1_vbus"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio5 2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* CAN MCP251XFD */ + can0: can@0 { + compatible = "microchip,mcp251xfd"; + clocks = <&can_osc_40m>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + spi-max-frequency = <10000000>; + }; + + tpm: tpm@1 { + compatible = "tcg,tpm_tis-spi"; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + reg = <1>; + spi-max-frequency = <38000000>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + temp_sense0: temperature-sensor@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + interrupt-parent = <&gpio4>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; + #thermal-sensor-cells = <1>; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* PCIe */ +&pcie0 { + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_250M>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +/* RTC */ +&rv3028 { + trickle-resistor-ohms = <3000>; +}; + +&uart1 { + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* UART2 - RS232 */ +&uart2 { + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* UART - console */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + adp-disable; + dr_mode = "otg"; + over-current-active-low; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + vbus-supply = <®_usb_hub_vbus>; + status = "okay"; +}; + +/* SD-Card */ +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_nvcc_sd2>; + status = "okay"; +}; + +&iomuxc { + pinctrl_can_int: can-intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00 + >; + }; + + pinctrl_gpiokeys: keygrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0 + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0 + >; + }; + + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0 + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0 + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0 + >; + }; + + pinctrl_leds: leds1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00 + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* COEX2 */ + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00 + /* COEX1 */ + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 + >; + }; + + pinctrl_tempsense: tempsensegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00 + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00 + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usbhubpwr: usbhubpwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00 + >; + }; + + pinctrl_usbotg1pwr: usbotg1pwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] arm64: dts: freescale: add phyGATE-Tauri i.MX 8M Mini Support 2023-09-01 9:26 ` [PATCH 2/2] arm64: dts: freescale: add phyGATE-Tauri i.MX 8M Mini Support Yannic Moog @ 2023-09-25 1:26 ` Shawn Guo 2023-09-25 6:57 ` Yannic Moog 0 siblings, 1 reply; 6+ messages in thread From: Shawn Guo @ 2023-09-25 1:26 UTC (permalink / raw) To: Yannic Moog Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Li Yang, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team, devicetree, linux-kernel, linux-arm-kernel, upstream On Fri, Sep 01, 2023 at 11:26:17AM +0200, Yannic Moog wrote: > phyGATE-Tauri uses a phyCORE-i.MX8MM SoM. Add device tree for the board. > > Signed-off-by: Yannic Moog <y.moog@phytec.de> > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > .../boot/dts/freescale/imx8mm-phygate-tauri-l.dts | 488 +++++++++++++++++++++ > 2 files changed, 489 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index a750be13ace8..68e5a878e359 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts > new file mode 100644 > index 000000000000..457b23aa57fd > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts > @@ -0,0 +1,488 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2023 PHYTEC Messtechnik GmbH > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/leds/common.h> > +#include "imx8mm-phycore-som.dtsi" > + > +/ { > + model = "PHYTEC phyGATE-Tauri-L-iMX8MM"; > + compatible = "phytec,imx8mm-phygate-tauri-l", > + "phytec,imx8mm-phycore-som", "fsl,imx8mm"; > + > + chosen { > + stdout-path = &uart3; > + }; > + > + can_osc_40m: can-clock { Can we name the code clock-can? > + compatible = "fixed-clock"; > + clock-frequency = <40000000>; > + clock-output-names = "can_osc_40m"; > + #clock-cells = <0>; > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_gpiokeys>; > + > + key { > + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; > + label = "KEY-A"; > + linux,code = <30>; Can we use the constant defined in include/dt-bindings/input/linux-event-codes.h? > + }; > + }; > + > + leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_leds>; > + > + led-1 { > + color = <LED_COLOR_ID_RED>; > + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "none"; > + }; > + > + led-2 { > + color = <LED_COLOR_ID_YELLOW>; > + gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "none"; > + }; > + }; > + > + usdhc1_pwrseq: pwr-seq { > + compatible = "mmc-pwrseq-simple"; > + post-power-on-delay-ms = <100>; > + power-off-delay-us = <60>; > + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; > + }; > + > + reg_usb_hub_vbus: regulator-hub-otg1 { > + compatible = "regulator-fixed"; > + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usbhubpwr>; > + regulator-name = "usb_hub_vbus"; > + regulator-max-microvolt = <5000000>; > + regulator-min-microvolt = <5000000>; > + }; > + > + reg_usb_otg1_vbus: regulator-usb-otg1 { > + compatible = "regulator-fixed"; > + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usbotg1pwr>; > + regulator-name = "usb_otg1_vbus"; > + regulator-max-microvolt = <5000000>; > + regulator-min-microvolt = <5000000>; > + }; > + > + reg_usdhc2_vmmc: regulator-usdhc2 { > + compatible = "regulator-fixed"; > + enable-active-high; Can we move it after 'gpio' property? > + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > + off-on-delay-us = <20000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <3300000>; > + regulator-name = "VSD_3V3"; > + }; > +}; > + > +&ecspi1 { > + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, > + <&gpio5 13 GPIO_ACTIVE_LOW>, > + <&gpio5 2 GPIO_ACTIVE_LOW>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "okay"; > + > + /* CAN MCP251XFD */ > + can0: can@0 { > + compatible = "microchip,mcp251xfd"; > + clocks = <&can_osc_40m>; > + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; > + interrupt-parent = <&gpio1>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_can_int>; > + reg = <0>; We usually put 'reg' right after 'compatible'. Shawn > + spi-max-frequency = <10000000>; > + }; > + > + tpm: tpm@1 { > + compatible = "tcg,tpm_tis-spi"; > + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; > + interrupt-parent = <&gpio2>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_tpm>; > + reg = <1>; > + spi-max-frequency = <38000000>; > + }; > +}; > + > +&i2c2 { > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c2>; > + pinctrl-1 = <&pinctrl_i2c2_gpio>; > + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + status = "okay"; > + > + temp_sense0: temperature-sensor@49 { > + compatible = "ti,tmp102"; > + reg = <0x49>; > + interrupt-parent = <&gpio4>; > + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_tempsense>; > + #thermal-sensor-cells = <1>; > + }; > +}; > + > +&i2c3 { > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c3>; > + pinctrl-1 = <&pinctrl_i2c3_gpio>; > + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + status = "okay"; > +}; > + > +&i2c4 { > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c4>; > + pinctrl-1 = <&pinctrl_i2c4_gpio>; > + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + status = "okay"; > +}; > + > +/* PCIe */ > +&pcie0 { > + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, > + <&clk IMX8MM_CLK_PCIE1_PHY>, > + <&clk IMX8MM_CLK_PCIE1_CTRL>; > + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, > + <&clk IMX8MM_SYS_PLL2_100M>, > + <&clk IMX8MM_SYS_PLL2_250M>; > + assigned-clock-rates = <10000000>, <100000000>, <250000000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie>; > + reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; > + status = "okay"; > +}; > + > +&pwm1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm1>; > + status = "okay"; > +}; > + > +&pwm3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm3>; > + status = "okay"; > +}; > + > +&pwm4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm4>; > + status = "okay"; > +}; > + > +/* RTC */ > +&rv3028 { > + trickle-resistor-ohms = <3000>; > +}; > + > +&uart1 { > + assigned-clocks = <&clk IMX8MM_CLK_UART1>; > + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + status = "okay"; > +}; > + > +/* UART2 - RS232 */ > +&uart2 { > + assigned-clocks = <&clk IMX8MM_CLK_UART2>; > + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart2>; > + status = "okay"; > +}; > + > +/* UART - console */ > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart3>; > + status = "okay"; > +}; > + > +/* USB */ > +&usbotg1 { > + adp-disable; > + dr_mode = "otg"; > + over-current-active-low; > + samsung,picophy-pre-emp-curr-control = <3>; > + samsung,picophy-dc-vol-level-adjust = <7>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usbotg1>; > + srp-disable; > + vbus-supply = <®_usb_otg1_vbus>; > + status = "okay"; > +}; > + > +&usbotg2 { > + disable-over-current; > + dr_mode = "host"; > + samsung,picophy-pre-emp-curr-control = <3>; > + samsung,picophy-dc-vol-level-adjust = <7>; > + vbus-supply = <®_usb_hub_vbus>; > + status = "okay"; > +}; > + > +/* SD-Card */ > +&usdhc2 { > + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; > + assigned-clock-rates = <200000000>; > + bus-width = <4>; > + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; > + disable-wp; > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; > + vmmc-supply = <®_usdhc2_vmmc>; > + vqmmc-supply = <®_nvcc_sd2>; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_can_int: can-intgrp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 > + >; > + }; > + > + pinctrl_ecspi1: ecspi1grp { > + fsl,pins = < > + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 > + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 > + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 > + >; > + }; > + > + pinctrl_ecspi1_cs: ecspi1csgrp { > + fsl,pins = < > + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 > + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00 > + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00 > + >; > + }; > + > + pinctrl_gpiokeys: keygrp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 > + >; > + }; > + > + pinctrl_i2c2: i2c2grp { > + fsl,pins = < > + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 > + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 > + >; > + }; > + > + pinctrl_i2c2_gpio: i2c2gpiogrp { > + fsl,pins = < > + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0 > + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0 > + >; > + }; > + > + > + pinctrl_i2c3: i2c3grp { > + fsl,pins = < > + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 > + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 > + >; > + }; > + > + pinctrl_i2c3_gpio: i2c3gpiogrp { > + fsl,pins = < > + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0 > + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0 > + >; > + }; > + > + pinctrl_i2c4: i2c4grp { > + fsl,pins = < > + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 > + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 > + >; > + }; > + > + pinctrl_i2c4_gpio: i2c4gpiogrp { > + fsl,pins = < > + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0 > + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0 > + >; > + }; > + > + pinctrl_leds: leds1grp { > + fsl,pins = < > + MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00 > + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00 > + >; > + }; > + > + pinctrl_pcie: pciegrp { > + fsl,pins = < > + /* COEX2 */ > + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00 > + /* COEX1 */ > + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 > + >; > + }; > + > + pinctrl_pwm1: pwm1grp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40 > + >; > + }; > + > + pinctrl_pwm3: pwm3grp { > + fsl,pins = < > + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40 > + >; > + }; > + > + pinctrl_pwm4: pwm4grp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40 > + >; > + }; > + > + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { > + fsl,pins = < > + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 > + >; > + }; > + > + pinctrl_tempsense: tempsensegrp { > + fsl,pins = < > + MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00 > + >; > + }; > + > + pinctrl_tpm: tpmgrp { > + fsl,pins = < > + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 > + >; > + }; > + > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00 > + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00 > + >; > + }; > + > + pinctrl_uart2: uart2grp { > + fsl,pins = < > + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 > + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 > + >; > + }; > + > + pinctrl_uart3: uart3grp { > + fsl,pins = < > + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 > + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 > + >; > + }; > + > + pinctrl_usbhubpwr: usbhubpwrgrp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00 > + >; > + }; > + > + pinctrl_usbotg1pwr: usbotg1pwrgrp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 > + >; > + }; > + > + pinctrl_usbotg1: usbotg1grp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 > + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 > + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 > + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 > + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 > + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 > + >; > + }; > + > + pinctrl_usdhc2_gpio: usdhc2gpiogrp { > + fsl,pins = < > + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 > + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 > + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 > + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 > + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 > + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 > + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 > + >; > + }; > + > + pinctrl_usdhc2_100mhz: usdhc2100mhzgrp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 > + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 > + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 > + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 > + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 > + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 > + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 > + >; > + }; > + > + pinctrl_usdhc2_200mhz: usdhc2200mhzgrp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 > + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 > + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 > + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 > + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 > + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 > + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 > + >; > + }; > +}; > > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] arm64: dts: freescale: add phyGATE-Tauri i.MX 8M Mini Support 2023-09-25 1:26 ` Shawn Guo @ 2023-09-25 6:57 ` Yannic Moog 0 siblings, 0 replies; 6+ messages in thread From: Yannic Moog @ 2023-09-25 6:57 UTC (permalink / raw) To: shawnguo@kernel.org Cc: upstream@lists.phytec.de, linux-imx@nxp.com, leoyang.li@nxp.com, s.hauer@pengutronix.de, kernel@pengutronix.de, devicetree@vger.kernel.org, festevam@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org Hello Shawn, On Mon, 2023-09-25 at 09:26 +0800, Shawn Guo wrote: > On Fri, Sep 01, 2023 at 11:26:17AM +0200, Yannic Moog wrote: > > phyGATE-Tauri uses a phyCORE-i.MX8MM SoM. Add device tree for the > > board. > > > > Signed-off-by: Yannic Moog <y.moog@phytec.de> > > --- > > arch/arm64/boot/dts/freescale/Makefile | 1 + > > .../boot/dts/freescale/imx8mm-phygate-tauri-l.dts | 488 > > +++++++++++++++++++++ > > 2 files changed, 489 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/Makefile > > b/arch/arm64/boot/dts/freescale/Makefile > > index a750be13ace8..68e5a878e359 100644 > > --- a/arch/arm64/boot/dts/freescale/Makefile > > +++ b/arch/arm64/boot/dts/freescale/Makefile > > @@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb > > +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri- > > l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts > > new file mode 100644 > > index 000000000000..457b23aa57fd > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts > > @@ -0,0 +1,488 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2023 PHYTEC Messtechnik GmbH > > + */ > > + > > +/dts-v1/; > > + > > +#include <dt-bindings/leds/common.h> > > +#include "imx8mm-phycore-som.dtsi" > > + > > +/ { > > + model = "PHYTEC phyGATE-Tauri-L-iMX8MM"; > > + compatible = "phytec,imx8mm-phygate-tauri-l", > > + "phytec,imx8mm-phycore-som", "fsl,imx8mm"; > > + > > + chosen { > > + stdout-path = &uart3; > > + }; > > + > > + can_osc_40m: can-clock { > > Can we name the code clock-can? > > > + compatible = "fixed-clock"; > > + clock-frequency = <40000000>; > > + clock-output-names = "can_osc_40m"; > > + #clock-cells = <0>; > > + }; > > + > > + gpio-keys { > > + compatible = "gpio-keys"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_gpiokeys>; > > + > > + key { > > + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; > > + label = "KEY-A"; > > + linux,code = <30>; > > Can we use the constant defined in > include/dt-bindings/input/linux-event-codes.h? > > > + }; > > + }; > > + > > + leds { > > + compatible = "gpio-leds"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_leds>; > > + > > + led-1 { > > + color = <LED_COLOR_ID_RED>; > > + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; > > + linux,default-trigger = "none"; > > + }; > > + > > + led-2 { > > + color = <LED_COLOR_ID_YELLOW>; > > + gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; > > + linux,default-trigger = "none"; > > + }; > > + }; > > + > > + usdhc1_pwrseq: pwr-seq { > > + compatible = "mmc-pwrseq-simple"; > > + post-power-on-delay-ms = <100>; > > + power-off-delay-us = <60>; > > + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; > > + }; > > + > > + reg_usb_hub_vbus: regulator-hub-otg1 { > > + compatible = "regulator-fixed"; > > + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usbhubpwr>; > > + regulator-name = "usb_hub_vbus"; > > + regulator-max-microvolt = <5000000>; > > + regulator-min-microvolt = <5000000>; > > + }; > > + > > + reg_usb_otg1_vbus: regulator-usb-otg1 { > > + compatible = "regulator-fixed"; > > + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usbotg1pwr>; > > + regulator-name = "usb_otg1_vbus"; > > + regulator-max-microvolt = <5000000>; > > + regulator-min-microvolt = <5000000>; > > + }; > > + > > + reg_usdhc2_vmmc: regulator-usdhc2 { > > + compatible = "regulator-fixed"; > > + enable-active-high; > > Can we move it after 'gpio' property? > > > + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > > + off-on-delay-us = <20000>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; > > + regulator-max-microvolt = <3300000>; > > + regulator-min-microvolt = <3300000>; > > + regulator-name = "VSD_3V3"; > > + }; > > +}; > > + > > +&ecspi1 { > > + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, > > + <&gpio5 13 GPIO_ACTIVE_LOW>, > > + <&gpio5 2 GPIO_ACTIVE_LOW>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + status = "okay"; > > + > > + /* CAN MCP251XFD */ > > + can0: can@0 { > > + compatible = "microchip,mcp251xfd"; > > + clocks = <&can_osc_40m>; > > + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; > > + interrupt-parent = <&gpio1>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_can_int>; > > + reg = <0>; > > We usually put 'reg' right after 'compatible'. Thanks for pointing these things out, will send an updated version. Yannic > > Shawn [snip] ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-09-25 6:57 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-09-01 9:26 [PATCH 0/2] Add support for the phyGATE-Tauri-L IoT Gateway Yannic Moog 2023-09-01 9:26 ` [PATCH 1/2] dt-bindings: arm: fsl: add phyGATE-Tauri-L board Yannic Moog 2023-09-01 15:39 ` Conor Dooley 2023-09-01 9:26 ` [PATCH 2/2] arm64: dts: freescale: add phyGATE-Tauri i.MX 8M Mini Support Yannic Moog 2023-09-25 1:26 ` Shawn Guo 2023-09-25 6:57 ` Yannic Moog
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