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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id b17-20020a5d4d91000000b0031c855d52efsm17509312wru.87.2023.09.20.00.44.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 00:44:31 -0700 (PDT) Date: Wed, 20 Sep 2023 09:44:30 +0200 From: Andrew Jones To: Anup Patel Cc: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH 2/7] RISC-V: Detect Zicond from ISA string Message-ID: <20230920-36a5645f766ed9cce75a9e8c@orel> References: <20230919035343.1399389-1-apatel@ventanamicro.com> <20230919035343.1399389-3-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230919035343.1399389-3-apatel@ventanamicro.com> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net On Tue, Sep 19, 2023 at 09:23:38AM +0530, Anup Patel wrote: > The RISC-V integer conditional (Zicond) operation extension defines > standard conditional arithmetic and conditional-select/move operations > which are inspired from the XVentanaCondOps extension. In fact, QEMU > RISC-V also has support for emulating Zicond extension. > > Let us detect Zicond extension from ISA string available through > DT or ACPI. > > Signed-off-by: Anup Patel > --- > Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 3 files changed, 8 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index cad8ef68eca7..7ea90e2dbc5b 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -225,6 +225,12 @@ properties: > ratified in the 20191213 version of the unprivileged ISA > specification. > > + - const: zicond > + description: > + The standard Zicond extension for conditional arithmetic and > + conditional-select/move operations as ratified in commit 8fb6694 > + ("Update Gemfile") of riscv-zicond. As of yesterday, v1.0 of the spec points at commit 95cf1f9 ("Add changes requested by Ved during signoff") > + > - const: zicsr > description: | > The standard Zicsr extension for control and status register > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index b7efe9e2fa89..15bafc02ffd4 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -60,6 +60,7 @@ > #define RISCV_ISA_EXT_ZIHPM 42 > #define RISCV_ISA_EXT_SMSTATEEN 43 > #define RISCV_ISA_EXT_XVENTANACONDOPS 44 > +#define RISCV_ISA_EXT_ZICOND 45 > > #define RISCV_ISA_EXT_MAX 64 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 3a31d34fe709..49b6551f3347 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -174,6 +174,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), > __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), > + __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), Zi extensions come before Zb extensions. > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > -- > 2.34.1 > Thanks, drew