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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id j5-20020a5d6045000000b0032008f99216sm10914828wrt.96.2023.09.20.00.46.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 00:46:03 -0700 (PDT) Date: Wed, 20 Sep 2023 09:46:02 +0200 From: Andrew Jones To: Anup Patel Cc: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH 3/7] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM Message-ID: <20230920-64bd7206b92e056d76cd9715@orel> References: <20230919035343.1399389-1-apatel@ventanamicro.com> <20230919035343.1399389-4-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230919035343.1399389-4-apatel@ventanamicro.com> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net On Tue, Sep 19, 2023 at 09:23:39AM +0530, Anup Patel wrote: > We extend the KVM ISA extension ONE_REG interface to allow KVM > user space to detect and enable XVentanaCondOps extension for > Guest/VM. > > Signed-off-by: Anup Patel > --- > arch/riscv/include/uapi/asm/kvm.h | 1 + > arch/riscv/kvm/vcpu_onereg.c | 2 ++ > 2 files changed, 3 insertions(+) > > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h > index b1baf6f096a3..e030c12c7dfc 100644 > --- a/arch/riscv/include/uapi/asm/kvm.h > +++ b/arch/riscv/include/uapi/asm/kvm.h > @@ -138,6 +138,7 @@ enum KVM_RISCV_ISA_EXT_ID { > KVM_RISCV_ISA_EXT_ZIFENCEI, > KVM_RISCV_ISA_EXT_ZIHPM, > KVM_RISCV_ISA_EXT_SMSTATEEN, > + KVM_RISCV_ISA_EXT_XVENTANACONDOPS, > KVM_RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c > index 388599fcf684..17a847a1114b 100644 > --- a/arch/riscv/kvm/vcpu_onereg.c > +++ b/arch/riscv/kvm/vcpu_onereg.c > @@ -40,6 +40,7 @@ static const unsigned long kvm_isa_ext_arr[] = { > KVM_ISA_EXT_ARR(SVINVAL), > KVM_ISA_EXT_ARR(SVNAPOT), > KVM_ISA_EXT_ARR(SVPBMT), > + KVM_ISA_EXT_ARR(XVENTANACONDOPS), > KVM_ISA_EXT_ARR(ZBA), > KVM_ISA_EXT_ARR(ZBB), > KVM_ISA_EXT_ARR(ZBS), > @@ -89,6 +90,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) > case KVM_RISCV_ISA_EXT_SSTC: > case KVM_RISCV_ISA_EXT_SVINVAL: > case KVM_RISCV_ISA_EXT_SVNAPOT: > + case KVM_RISCV_ISA_EXT_XVENTANACONDOPS: > case KVM_RISCV_ISA_EXT_ZBA: > case KVM_RISCV_ISA_EXT_ZBB: > case KVM_RISCV_ISA_EXT_ZBS: > -- > 2.34.1 > Reviewed-by: Andrew Jones