From: Andrew Jones <ajones@ventanamicro.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Conor Dooley <conor@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Shuah Khan <shuah@kernel.org>,
Mayuresh Chitale <mchitale@ventanamicro.com>,
devicetree@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org
Subject: Re: [PATCH 4/7] RISC-V: KVM: Allow Zicond extension for Guest/VM
Date: Wed, 20 Sep 2023 09:46:53 +0200 [thread overview]
Message-ID: <20230920-be44cc5bd0f749a1137d103c@orel> (raw)
In-Reply-To: <20230919035343.1399389-5-apatel@ventanamicro.com>
On Tue, Sep 19, 2023 at 09:23:40AM +0530, Anup Patel wrote:
> We extend the KVM ISA extension ONE_REG interface to allow KVM
> user space to detect and enable Zicond extension for Guest/VM.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/vcpu_onereg.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index e030c12c7dfc..35ceb38a4eff 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -139,6 +139,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_ZIHPM,
> KVM_RISCV_ISA_EXT_SMSTATEEN,
> KVM_RISCV_ISA_EXT_XVENTANACONDOPS,
> + KVM_RISCV_ISA_EXT_ZICOND,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index 17a847a1114b..d3ca4969c985 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -47,6 +47,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> KVM_ISA_EXT_ARR(ZICBOM),
> KVM_ISA_EXT_ARR(ZICBOZ),
> KVM_ISA_EXT_ARR(ZICNTR),
> + KVM_ISA_EXT_ARR(ZICOND),
> KVM_ISA_EXT_ARR(ZICSR),
> KVM_ISA_EXT_ARR(ZIFENCEI),
> KVM_ISA_EXT_ARR(ZIHINTPAUSE),
> @@ -95,6 +96,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
> case KVM_RISCV_ISA_EXT_ZBB:
> case KVM_RISCV_ISA_EXT_ZBS:
> case KVM_RISCV_ISA_EXT_ZICNTR:
> + case KVM_RISCV_ISA_EXT_ZICOND:
> case KVM_RISCV_ISA_EXT_ZICSR:
> case KVM_RISCV_ISA_EXT_ZIFENCEI:
> case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-09-20 7:47 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-19 3:53 [PATCH 0/7] KVM RISC-V Conditional Operations Anup Patel
2023-09-19 3:53 ` [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string Anup Patel
2023-09-19 7:26 ` Conor Dooley
2023-09-25 13:30 ` Anup Patel
2023-09-20 7:38 ` Andrew Jones
2023-10-02 6:27 ` Christoph Hellwig
2023-10-02 15:36 ` Anup Patel
2023-10-05 6:49 ` Christoph Hellwig
2023-09-19 3:53 ` [PATCH 2/7] RISC-V: Detect Zicond " Anup Patel
2023-09-19 7:27 ` Conor Dooley
2023-09-25 13:31 ` Anup Patel
2023-09-20 7:44 ` Andrew Jones
2023-09-25 13:31 ` Anup Patel
2023-09-19 3:53 ` [PATCH 3/7] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM Anup Patel
2023-09-20 7:46 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 4/7] RISC-V: KVM: Allow Zicond " Anup Patel
2023-09-20 7:46 ` Andrew Jones [this message]
2023-09-19 3:53 ` [PATCH 5/7] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Anup Patel
2023-09-20 7:50 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 6/7] KVM: riscv: selftests: Add smstateen registers " Anup Patel
2023-09-20 8:13 ` Andrew Jones
2023-09-19 3:53 ` [PATCH 7/7] KVM: riscv: selftests: Add condops extensions " Anup Patel
2023-09-20 8:18 ` Andrew Jones
2023-09-25 13:32 ` Anup Patel
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