[PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support

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* [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support
@ 2023-09-20  6:33 Chen Wang
  2023-09-20  6:34 ` [PATCH v2 01/11] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
                   ` (12 more replies)
  0 siblings, 13 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-20  6:33 UTC (permalink / raw)
  To: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang

Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
in a standard mATX form factor. Add minimal device
tree files for the SG2042 SOC and the Milk-V Pioneer board.

Now only support basic uart drivers to boot up into a basic console.

Thanks,
Chen

---

Changes in v2:
  The patch series is based on v6.6-rc1. You can simply review or test 
  the patches at the link [4].
  - Improve format for comment of commitments as per input from last review.
  - Improve format of DTS as per input from last review.
  - Remove numa related stuff from DTS. This part is just for optimization, may
    add it later if really needed. 

Previous versions:
v1: due to it is not sent in thread, I have listed permlinks of the patchset
    [v1-0/12] ~ [v1-12/12] here for quick reference. You can simply review or
    test the patches at the link [3].

[1]: https://milkv.io/pioneer
[2]: https://en.sophgo.com/product/introduce/sg2042.html
[3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
[4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
[v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
[v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
[v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
[v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
[v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
[v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
[v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
[v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
[v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
[v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
[v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
[v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
[v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/

---

Chen Wang (8):
  riscv: Add SOPHGO SOC family Kconfig support
  dt-bindings: vendor-prefixes: add milkv/sophgo
  dt-bindings: riscv: add sophgo sg2042 bindings
  dt-bindings: riscv: Add T-HEAD C920 compatibles
  dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC
  riscv: dts: add initial SOPHGO SG2042 SoC device tree
  riscv: dts: sophgo: add Milk-V Pioneer board device tree
  riscv: defconfig: enable SOPHGO SoC

Emil Renner Berthing (2):
  dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts
  serial: 8250_dw: Add Sophgo SG2042 support

Inochi Amaoto (1):
  dt-bindings: timer: Add Sophgo sg2042 clint

 .../sifive,plic-1.0.0.yaml                    |    1 +
 .../devicetree/bindings/riscv/cpus.yaml       |    1 +
 .../devicetree/bindings/riscv/sophgo.yaml     |   28 +
 .../bindings/serial/snps-dw-apb-uart.yaml     |    1 +
 .../bindings/timer/sifive,clint.yaml          |    8 +
 .../devicetree/bindings/vendor-prefixes.yaml  |    4 +
 MAINTAINERS                                   |    7 +
 arch/riscv/Kconfig.socs                       |    5 +
 arch/riscv/boot/dts/Makefile                  |    1 +
 arch/riscv/boot/dts/sophgo/Makefile           |    3 +
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi   | 1744 +++++++++++++++++
 .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |   19 +
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  439 +++++
 arch/riscv/configs/defconfig                  |    1 +
 drivers/tty/serial/8250/8250_dw.c             |    5 +-
 15 files changed, 2265 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
 create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi


base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
-- 
2.25.1


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCH v2 01/11] riscv: Add SOPHGO SOC family Kconfig support
  2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
@ 2023-09-20  6:34 ` Chen Wang
  2023-09-20  7:34   ` Guo Ren
  2023-09-20  8:21   ` Conor Dooley
  2023-09-20  6:37 ` [PATCH v2 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo Chen Wang
                   ` (11 subsequent siblings)
  12 siblings, 2 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-20  6:34 UTC (permalink / raw)
  To: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang

The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
cores.

Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---
 arch/riscv/Kconfig.socs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 6833d01e2e70..d4df7b5d0f16 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -22,6 +22,11 @@ config SOC_SIFIVE
 	help
 	  This enables support for SiFive SoC platform hardware.
 
+config ARCH_SOPHGO
+	bool "Sophgo SoCs"
+	help
+	  This enables support for Sophgo SoC platform hardware.
+
 config ARCH_STARFIVE
 	def_bool SOC_STARFIVE
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 01/11] riscv: Add SOPHGO SOC family Kconfig support
  2023-09-20  6:34 ` [PATCH v2 01/11] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
@ 2023-09-20  7:34   ` Guo Ren
  2023-09-20  8:21   ` Conor Dooley
  1 sibling, 0 replies; 67+ messages in thread
From: Guo Ren @ 2023-09-20  7:34 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

On Wed, Sep 20, 2023 at 2:35 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
> cores.
>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  arch/riscv/Kconfig.socs | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 6833d01e2e70..d4df7b5d0f16 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -22,6 +22,11 @@ config SOC_SIFIVE
>         help
>           This enables support for SiFive SoC platform hardware.
>
> +config ARCH_SOPHGO
> +       bool "Sophgo SoCs"
> +       help
> +         This enables support for Sophgo SoC platform hardware.
> +
Reviewed-by: Guo Ren <guoren@kernel.org>

>  config ARCH_STARFIVE
>         def_bool SOC_STARFIVE
>
> --
> 2.25.1
>


-- 
Best Regards
 Guo Ren

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 01/11] riscv: Add SOPHGO SOC family Kconfig support
  2023-09-20  6:34 ` [PATCH v2 01/11] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
  2023-09-20  7:34   ` Guo Ren
@ 2023-09-20  8:21   ` Conor Dooley
  1 sibling, 0 replies; 67+ messages in thread
From: Conor Dooley @ 2023-09-20  8:21 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>


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^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCH v2 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo
  2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
  2023-09-20  6:34 ` [PATCH v2 01/11] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
@ 2023-09-20  6:37 ` Chen Wang
  2023-09-20  7:38   ` Guo Ren
  2023-09-20  8:22   ` Conor Dooley
  2023-09-20  6:37 ` [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings Chen Wang
                   ` (10 subsequent siblings)
  12 siblings, 2 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-20  6:37 UTC (permalink / raw)
  To: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang

Add new vendor strings to dt bindings.
These new vendor strings are used by
- Sophgo SG2042 SoC [1]
- Milk-V Pioneer board [2], which uses SG2042 chip.

[1]: https://en.sophgo.com/product/introduce/sg2042.html
[2]: https://milkv.io/pioneer

Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 573578db9509..fcca9e070a9a 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -863,6 +863,8 @@ patternProperties:
     description: MikroElektronika d.o.o.
   "^mikrotik,.*":
     description: MikroTik
+  "^milkv,.*":
+    description: MilkV Technology Co., Ltd
   "^miniand,.*":
     description: Miniand Tech
   "^minix,.*":
@@ -1273,6 +1275,8 @@ patternProperties:
     description: Solomon Systech Limited
   "^sony,.*":
     description: Sony Corporation
+  "^sophgo,.*":
+    description: Sophgo Technology Inc.
   "^sourceparts,.*":
     description: Source Parts Inc.
   "^spansion,.*":
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo
  2023-09-20  6:37 ` [PATCH v2 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo Chen Wang
@ 2023-09-20  7:38   ` Guo Ren
  2023-09-20  8:22   ` Conor Dooley
  1 sibling, 0 replies; 67+ messages in thread
From: Guo Ren @ 2023-09-20  7:38 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

On Wed, Sep 20, 2023 at 2:37 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> Add new vendor strings to dt bindings.
> These new vendor strings are used by
> - Sophgo SG2042 SoC [1]
> - Milk-V Pioneer board [2], which uses SG2042 chip.
>
> [1]: https://en.sophgo.com/product/introduce/sg2042.html
> [2]: https://milkv.io/pioneer
>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 573578db9509..fcca9e070a9a 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -863,6 +863,8 @@ patternProperties:
>      description: MikroElektronika d.o.o.
>    "^mikrotik,.*":
>      description: MikroTik
> +  "^milkv,.*":
> +    description: MilkV Technology Co., Ltd
>    "^miniand,.*":
>      description: Miniand Tech
>    "^minix,.*":
> @@ -1273,6 +1275,8 @@ patternProperties:
>      description: Solomon Systech Limited
>    "^sony,.*":
>      description: Sony Corporation
> +  "^sophgo,.*":
> +    description: Sophgo Technology Inc.
>    "^sourceparts,.*":
>      description: Source Parts Inc.
>    "^spansion,.*":
> --
> 2.25.1
>
Reviewed-by: Guo Ren <guoren@kernel.org>

-- 
Best Regards
 Guo Ren

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo
  2023-09-20  6:37 ` [PATCH v2 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo Chen Wang
  2023-09-20  7:38   ` Guo Ren
@ 2023-09-20  8:22   ` Conor Dooley
  2023-09-20  9:14     ` Chen Wang
  1 sibling, 1 reply; 67+ messages in thread
From: Conor Dooley @ 2023-09-20  8:22 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

[-- Attachment #1: Type: text/plain, Size: 1581 bytes --]

Yo,

On Wed, Sep 20, 2023 at 02:37:28PM +0800, Chen Wang wrote:
> Add new vendor strings to dt bindings.
> These new vendor strings are used by
> - Sophgo SG2042 SoC [1]
> - Milk-V Pioneer board [2], which uses SG2042 chip.
> 
> [1]: https://en.sophgo.com/product/introduce/sg2042.html
> [2]: https://milkv.io/pioneer

If you resend, make these link tags please. Otherwise,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 573578db9509..fcca9e070a9a 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -863,6 +863,8 @@ patternProperties:
>      description: MikroElektronika d.o.o.
>    "^mikrotik,.*":
>      description: MikroTik
> +  "^milkv,.*":
> +    description: MilkV Technology Co., Ltd
>    "^miniand,.*":
>      description: Miniand Tech
>    "^minix,.*":
> @@ -1273,6 +1275,8 @@ patternProperties:
>      description: Solomon Systech Limited
>    "^sony,.*":
>      description: Sony Corporation
> +  "^sophgo,.*":
> +    description: Sophgo Technology Inc.
>    "^sourceparts,.*":
>      description: Source Parts Inc.
>    "^spansion,.*":
> -- 
> 2.25.1
> 

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^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo
  2023-09-20  8:22   ` Conor Dooley
@ 2023-09-20  9:14     ` Chen Wang
  0 siblings, 0 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-20  9:14 UTC (permalink / raw)
  To: Conor Dooley
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

Regards,

unicornx

Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 16:23写道：
>
> Yo,
>
> On Wed, Sep 20, 2023 at 02:37:28PM +0800, Chen Wang wrote:
> > Add new vendor strings to dt bindings.
> > These new vendor strings are used by
> > - Sophgo SG2042 SoC [1]
> > - Milk-V Pioneer board [2], which uses SG2042 chip.
> >
> > [1]: https://en.sophgo.com/product/introduce/sg2042.html
> > [2]: https://milkv.io/pioneer
>
> If you resend, make these link tags please. Otherwise,
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
Sure, I will correct them in next revision. Thanks.

> Thanks,
> Conor.
>
> > Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> > ---
> >  Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > index 573578db9509..fcca9e070a9a 100644
> > --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > @@ -863,6 +863,8 @@ patternProperties:
> >      description: MikroElektronika d.o.o.
> >    "^mikrotik,.*":
> >      description: MikroTik
> > +  "^milkv,.*":
> > +    description: MilkV Technology Co., Ltd
> >    "^miniand,.*":
> >      description: Miniand Tech
> >    "^minix,.*":
> > @@ -1273,6 +1275,8 @@ patternProperties:
> >      description: Solomon Systech Limited
> >    "^sony,.*":
> >      description: Sony Corporation
> > +  "^sophgo,.*":
> > +    description: Sophgo Technology Inc.
> >    "^sourceparts,.*":
> >      description: Source Parts Inc.
> >    "^spansion,.*":
> > --
> > 2.25.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
  2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
  2023-09-20  6:34 ` [PATCH v2 01/11] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
  2023-09-20  6:37 ` [PATCH v2 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo Chen Wang
@ 2023-09-20  6:37 ` Chen Wang
  2023-09-20  7:43   ` Guo Ren
                     ` (2 more replies)
  2023-09-20  6:38 ` [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles Chen Wang
                   ` (9 subsequent siblings)
  12 siblings, 3 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-20  6:37 UTC (permalink / raw)
  To: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang

Add DT binding documentation for the Sophgo SG2042 Soc [1] and the
Milk-V Pioneer board [2].

[1]: https://en.sophgo.com/product/introduce/sg2042.html
[2]: https://milkv.io/pioneer

Acked-by: Chao Wei <chao.wei@sophgo.com>
Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---
 .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
 MAINTAINERS                                   |  7 +++++
 2 files changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml

diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
new file mode 100644
index 000000000000..82468ae915db
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SoC-based boards
+
+maintainers:
+  - Chao Wei <chao.wei@sophgo.com>
+  - Xiaoguang Xing <xiaoguang.xing@sophgo.com>
+
+description:
+  Sophgo SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - milkv,pioneer
+          - const: sophgo,sg2042
+
+additionalProperties: true
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 90f13281d297..b74d505003e2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20063,6 +20063,13 @@ F:	drivers/char/sonypi.c
 F:	drivers/platform/x86/sony-laptop.c
 F:	include/linux/sony-laptop.h
 
+SOPHGO DEVICETREES
+M:	Xiaoguang Xing <xiaoguang.xing@sophgo.com>
+M:	Chao Wei <chao.wei@sophgo.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/riscv/sophgo.yaml
+F:	arch/riscv/boot/dts/sophgo/
+
 SOUND
 M:	Jaroslav Kysela <perex@perex.cz>
 M:	Takashi Iwai <tiwai@suse.com>
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
  2023-09-20  6:37 ` [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings Chen Wang
@ 2023-09-20  7:43   ` Guo Ren
  2023-09-20  8:28   ` Conor Dooley
  2023-09-20 11:55   ` Krzysztof Kozlowski
  2 siblings, 0 replies; 67+ messages in thread
From: Guo Ren @ 2023-09-20  7:43 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

On Wed, Sep 20, 2023 at 2:38 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> Add DT binding documentation for the Sophgo SG2042 Soc [1] and the
> Milk-V Pioneer board [2].
>
> [1]: https://en.sophgo.com/product/introduce/sg2042.html
> [2]: https://milkv.io/pioneer
>
> Acked-by: Chao Wei <chao.wei@sophgo.com>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
>  MAINTAINERS                                   |  7 +++++
>  2 files changed, 35 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
>
> diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> new file mode 100644
> index 000000000000..82468ae915db
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> @@ -0,0 +1,28 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sophgo SoC-based boards
> +
> +maintainers:
> +  - Chao Wei <chao.wei@sophgo.com>
> +  - Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> +
> +description:
> +  Sophgo SoC-based boards
> +
> +properties:
> +  $nodename:
> +    const: '/'
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - milkv,pioneer
> +          - const: sophgo,sg2042
> +
> +additionalProperties: true
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 90f13281d297..b74d505003e2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20063,6 +20063,13 @@ F:     drivers/char/sonypi.c
>  F:     drivers/platform/x86/sony-laptop.c
>  F:     include/linux/sony-laptop.h
>
> +SOPHGO DEVICETREES
> +M:     Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> +M:     Chao Wei <chao.wei@sophgo.com>
> +S:     Maintained
> +F:     Documentation/devicetree/bindings/riscv/sophgo.yaml
> +F:     arch/riscv/boot/dts/sophgo/
> +
>  SOUND
>  M:     Jaroslav Kysela <perex@perex.cz>
>  M:     Takashi Iwai <tiwai@suse.com>
> --
> 2.25.1
>
LGTM

Reviewed-by: Guo Ren <guoren@kernel.org>

-- 
Best Regards
 Guo Ren

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
  2023-09-20  6:37 ` [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings Chen Wang
  2023-09-20  7:43   ` Guo Ren
@ 2023-09-20  8:28   ` Conor Dooley
  2023-09-21 10:21     ` Chen Wang
  2023-09-22  1:48     ` Chen Wang
  2023-09-20 11:55   ` Krzysztof Kozlowski
  2 siblings, 2 replies; 67+ messages in thread
From: Conor Dooley @ 2023-09-20  8:28 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

[-- Attachment #1: Type: text/plain, Size: 2915 bytes --]

Yo,

On Wed, Sep 20, 2023 at 02:37:51PM +0800, Chen Wang wrote:
> Add DT binding documentation for the Sophgo SG2042 Soc [1] and the
> Milk-V Pioneer board [2].
> 
> [1]: https://en.sophgo.com/product/introduce/sg2042.html
> [2]: https://milkv.io/pioneer

Again, link tags please.

> Acked-by: Chao Wei <chao.wei@sophgo.com>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
>  MAINTAINERS                                   |  7 +++++
>  2 files changed, 35 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
> 
> diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> new file mode 100644
> index 000000000000..82468ae915db
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> @@ -0,0 +1,28 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sophgo SoC-based boards
> +
> +maintainers:
> +  - Chao Wei <chao.wei@sophgo.com>
> +  - Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> +
> +description:
> +  Sophgo SoC-based boards
> +
> +properties:
> +  $nodename:
> +    const: '/'
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - milkv,pioneer
> +          - const: sophgo,sg2042
> +
> +additionalProperties: true
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 90f13281d297..b74d505003e2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20063,6 +20063,13 @@ F:	drivers/char/sonypi.c
>  F:	drivers/platform/x86/sony-laptop.c
>  F:	include/linux/sony-laptop.h
>  
> +SOPHGO DEVICETREES
> +M:	Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> +M:	Chao Wei <chao.wei@sophgo.com>
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/riscv/sophgo.yaml

> +F:	arch/riscv/boot/dts/sophgo/

Firstly, this directory does not exist at the time of this patch, so it
should not be added here, but rather at the time that you create it.

Secondly, are Xiaoguang Xing and Chao Wei going to monitor the lists &
apply patches for these files? If so, you should add a git tree here
that they will apply patches to & add to linux-next. Also, I'd really
like to see some on-list signs of life from these people, otherwise
I'd rather see your name here instead of theirs.

If they don't intend reviewing/testing/applying patches, I can do it as
a last resort but I would rather that someone who specifically cares for
this hardware does it.

Thanks,
Conor.

> +
>  SOUND
>  M:	Jaroslav Kysela <perex@perex.cz>
>  M:	Takashi Iwai <tiwai@suse.com>
> -- 
> 2.25.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
  2023-09-20  8:28   ` Conor Dooley
@ 2023-09-21 10:21     ` Chen Wang
  2023-09-21 12:18       ` Conor Dooley
  2023-09-22  1:48     ` Chen Wang
  1 sibling, 1 reply; 67+ messages in thread
From: Chen Wang @ 2023-09-21 10:21 UTC (permalink / raw)
  To: Conor Dooley
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

Regards,

unicornx

Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 16:29写道：
>
> Yo,
>
> On Wed, Sep 20, 2023 at 02:37:51PM +0800, Chen Wang wrote:
> > Add DT binding documentation for the Sophgo SG2042 Soc [1] and the
> > Milk-V Pioneer board [2].
> >
> > [1]: https://en.sophgo.com/product/introduce/sg2042.html
> > [2]: https://milkv.io/pioneer
>
> Again, link tags please.
>
> > Acked-by: Chao Wei <chao.wei@sophgo.com>
> > Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> > ---
> >  .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
> >  MAINTAINERS                                   |  7 +++++
> >  2 files changed, 35 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> > new file mode 100644
> > index 000000000000..82468ae915db
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> > @@ -0,0 +1,28 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Sophgo SoC-based boards
> > +
> > +maintainers:
> > +  - Chao Wei <chao.wei@sophgo.com>
> > +  - Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > +
> > +description:
> > +  Sophgo SoC-based boards
> > +
> > +properties:
> > +  $nodename:
> > +    const: '/'
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - enum:
> > +              - milkv,pioneer
> > +          - const: sophgo,sg2042
> > +
> > +additionalProperties: true
> > +
> > +...
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 90f13281d297..b74d505003e2 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -20063,6 +20063,13 @@ F:   drivers/char/sonypi.c
> >  F:   drivers/platform/x86/sony-laptop.c
> >  F:   include/linux/sony-laptop.h
> >
> > +SOPHGO DEVICETREES
> > +M:   Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > +M:   Chao Wei <chao.wei@sophgo.com>
> > +S:   Maintained
> > +F:   Documentation/devicetree/bindings/riscv/sophgo.yaml
>
> > +F:   arch/riscv/boot/dts/sophgo/
>
> Firstly, this directory does not exist at the time of this patch, so it
> should not be added here, but rather at the time that you create it.
>
> Secondly, are Xiaoguang Xing and Chao Wei going to monitor the lists &
> apply patches for these files? If so, you should add a git tree here
> that they will apply patches to & add to linux-next. Also, I'd really
> like to see some on-list signs of life from these people, otherwise
> I'd rather see your name here instead of theirs.
>
> If they don't intend reviewing/testing/applying patches, I can do it as
> a last resort but I would rather that someone who specifically cares for
> this hardware does it.
>
> Thanks,
> Conor.
>

Hi, Conor:
Please allow me to explain first. As a community volunteer, I actually
had full discussions and testing with Sophgo people when submitting
patches, so I added tag such "Acked-by: Xiaoguang Xing ..." to the
signature part of most patches. Also if you think a formal email is
required, I will talk them to send it.

As for the issue of MAINTAINERS, I discussed it with the people from
Sophgo. They (including me also) feel that we are not very familiar
with the community process (especially as maintainer, and actually I
modify the file MAINTAINERS is just to suppress warning information
when running checkpatch.pl), so we sincerely hope to invite you, Mr.
Conor, to help us for a period of time on maintenance work, including
checking relevant patches, merging and submitting PRs, we will learn
together with you for a while, and then take over this part of the
work when we become familiar with it. We know that you are also very
busy at work, especially if you don't have the hardware at hand. I
have the hardware here and I can take the responsibility to run
testing. What do you think? I'm waiting for your reply. Thanks in
advance.

> > +
> >  SOUND
> >  M:   Jaroslav Kysela <perex@perex.cz>
> >  M:   Takashi Iwai <tiwai@suse.com>
> > --
> > 2.25.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
  2023-09-21 10:21     ` Chen Wang
@ 2023-09-21 12:18       ` Conor Dooley
  2023-09-21 13:40         ` Chen Wang
  2023-09-21 13:51         ` Chen Wang
  0 siblings, 2 replies; 67+ messages in thread
From: Conor Dooley @ 2023-09-21 12:18 UTC (permalink / raw)
  To: Chen Wang
  Cc: Conor Dooley, aou, chao.wei, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing,
	Chen Wang

[-- Attachment #1: Type: text/plain, Size: 4870 bytes --]

On Thu, Sep 21, 2023 at 06:21:08PM +0800, Chen Wang wrote:
> Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 16:29写道：
> > On Wed, Sep 20, 2023 at 02:37:51PM +0800, Chen Wang wrote:
> > > Add DT binding documentation for the Sophgo SG2042 Soc [1] and the
> > > Milk-V Pioneer board [2].
> > >
> > > [1]: https://en.sophgo.com/product/introduce/sg2042.html
> > > [2]: https://milkv.io/pioneer
> >
> > Again, link tags please.
> >
> > > Acked-by: Chao Wei <chao.wei@sophgo.com>
> > > Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > > Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> > > ---
> > >  .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
> > >  MAINTAINERS                                   |  7 +++++
> > >  2 files changed, 35 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> > > new file mode 100644
> > > index 000000000000..82468ae915db
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> > > @@ -0,0 +1,28 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Sophgo SoC-based boards
> > > +
> > > +maintainers:
> > > +  - Chao Wei <chao.wei@sophgo.com>
> > > +  - Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > > +
> > > +description:
> > > +  Sophgo SoC-based boards
> > > +
> > > +properties:
> > > +  $nodename:
> > > +    const: '/'
> > > +  compatible:
> > > +    oneOf:
> > > +      - items:
> > > +          - enum:
> > > +              - milkv,pioneer
> > > +          - const: sophgo,sg2042
> > > +
> > > +additionalProperties: true
> > > +
> > > +...
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index 90f13281d297..b74d505003e2 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -20063,6 +20063,13 @@ F:   drivers/char/sonypi.c
> > >  F:   drivers/platform/x86/sony-laptop.c
> > >  F:   include/linux/sony-laptop.h
> > >
> > > +SOPHGO DEVICETREES
> > > +M:   Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > > +M:   Chao Wei <chao.wei@sophgo.com>
> > > +S:   Maintained
> > > +F:   Documentation/devicetree/bindings/riscv/sophgo.yaml
> >
> > > +F:   arch/riscv/boot/dts/sophgo/
> >
> > Firstly, this directory does not exist at the time of this patch, so it
> > should not be added here, but rather at the time that you create it.
> >
> > Secondly, are Xiaoguang Xing and Chao Wei going to monitor the lists &
> > apply patches for these files? If so, you should add a git tree here
> > that they will apply patches to & add to linux-next. Also, I'd really
> > like to see some on-list signs of life from these people, otherwise
> > I'd rather see your name here instead of theirs.
> >
> > If they don't intend reviewing/testing/applying patches, I can do it as
> > a last resort but I would rather that someone who specifically cares for
> > this hardware does it.
> 
> Please allow me to explain first. As a community volunteer, I actually
> had full discussions and testing with Sophgo people when submitting
> patches, so I added tag such "Acked-by: Xiaoguang Xing ..." to the
> signature part of most patches. Also if you think a formal email is
> required, I will talk them to send it.

No, I'm okay with the acks that are on these patches. I just want to
make sure that those who are acking know why they are & am wondering why
your name is not there, seeing as you're the one who has submitted these
patches.

> As for the issue of MAINTAINERS, I discussed it with the people from
> Sophgo. They (including me also) feel that we are not very familiar
> with the community process (especially as maintainer, and actually I
> modify the file MAINTAINERS is just to suppress warning information
> when running checkpatch.pl), so we sincerely hope to invite you, Mr.
> Conor,

Oh god, there's no need to call me "Mr. Conor". Conor will do perfectly
fine!

> to help us for a period of time on maintenance work, including
> checking relevant patches, merging and submitting PRs, we will learn
> together with you for a while, and then take over this part of the
> work when we become familiar with it. We know that you are also very
> busy at work, especially if you don't have the hardware at hand. I
> have the hardware here and I can take the responsibility to run
> testing. What do you think? I'm waiting for your reply. Thanks in
> advance.

That seems fine to me. In that case, you should add yourself to the
MAINTAINERS entry.

Thanks,
Conor.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
  2023-09-21 12:18       ` Conor Dooley
@ 2023-09-21 13:40         ` Chen Wang
  2023-09-21 13:51         ` Chen Wang
  1 sibling, 0 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-21 13:40 UTC (permalink / raw)
  To: Conor Dooley
  Cc: Conor Dooley, aou, chao.wei, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing,
	Chen Wang

Regards,

unicornx

Conor Dooley <conor@kernel.org> 于2023年9月21日周四 20:18写道：
>
> On Thu, Sep 21, 2023 at 06:21:08PM +0800, Chen Wang wrote:
> > Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 16:29写道：
> > > On Wed, Sep 20, 2023 at 02:37:51PM +0800, Chen Wang wrote:
> > > > Add DT binding documentation for the Sophgo SG2042 Soc [1] and the
> > > > Milk-V Pioneer board [2].
> > > >
> > > > [1]: https://en.sophgo.com/product/introduce/sg2042.html
> > > > [2]: https://milkv.io/pioneer
> > >
> > > Again, link tags please.
> > >
> > > > Acked-by: Chao Wei <chao.wei@sophgo.com>
> > > > Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > > > Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> > > > ---
> > > >  .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
> > > >  MAINTAINERS                                   |  7 +++++
> > > >  2 files changed, 35 insertions(+)
> > > >  create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> > > > new file mode 100644
> > > > index 000000000000..82468ae915db
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> > > > @@ -0,0 +1,28 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Sophgo SoC-based boards
> > > > +
> > > > +maintainers:
> > > > +  - Chao Wei <chao.wei@sophgo.com>
> > > > +  - Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > > > +
> > > > +description:
> > > > +  Sophgo SoC-based boards
> > > > +
> > > > +properties:
> > > > +  $nodename:
> > > > +    const: '/'
> > > > +  compatible:
> > > > +    oneOf:
> > > > +      - items:
> > > > +          - enum:
> > > > +              - milkv,pioneer
> > > > +          - const: sophgo,sg2042
> > > > +
> > > > +additionalProperties: true
> > > > +
> > > > +...
> > > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > > index 90f13281d297..b74d505003e2 100644
> > > > --- a/MAINTAINERS
> > > > +++ b/MAINTAINERS
> > > > @@ -20063,6 +20063,13 @@ F:   drivers/char/sonypi.c
> > > >  F:   drivers/platform/x86/sony-laptop.c
> > > >  F:   include/linux/sony-laptop.h
> > > >
> > > > +SOPHGO DEVICETREES
> > > > +M:   Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > > > +M:   Chao Wei <chao.wei@sophgo.com>
> > > > +S:   Maintained
> > > > +F:   Documentation/devicetree/bindings/riscv/sophgo.yaml
> > >
> > > > +F:   arch/riscv/boot/dts/sophgo/
> > >
> > > Firstly, this directory does not exist at the time of this patch, so it
> > > should not be added here, but rather at the time that you create it.
> > >
> > > Secondly, are Xiaoguang Xing and Chao Wei going to monitor the lists &
> > > apply patches for these files? If so, you should add a git tree here
> > > that they will apply patches to & add to linux-next. Also, I'd really
> > > like to see some on-list signs of life from these people, otherwise
> > > I'd rather see your name here instead of theirs.
> > >
> > > If they don't intend reviewing/testing/applying patches, I can do it as
> > > a last resort but I would rather that someone who specifically cares for
> > > this hardware does it.
> >
> > Please allow me to explain first. As a community volunteer, I actually
> > had full discussions and testing with Sophgo people when submitting
> > patches, so I added tag such "Acked-by: Xiaoguang Xing ..." to the
> > signature part of most patches. Also if you think a formal email is
> > required, I will talk them to send it.
>
> No, I'm okay with the acks that are on these patches. I just want to
> make sure that those who are acking know why they are & am wondering why
> your name is not there, seeing as you're the one who has submitted these
> patches.
>
> > As for the issue of MAINTAINERS, I discussed it with the people from
> > Sophgo. They (including me also) feel that we are not very familiar
> > with the community process (especially as maintainer, and actually I
> > modify the file MAINTAINERS is just to suppress warning information
> > when running checkpatch.pl), so we sincerely hope to invite you, Mr.
> > Conor,
>
> Oh god, there's no need to call me "Mr. Conor". Conor will do perfectly
> fine!
>
> > to help us for a period of time on maintenance work, including
> > checking relevant patches, merging and submitting PRs, we will learn
> > together with you for a while, and then take over this part of the
> > work when we become familiar with it. We know that you are also very
> > busy at work, especially if you don't have the hardware at hand. I
> > have the hardware here and I can take the responsibility to run
> > testing. What do you think? I'm waiting for your reply. Thanks in
> > advance.
>
> That seems fine to me. In that case, you should add yourself to the
> MAINTAINERS entry.
>
> Thanks,
> Conor.

Okay，I will add it in next revision, thank you again.

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
  2023-09-21 12:18       ` Conor Dooley
  2023-09-21 13:40         ` Chen Wang
@ 2023-09-21 13:51         ` Chen Wang
  2023-09-21 14:00           ` Conor Dooley
  1 sibling, 1 reply; 67+ messages in thread
From: Chen Wang @ 2023-09-21 13:51 UTC (permalink / raw)
  To: Conor Dooley
  Cc: Conor Dooley, aou, chao.wei, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing,
	Chen Wang

Regards,

unicornx

Conor Dooley <conor@kernel.org> 于2023年9月21日周四 20:18写道：
>
> On Thu, Sep 21, 2023 at 06:21:08PM +0800, Chen Wang wrote:
> > Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 16:29写道：
> > > On Wed, Sep 20, 2023 at 02:37:51PM +0800, Chen Wang wrote:
> > > > Add DT binding documentation for the Sophgo SG2042 Soc [1] and the
> > > > Milk-V Pioneer board [2].
> > > >
> > > > [1]: https://en.sophgo.com/product/introduce/sg2042.html
> > > > [2]: https://milkv.io/pioneer
> > >
> > > Again, link tags please.
> > >
> > > > Acked-by: Chao Wei <chao.wei@sophgo.com>
> > > > Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > > > Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> > > > ---
> > > >  .../devicetree/bindings/riscv/sophgo.yaml     | 28 +++++++++++++++++++
> > > >  MAINTAINERS                                   |  7 +++++
> > > >  2 files changed, 35 insertions(+)
> > > >  create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> > > > new file mode 100644
> > > > index 000000000000..82468ae915db
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> > > > @@ -0,0 +1,28 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Sophgo SoC-based boards
> > > > +
> > > > +maintainers:
> > > > +  - Chao Wei <chao.wei@sophgo.com>
> > > > +  - Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > > > +
> > > > +description:
> > > > +  Sophgo SoC-based boards
> > > > +
> > > > +properties:
> > > > +  $nodename:
> > > > +    const: '/'
> > > > +  compatible:
> > > > +    oneOf:
> > > > +      - items:
> > > > +          - enum:
> > > > +              - milkv,pioneer
> > > > +          - const: sophgo,sg2042
> > > > +
> > > > +additionalProperties: true
> > > > +
> > > > +...
> > > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > > index 90f13281d297..b74d505003e2 100644
> > > > --- a/MAINTAINERS
> > > > +++ b/MAINTAINERS
> > > > @@ -20063,6 +20063,13 @@ F:   drivers/char/sonypi.c
> > > >  F:   drivers/platform/x86/sony-laptop.c
> > > >  F:   include/linux/sony-laptop.h
> > > >
> > > > +SOPHGO DEVICETREES
> > > > +M:   Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > > > +M:   Chao Wei <chao.wei@sophgo.com>
> > > > +S:   Maintained
> > > > +F:   Documentation/devicetree/bindings/riscv/sophgo.yaml
> > >
> > > > +F:   arch/riscv/boot/dts/sophgo/
> > >
> > > Firstly, this directory does not exist at the time of this patch, so it
> > > should not be added here, but rather at the time that you create it.
> > >
> > > Secondly, are Xiaoguang Xing and Chao Wei going to monitor the lists &
> > > apply patches for these files? If so, you should add a git tree here
> > > that they will apply patches to & add to linux-next. Also, I'd really
> > > like to see some on-list signs of life from these people, otherwise
> > > I'd rather see your name here instead of theirs.
> > >
> > > If they don't intend reviewing/testing/applying patches, I can do it as
> > > a last resort but I would rather that someone who specifically cares for
> > > this hardware does it.
> >
> > Please allow me to explain first. As a community volunteer, I actually
> > had full discussions and testing with Sophgo people when submitting
> > patches, so I added tag such "Acked-by: Xiaoguang Xing ..." to the
> > signature part of most patches. Also if you think a formal email is
> > required, I will talk them to send it.
>
> No, I'm okay with the acks that are on these patches. I just want to
> make sure that those who are acking know why they are & am wondering why
> your name is not there, seeing as you're the one who has submitted these
> patches.
>
> > As for the issue of MAINTAINERS, I discussed it with the people from
> > Sophgo. They (including me also) feel that we are not very familiar
> > with the community process (especially as maintainer, and actually I
> > modify the file MAINTAINERS is just to suppress warning information
> > when running checkpatch.pl), so we sincerely hope to invite you, Mr.
> > Conor,
>
> Oh god, there's no need to call me "Mr. Conor". Conor will do perfectly
> fine!
>
> > to help us for a period of time on maintenance work, including
> > checking relevant patches, merging and submitting PRs, we will learn
> > together with you for a while, and then take over this part of the
> > work when we become familiar with it. We know that you are also very
> > busy at work, especially if you don't have the hardware at hand. I
> > have the hardware here and I can take the responsibility to run
> > testing. What do you think? I'm waiting for your reply. Thanks in
> > advance.
>
> That seems fine to me. In that case, you should add yourself to the
> MAINTAINERS entry.
>
> Thanks,
> Conor.

Conor, do you want me to add you to the MAINTAINERS entry too?

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
  2023-09-21 13:51         ` Chen Wang
@ 2023-09-21 14:00           ` Conor Dooley
  0 siblings, 0 replies; 67+ messages in thread
From: Conor Dooley @ 2023-09-21 14:00 UTC (permalink / raw)
  To: Chen Wang
  Cc: Conor Dooley, aou, chao.wei, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing,
	Chen Wang

[-- Attachment #1: Type: text/plain, Size: 206 bytes --]

On Thu, Sep 21, 2023 at 09:51:58PM +0800, Chen Wang wrote:

> Conor, do you want me to add you to the MAINTAINERS entry too?

Nope, no need. My existing maintainers entries should cover it.

Thanks,
Conor.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
  2023-09-20  8:28   ` Conor Dooley
  2023-09-21 10:21     ` Chen Wang
@ 2023-09-22  1:48     ` Chen Wang
  1 sibling, 0 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-22  1:48 UTC (permalink / raw)
  To: Conor Dooley
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

Regards,

unicornx


> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 90f13281d297..b74d505003e2 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -20063,6 +20063,13 @@ F:   drivers/char/sonypi.c
> >  F:   drivers/platform/x86/sony-laptop.c
> >  F:   include/linux/sony-laptop.h
> >
> > +SOPHGO DEVICETREES
> > +M:   Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > +M:   Chao Wei <chao.wei@sophgo.com>
> > +S:   Maintained
> > +F:   Documentation/devicetree/bindings/riscv/sophgo.yaml
>
> > +F:   arch/riscv/boot/dts/sophgo/
>
> Firstly, this directory does not exist at the time of this patch, so it
> should not be added here, but rather at the time that you create it.
>
> Secondly, are Xiaoguang Xing and Chao Wei going to monitor the lists &
> apply patches for these files? If so, you should add a git tree here
> that they will apply patches to & add to linux-next. Also, I'd really

Conor, FYI, regarding "add a git tree here that they will apply
patches to & add to linux-next.", I will not add in this patchset. I
plan to add this when we start to take the maintainece work. Let me
know if any questions.

> like to see some on-list signs of life from these people, otherwise
> I'd rather see your name here instead of theirs.
>
> If they don't intend reviewing/testing/applying patches, I can do it as
> a last resort but I would rather that someone who specifically cares for
> this hardware does it.
>
> Thanks,
> Conor.
>
> > +
> >  SOUND
> >  M:   Jaroslav Kysela <perex@perex.cz>
> >  M:   Takashi Iwai <tiwai@suse.com>
> > --
> > 2.25.1
> >

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
  2023-09-20  6:37 ` [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings Chen Wang
  2023-09-20  7:43   ` Guo Ren
  2023-09-20  8:28   ` Conor Dooley
@ 2023-09-20 11:55   ` Krzysztof Kozlowski
  2023-09-20 12:03     ` 汪辰
  2 siblings, 1 reply; 67+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-20 11:55 UTC (permalink / raw)
  To: Chen Wang, aou, chao.wei, conor, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang

On 20/09/2023 08:37, Chen Wang wrote:
> Add DT binding documentation for the Sophgo SG2042 Soc [1] and the
> Milk-V Pioneer board [2].
> 
> [1]: https://en.sophgo.com/product/introduce/sg2042.html
> [2]: https://milkv.io/pioneer

This is a friendly reminder during the review process.

It looks like you received a tag and forgot to add it.

If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions, under or above your Signed-off-by tag. Tag is "received", when
provided in a message replied to you on the mailing list. Tools like b4
can help here. However, there's no need to repost patches *only* to add
the tags. The upstream maintainer will do that for tags received on the
version they apply.

https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577

If a tag was not added on purpose, please state why and what changed.

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
  2023-09-20 11:55   ` Krzysztof Kozlowski
@ 2023-09-20 12:03     ` 汪辰
  2023-09-21  0:48       ` Jisheng Zhang
  0 siblings, 1 reply; 67+ messages in thread
From: 汪辰 @ 2023-09-20 12:03 UTC (permalink / raw)
  To: Krzysztof Kozlowski
  Cc: Chen Wang, aou, chao.wei, conor, devicetree, emil.renner.berthing,
	guoren, jszhang, linux-kernel, linux-riscv, palmer, paul.walmsley,
	xiaoguang.xing

Sorry, my mistake to forget adding the tag, will add in next revision.

&gt; -----原始邮件-----
&gt; 发件人: "Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>
&gt; 发送时间: 2023-09-20 19:55:30 (星期三)
&gt; 收件人: "Chen Wang" <unicornxw@gmail.com>, aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, emil.renner.berthing@canonical.com, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com
&gt; 抄送: "Chen Wang" <wangchen20@iscas.ac.cn>
&gt; 主题: Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
&gt; 
&gt; On 20/09/2023 08:37, Chen Wang wrote:
&gt; &gt; Add DT binding documentation for the Sophgo SG2042 Soc [1] and the
&gt; &gt; Milk-V Pioneer board [2].
&gt; &gt; 
&gt; &gt; [1]: https://en.sophgo.com/product/introduce/sg2042.html
&gt; &gt; [2]: https://milkv.io/pioneer
&gt; 
&gt; This is a friendly reminder during the review process.
&gt; 
&gt; It looks like you received a tag and forgot to add it.
&gt; 
&gt; If you do not know the process, here is a short explanation:
&gt; Please add Acked-by/Reviewed-by/Tested-by tags when posting new
&gt; versions, under or above your Signed-off-by tag. Tag is "received", when
&gt; provided in a message replied to you on the mailing list. Tools like b4
&gt; can help here. However, there's no need to repost patches *only* to add
&gt; the tags. The upstream maintainer will do that for tags received on the
&gt; version they apply.
&gt; 
&gt; https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577
&gt; 
&gt; If a tag was not added on purpose, please state why and what changed.
&gt; 
&gt; Best regards,
&gt; Krzysztof

------------------------------

Best Regards 

 汪辰(Wang Chen) 

</wangchen20@iscas.ac.cn></unicornxw@gmail.com></krzysztof.kozlowski@linaro.org>

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
  2023-09-20 12:03     ` 汪辰
@ 2023-09-21  0:48       ` Jisheng Zhang
  0 siblings, 0 replies; 67+ messages in thread
From: Jisheng Zhang @ 2023-09-21  0:48 UTC (permalink / raw)
  To: 汪辰
  Cc: Krzysztof Kozlowski, Chen Wang, aou, chao.wei, conor, devicetree,
	emil.renner.berthing, guoren, linux-kernel, linux-riscv, palmer,
	paul.walmsley, xiaoguang.xing

On Wed, Sep 20, 2023 at 08:03:50PM +0800, 汪辰 wrote:
> Sorry, my mistake to forget adding the tag, will add in next revision.

Hi Chen,

Soft remind: In mailist, top post should be avoided.

> 
> 
> &gt; -----原始邮件-----

And it looks like your email client is wrong, I dunno how your reply
looks in other people's email client, but it looks like html or
rich text in mutt.

> &gt; 发件人: "Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>
> &gt; 发送时间: 2023-09-20 19:55:30 (星期三)
> &gt; 收件人: "Chen Wang" <unicornxw@gmail.com>, aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, emil.renner.berthing@canonical.com, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com
> &gt; 抄送: "Chen Wang" <wangchen20@iscas.ac.cn>
> &gt; 主题: Re: [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings
> &gt; 
> &gt; On 20/09/2023 08:37, Chen Wang wrote:
> &gt; &gt; Add DT binding documentation for the Sophgo SG2042 Soc [1] and the
> &gt; &gt; Milk-V Pioneer board [2].
> &gt; &gt; 
> &gt; &gt; [1]: https://en.sophgo.com/product/introduce/sg2042.html
> &gt; &gt; [2]: https://milkv.io/pioneer
> &gt; 
> &gt; This is a friendly reminder during the review process.
> &gt; 
> &gt; It looks like you received a tag and forgot to add it.
> &gt; 
> &gt; If you do not know the process, here is a short explanation:
> &gt; Please add Acked-by/Reviewed-by/Tested-by tags when posting new
> &gt; versions, under or above your Signed-off-by tag. Tag is "received", when
> &gt; provided in a message replied to you on the mailing list. Tools like b4
> &gt; can help here. However, there's no need to repost patches *only* to add
> &gt; the tags. The upstream maintainer will do that for tags received on the
> &gt; version they apply.
> &gt; 
> &gt; https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577
> &gt; 
> &gt; If a tag was not added on purpose, please state why and what changed.
> &gt; 
> &gt; Best regards,
> &gt; Krzysztof
> 
> 
> ------------------------------
> 
> Best Regards 
>  
>  汪辰(Wang Chen) 
> 
> </wangchen20@iscas.ac.cn></unicornxw@gmail.com></krzysztof.kozlowski@linaro.org>

^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles
  2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
                   ` (2 preceding siblings ...)
  2023-09-20  6:37 ` [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings Chen Wang
@ 2023-09-20  6:38 ` Chen Wang
  2023-09-20  7:44   ` Guo Ren
  2023-09-20  8:37   ` Conor Dooley
  2023-09-20  6:39 ` [PATCH v2 05/11] dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC Chen Wang
                   ` (8 subsequent siblings)
  12 siblings, 2 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-20  6:38 UTC (permalink / raw)
  To: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang

The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C920 core is used in the SOPHGO SG2042 SoC.

Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 38c0b5213736..185a0191bad6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@ properties:
               - sifive,u74-mc
               - thead,c906
               - thead,c910
+              - thead,c920
           - const: riscv
       - items:
           - enum:
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles
  2023-09-20  6:38 ` [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles Chen Wang
@ 2023-09-20  7:44   ` Guo Ren
  2023-09-20  8:37   ` Conor Dooley
  1 sibling, 0 replies; 67+ messages in thread
From: Guo Ren @ 2023-09-20  7:44 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

On Wed, Sep 20, 2023 at 2:38 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> Notably, the C920 core is used in the SOPHGO SG2042 SoC.
>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 38c0b5213736..185a0191bad6 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -47,6 +47,7 @@ properties:
>                - sifive,u74-mc
>                - thead,c906
>                - thead,c910
> +              - thead,c920
Reviewed-by: Guo Ren <guoren@kernel.org>

>            - const: riscv
>        - items:
>            - enum:
> --
> 2.25.1
>


-- 
Best Regards
 Guo Ren

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles
  2023-09-20  6:38 ` [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles Chen Wang
  2023-09-20  7:44   ` Guo Ren
@ 2023-09-20  8:37   ` Conor Dooley
  1 sibling, 0 replies; 67+ messages in thread
From: Conor Dooley @ 2023-09-20  8:37 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

[-- Attachment #1: Type: text/plain, Size: 1007 bytes --]

On Wed, Sep 20, 2023 at 02:38:08PM +0800, Chen Wang wrote:
> The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> Notably, the C920 core is used in the SOPHGO SG2042 SoC.
> 
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 38c0b5213736..185a0191bad6 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -47,6 +47,7 @@ properties:
>                - sifive,u74-mc
>                - thead,c906
>                - thead,c910
> +              - thead,c920
>            - const: riscv
>        - items:
>            - enum:
> -- 
> 2.25.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCH v2 05/11] dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC
  2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
                   ` (3 preceding siblings ...)
  2023-09-20  6:38 ` [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles Chen Wang
@ 2023-09-20  6:39 ` Chen Wang
  2023-09-20  7:45   ` Guo Ren
  2023-09-20  8:57   ` Conor Dooley
  2023-09-20  6:39 ` [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint Chen Wang
                   ` (7 subsequent siblings)
  12 siblings, 2 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-20  6:39 UTC (permalink / raw)
  To: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang

Add compatible string for SOPHGO SG2042 plic.

Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index dc1f28e55266..16f9c4760c0f 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -65,6 +65,7 @@ properties:
       - items:
           - enum:
               - allwinner,sun20i-d1-plic
+              - sophgo,sg2042-plic
               - thead,th1520-plic
           - const: thead,c900-plic
       - items:
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 05/11] dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC
  2023-09-20  6:39 ` [PATCH v2 05/11] dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC Chen Wang
@ 2023-09-20  7:45   ` Guo Ren
  2023-09-20  8:57   ` Conor Dooley
  1 sibling, 0 replies; 67+ messages in thread
From: Guo Ren @ 2023-09-20  7:45 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

On Wed, Sep 20, 2023 at 2:39 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> Add compatible string for SOPHGO SG2042 plic.
>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index dc1f28e55266..16f9c4760c0f 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -65,6 +65,7 @@ properties:
>        - items:
>            - enum:
>                - allwinner,sun20i-d1-plic
> +              - sophgo,sg2042-plic
>                - thead,th1520-plic
>            - const: thead,c900-plic
>        - items:
> --
> 2.25.1
>
Reviewed-by: Guo Ren <guoren@kernel.org>

-- 
Best Regards
 Guo Ren

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 05/11] dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC
  2023-09-20  6:39 ` [PATCH v2 05/11] dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC Chen Wang
  2023-09-20  7:45   ` Guo Ren
@ 2023-09-20  8:57   ` Conor Dooley
  1 sibling, 0 replies; 67+ messages in thread
From: Conor Dooley @ 2023-09-20  8:57 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

[-- Attachment #1: Type: text/plain, Size: 1066 bytes --]

On Wed, Sep 20, 2023 at 02:39:03PM +0800, Chen Wang wrote:
> Add compatible string for SOPHGO SG2042 plic.
> 
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> ---
>  .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index dc1f28e55266..16f9c4760c0f 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -65,6 +65,7 @@ properties:
>        - items:
>            - enum:
>                - allwinner,sun20i-d1-plic
> +              - sophgo,sg2042-plic
>                - thead,th1520-plic
>            - const: thead,c900-plic
>        - items:
> -- 
> 2.25.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint
  2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
                   ` (4 preceding siblings ...)
  2023-09-20  6:39 ` [PATCH v2 05/11] dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC Chen Wang
@ 2023-09-20  6:39 ` Chen Wang
  2023-09-20  8:12   ` Guo Ren
                     ` (2 more replies)
  2023-09-20  6:39 ` [PATCH v2 07/11] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts Chen Wang
                   ` (6 subsequent siblings)
  12 siblings, 3 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-20  6:39 UTC (permalink / raw)
  To: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Inochi Amaoto, Chen Wang

From: Inochi Amaoto <inochiama@outlook.com>

Add two new compatible string formatted like `C9xx-clint-xxx` to identify
the timer and ipi device separately, and do not allow c900-clint as the
fallback to avoid conflict.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index a0185e15a42f..ae69696c5c75 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -39,6 +39,14 @@ properties:
               - allwinner,sun20i-d1-clint
               - thead,th1520-clint
           - const: thead,c900-clint
+      - items:
+          - enum:
+              - sophgo,sg2042-clint-mtimer
+          - const: thead,c900-clint-mtimer
+      - items:
+          - enum:
+              - sophgo,sg2042-clint-mswi
+          - const: thead,c900-clint-mswi
       - items:
           - const: sifive,clint0
           - const: riscv,clint0
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint
  2023-09-20  6:39 ` [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint Chen Wang
@ 2023-09-20  8:12   ` Guo Ren
  2023-09-20  8:50   ` Conor Dooley
  2023-09-20 11:57   ` Krzysztof Kozlowski
  2 siblings, 0 replies; 67+ messages in thread
From: Guo Ren @ 2023-09-20  8:12 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Inochi Amaoto, Chen Wang

On Wed, Sep 20, 2023 at 2:39 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> From: Inochi Amaoto <inochiama@outlook.com>
>
> Add two new compatible string formatted like `C9xx-clint-xxx` to identify
> the timer and ipi device separately, and do not allow c900-clint as the
> fallback to avoid conflict.
Please explain more about the c900-clint mtimer & mswi, why do we need
to separate the c900-clint into two pieces? When could we use
c900-clint which eases dts design?

>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index a0185e15a42f..ae69696c5c75 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -39,6 +39,14 @@ properties:
>                - allwinner,sun20i-d1-clint
>                - thead,th1520-clint
>            - const: thead,c900-clint
> +      - items:
> +          - enum:
> +              - sophgo,sg2042-clint-mtimer
> +          - const: thead,c900-clint-mtimer
> +      - items:
> +          - enum:
> +              - sophgo,sg2042-clint-mswi
> +          - const: thead,c900-clint-mswi
>        - items:
>            - const: sifive,clint0
>            - const: riscv,clint0
> --
> 2.25.1
>


-- 
Best Regards
 Guo Ren

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint
  2023-09-20  6:39 ` [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint Chen Wang
  2023-09-20  8:12   ` Guo Ren
@ 2023-09-20  8:50   ` Conor Dooley
  2023-09-20 11:57   ` Krzysztof Kozlowski
  2 siblings, 0 replies; 67+ messages in thread
From: Conor Dooley @ 2023-09-20  8:50 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Inochi Amaoto,
	Chen Wang

[-- Attachment #1: Type: text/plain, Size: 1938 bytes --]

On Wed, Sep 20, 2023 at 02:39:39PM +0800, Chen Wang wrote:
> From: Inochi Amaoto <inochiama@outlook.com>
> 
> Add two new compatible string formatted like `C9xx-clint-xxx` to identify
> the timer and ipi device separately, and do not allow c900-clint as the
> fallback to avoid conflict.
> 
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>

Have you ignored Krzysztof's comments on this? I don't see a response or
a reaction to his comments about the compatibles on the last version.
Additionally, where is the user for these? I don't see any drivers that
actually make use of these.

Why do you need to have 2 compatibles (and therefore 2 devices) for the
clint? I thought the clint was a single device, of which the mtimer and
mswi bits were just "features"? Having split register ranges isn't a
reason to have two compatibles, so I must be missing something here...

Thanks,
Conor.

> ---
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index a0185e15a42f..ae69696c5c75 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -39,6 +39,14 @@ properties:
>                - allwinner,sun20i-d1-clint
>                - thead,th1520-clint
>            - const: thead,c900-clint
> +      - items:
> +          - enum:
> +              - sophgo,sg2042-clint-mtimer
> +          - const: thead,c900-clint-mtimer
> +      - items:
> +          - enum:
> +              - sophgo,sg2042-clint-mswi
> +          - const: thead,c900-clint-mswi
>        - items:
>            - const: sifive,clint0
>            - const: riscv,clint0
> -- 
> 2.25.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint
  2023-09-20  6:39 ` [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint Chen Wang
  2023-09-20  8:12   ` Guo Ren
  2023-09-20  8:50   ` Conor Dooley
@ 2023-09-20 11:57   ` Krzysztof Kozlowski
  2 siblings, 0 replies; 67+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-20 11:57 UTC (permalink / raw)
  To: Chen Wang, aou, chao.wei, conor, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Inochi Amaoto, Chen Wang

On 20/09/2023 08:39, Chen Wang wrote:
> From: Inochi Amaoto <inochiama@outlook.com>
> 
> Add two new compatible string formatted like `C9xx-clint-xxx` to identify
> the timer and ipi device separately, and do not allow c900-clint as the

Why?

You received comment about it, so please provide proper explanation in
the commit msg.

Same device does not get two different compatibles.

You also did not respond to my comments, so you basically ignored it and
send the same.

NAK

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCH v2 07/11] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts
  2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
                   ` (5 preceding siblings ...)
  2023-09-20  6:39 ` [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint Chen Wang
@ 2023-09-20  6:39 ` Chen Wang
  2023-09-20  7:51   ` Guo Ren
  2023-09-20  8:37   ` Conor Dooley
  2023-09-20  6:40 ` [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support Chen Wang
                   ` (5 subsequent siblings)
  12 siblings, 2 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-20  6:39 UTC (permalink / raw)
  To: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang

From: Emil Renner Berthing <emil.renner.berthing@canonical.com>

Add compatible for the uarts on the Sophgo SG2042 RISC-V SoC.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---
 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 17c553123f96..011d89e6df0f 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -45,6 +45,7 @@ properties:
           - const: snps,dw-apb-uart
       - items:
           - enum:
+              - sophgo,sg2042-uart
               - starfive,jh7100-hsuart
               - starfive,jh7100-uart
           - const: snps,dw-apb-uart
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 07/11] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts
  2023-09-20  6:39 ` [PATCH v2 07/11] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts Chen Wang
@ 2023-09-20  7:51   ` Guo Ren
  2023-09-20  8:37   ` Conor Dooley
  1 sibling, 0 replies; 67+ messages in thread
From: Guo Ren @ 2023-09-20  7:51 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

On Wed, Sep 20, 2023 at 2:40 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Add compatible for the uarts on the Sophgo SG2042 RISC-V SoC.
>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> index 17c553123f96..011d89e6df0f 100644
> --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> @@ -45,6 +45,7 @@ properties:
>            - const: snps,dw-apb-uart
>        - items:
>            - enum:
> +              - sophgo,sg2042-uart
>                - starfive,jh7100-hsuart
>                - starfive,jh7100-uart
>            - const: snps,dw-apb-uart
> --
> 2.25.1
>
LGTM

Reviewed-by: Guo Ren <guoren@kernel.og>

-- 
Best Regards
 Guo Ren

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 07/11] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts
  2023-09-20  6:39 ` [PATCH v2 07/11] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts Chen Wang
  2023-09-20  7:51   ` Guo Ren
@ 2023-09-20  8:37   ` Conor Dooley
  1 sibling, 0 replies; 67+ messages in thread
From: Conor Dooley @ 2023-09-20  8:37 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

[-- Attachment #1: Type: text/plain, Size: 1153 bytes --]

On Wed, Sep 20, 2023 at 02:39:58PM +0800, Chen Wang wrote:
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> 
> Add compatible for the uarts on the Sophgo SG2042 RISC-V SoC.
> 
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> ---
>  Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> index 17c553123f96..011d89e6df0f 100644
> --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> @@ -45,6 +45,7 @@ properties:
>            - const: snps,dw-apb-uart
>        - items:
>            - enum:
> +              - sophgo,sg2042-uart
>                - starfive,jh7100-hsuart
>                - starfive,jh7100-uart
>            - const: snps,dw-apb-uart
> -- 
> 2.25.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support
  2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
                   ` (6 preceding siblings ...)
  2023-09-20  6:39 ` [PATCH v2 07/11] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts Chen Wang
@ 2023-09-20  6:40 ` Chen Wang
  2023-09-20  7:53   ` Guo Ren
  2023-09-22  9:41   ` Ben Dooks
  2023-09-20  6:40 ` [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree Chen Wang
                   ` (4 subsequent siblings)
  12 siblings, 2 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-20  6:40 UTC (permalink / raw)
  To: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang

From: Emil Renner Berthing <emil.renner.berthing@canonical.com>

Add quirk to skip setting the input clock rate for the uarts on the
Sophgo SG2042 SoC similar to the StarFive JH7100.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---
 drivers/tty/serial/8250/8250_dw.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index f4cafca1a7da..6c344877a07f 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
 	.quirks = DW_UART_QUIRK_IS_DMA_FC,
 };
 
-static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
+static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
 	.usr_reg = DW_UART_USR,
 	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
 };
@@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = {
 	{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
 	{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
 	{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
-	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
+	{ .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data },
+	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
 	{ /* Sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, dw8250_of_match);
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support
  2023-09-20  6:40 ` [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support Chen Wang
@ 2023-09-20  7:53   ` Guo Ren
  2023-09-20  8:05     ` Chen Wang
  2023-09-22  9:41   ` Ben Dooks
  1 sibling, 1 reply; 67+ messages in thread
From: Guo Ren @ 2023-09-20  7:53 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

On Wed, Sep 20, 2023 at 2:40 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Add quirk to skip setting the input clock rate for the uarts on the
> Sophgo SG2042 SoC similar to the StarFive JH7100.
>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  drivers/tty/serial/8250/8250_dw.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index f4cafca1a7da..6c344877a07f 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
>         .quirks = DW_UART_QUIRK_IS_DMA_FC,
>  };
>
> -static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
> +static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
>         .usr_reg = DW_UART_USR,
>         .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
>  };
> @@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = {
>         { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
>         { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
>         { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
> -       { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
> +       { .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data },
> +       { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
Why shall we touch the jh7100 stuff in this patch?

>         { /* Sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, dw8250_of_match);
> --
> 2.25.1
>


-- 
Best Regards
 Guo Ren

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support
  2023-09-20  7:53   ` Guo Ren
@ 2023-09-20  8:05     ` Chen Wang
  2023-09-20  8:08       ` Guo Ren
  0 siblings, 1 reply; 67+ messages in thread
From: Chen Wang @ 2023-09-20  8:05 UTC (permalink / raw)
  To: Guo Ren, Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

Ren, thanks for your review.

sg2042 and jh7100 use the same uart driver and we here just want to reuse the logic from jh7100.
We don't touch jh7100 stuff, we just rename "dw8250_starfive_jh7100_data"  to "dw8250_skip_set_rate_data" and make it a common data for both sg2042 and jh7100.

在 2023/9/20 15:53, Guo Ren 写道:
> On Wed, Sep 20, 2023 at 2:40 PM Chen Wang <unicornxw@gmail.com> wrote:
>> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>>
>> Add quirk to skip setting the input clock rate for the uarts on the
>> Sophgo SG2042 SoC similar to the StarFive JH7100.
>>
>> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
>> ---
>>   drivers/tty/serial/8250/8250_dw.c | 5 +++--
>>   1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
>> index f4cafca1a7da..6c344877a07f 100644
>> --- a/drivers/tty/serial/8250/8250_dw.c
>> +++ b/drivers/tty/serial/8250/8250_dw.c
>> @@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
>>          .quirks = DW_UART_QUIRK_IS_DMA_FC,
>>   };
>>
>> -static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
>> +static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
>>          .usr_reg = DW_UART_USR,
>>          .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
>>   };
>> @@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = {
>>          { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
>>          { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
>>          { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
>> -       { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
>> +       { .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data },
>> +       { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
> Why shall we touch the jh7100 stuff in this patch?
>
>>          { /* Sentinel */ }
>>   };
>>   MODULE_DEVICE_TABLE(of, dw8250_of_match);
>> --
>> 2.25.1
>>
>

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support
  2023-09-20  8:05     ` Chen Wang
@ 2023-09-20  8:08       ` Guo Ren
  0 siblings, 0 replies; 67+ messages in thread
From: Guo Ren @ 2023-09-20  8:08 UTC (permalink / raw)
  To: Chen Wang
  Cc: Chen Wang, aou, chao.wei, conor, devicetree, emil.renner.berthing,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

On Wed, Sep 20, 2023 at 4:06 PM Chen Wang <unicorn_wang@outlook.com> wrote:
>
> Ren, thanks for your review.
>
> sg2042 and jh7100 use the same uart driver and we here just want to reuse the logic from jh7100.
> We don't touch jh7100 stuff, we just rename "dw8250_starfive_jh7100_data"  to "dw8250_skip_set_rate_data" and make it a common data for both sg2042 and jh7100.
Okay, I got it now.
LGTM

Reviewed-by: Guo Ren <guoren@kernel.org>

>
> 在 2023/9/20 15:53, Guo Ren 写道:
> > On Wed, Sep 20, 2023 at 2:40 PM Chen Wang <unicornxw@gmail.com> wrote:
> >> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> >>
> >> Add quirk to skip setting the input clock rate for the uarts on the
> >> Sophgo SG2042 SoC similar to the StarFive JH7100.
> >>
> >> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> >> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> >> ---
> >>   drivers/tty/serial/8250/8250_dw.c | 5 +++--
> >>   1 file changed, 3 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> >> index f4cafca1a7da..6c344877a07f 100644
> >> --- a/drivers/tty/serial/8250/8250_dw.c
> >> +++ b/drivers/tty/serial/8250/8250_dw.c
> >> @@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
> >>          .quirks = DW_UART_QUIRK_IS_DMA_FC,
> >>   };
> >>
> >> -static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
> >> +static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
> >>          .usr_reg = DW_UART_USR,
> >>          .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
> >>   };
> >> @@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = {
> >>          { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
> >>          { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
> >>          { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
> >> -       { .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
> >> +       { .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data },
> >> +       { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
> > Why shall we touch the jh7100 stuff in this patch?
> >
> >>          { /* Sentinel */ }
> >>   };
> >>   MODULE_DEVICE_TABLE(of, dw8250_of_match);
> >> --
> >> 2.25.1
> >>
> >



-- 
Best Regards
 Guo Ren

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support
  2023-09-20  6:40 ` [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support Chen Wang
  2023-09-20  7:53   ` Guo Ren
@ 2023-09-22  9:41   ` Ben Dooks
  2023-09-22 10:40     ` Emil Renner Berthing
  1 sibling, 1 reply; 67+ messages in thread
From: Ben Dooks @ 2023-09-22  9:41 UTC (permalink / raw)
  To: Chen Wang, aou, chao.wei, conor, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang

On 20/09/2023 07:40, Chen Wang wrote:
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> 
> Add quirk to skip setting the input clock rate for the uarts on the
> Sophgo SG2042 SoC similar to the StarFive JH7100.

I'd love an actual explanation of why this is necessary here.

> 
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>   drivers/tty/serial/8250/8250_dw.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index f4cafca1a7da..6c344877a07f 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -770,7 +770,7 @@ static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
>   	.quirks = DW_UART_QUIRK_IS_DMA_FC,
>   };
>   
> -static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
> +static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
>   	.usr_reg = DW_UART_USR,
>   	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
>   };
> @@ -780,7 +780,8 @@ static const struct of_device_id dw8250_of_match[] = {
>   	{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
>   	{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
>   	{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
> -	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
> +	{ .compatible = "sophgo,sg2042-uart", .data = &dw8250_skip_set_rate_data },
> +	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
>   	{ /* Sentinel */ }
>   };
>   MODULE_DEVICE_TABLE(of, dw8250_of_match);

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html


^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support
  2023-09-22  9:41   ` Ben Dooks
@ 2023-09-22 10:40     ` Emil Renner Berthing
  2023-09-22 11:39       ` Chen Wang
  2023-09-26  7:38       ` Chen Wang
  0 siblings, 2 replies; 67+ messages in thread
From: Emil Renner Berthing @ 2023-09-22 10:40 UTC (permalink / raw)
  To: Ben Dooks, Chen Wang, aou, chao.wei, conor, devicetree,
	emil.renner.berthing, guoren, jszhang, krzysztof.kozlowski+dt,
	linux-kernel, linux-riscv, palmer, paul.walmsley, robh+dt,
	xiaoguang.xing
  Cc: Chen Wang

Ben Dooks wrote:
> On 20/09/2023 07:40, Chen Wang wrote:
> > From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> >
> > Add quirk to skip setting the input clock rate for the uarts on the
> > Sophgo SG2042 SoC similar to the StarFive JH7100.
>
> I'd love an actual explanation of why this is necessary here.

Makes sense. For the JH7100 the commit message is:

  On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to
  exactly 16 * 115200Hz and many other common bitrates. Trying this will
  only result in a higher input clock, but low enough that the UART's
  internal divisor can't come close enough to the baud rate target.
  So rather than try to set the input clock it's better to skip the
  clk_set_rate call and rely solely on the UART's internal divisor.

@Chen Wang is this also true for the SG2042?

/Emil

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support
  2023-09-22 10:40     ` Emil Renner Berthing
@ 2023-09-22 11:39       ` Chen Wang
  2023-09-26  7:38       ` Chen Wang
  1 sibling, 0 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-22 11:39 UTC (permalink / raw)
  To: Emil Renner Berthing
  Cc: Ben Dooks, aou, chao.wei, conor, devicetree, guoren, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

Regards,

unicornx

Emil Renner Berthing <emil.renner.berthing@canonical.com> 于2023年9月22日周五 18:40写道：
>
> Ben Dooks wrote:
> > On 20/09/2023 07:40, Chen Wang wrote:
> > > From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > >
> > > Add quirk to skip setting the input clock rate for the uarts on the
> > > Sophgo SG2042 SoC similar to the StarFive JH7100.
> >
> > I'd love an actual explanation of why this is necessary here.
>
> Makes sense. For the JH7100 the commit message is:
>
>   On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to
>   exactly 16 * 115200Hz and many other common bitrates. Trying this will
>   only result in a higher input clock, but low enough that the UART's
>   internal divisor can't come close enough to the baud rate target.
>   So rather than try to set the input clock it's better to skip the
>   clk_set_rate call and rely solely on the UART's internal divisor.
>
> @Chen Wang is this also true for the SG2042?
>
> /Emil

Emil & Ben,
I need to double-confirm this with sophgo engineers. Because they are
off work now, I will probably get back to you later next week.

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support
  2023-09-22 10:40     ` Emil Renner Berthing
  2023-09-22 11:39       ` Chen Wang
@ 2023-09-26  7:38       ` Chen Wang
  1 sibling, 0 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-26  7:38 UTC (permalink / raw)
  To: Emil Renner Berthing
  Cc: Ben Dooks, aou, chao.wei, conor, devicetree, guoren, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang, haijiao.liu

Emil Renner Berthing <emil.renner.berthing@canonical.com> 于2023年9月22日周五 18:40写道：
>
> Ben Dooks wrote:
> > On 20/09/2023 07:40, Chen Wang wrote:
> > > From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > >
> > > Add quirk to skip setting the input clock rate for the uarts on the
> > > Sophgo SG2042 SoC similar to the StarFive JH7100.
> >
> > I'd love an actual explanation of why this is necessary here.
>
> Makes sense. For the JH7100 the commit message is:
>
>   On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to
>   exactly 16 * 115200Hz and many other common bitrates. Trying this will
>   only result in a higher input clock, but low enough that the UART's
>   internal divisor can't come close enough to the baud rate target.
>   So rather than try to set the input clock it's better to skip the
>   clk_set_rate call and rely solely on the UART's internal divisor.
>
> @Chen Wang is this also true for the SG2042?
>
> /Emil

Emil & Ben,
After double-checking with Sophgo engineers and doing more
investigation, we think the original changes(quirk to skip setting the
input clock) on UART may not  be required. Due to currently, the
target of this patchset is just to enable a minimal system and no
clock relateding changes are included yet. I will first remove this
quirk change on UART and use the fixed frequence - 500M - and reply
solely on the UART's internal divisor to work. We will re-evaluate
this quirk change in next patchset when we involve clock related
stuff.
Looping Haijiao, engineer from Sophgo, who is working on clock on sg2042.

Regards,
Chen

^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
  2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
                   ` (7 preceding siblings ...)
  2023-09-20  6:40 ` [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support Chen Wang
@ 2023-09-20  6:40 ` Chen Wang
  2023-09-20  8:04   ` Guo Ren
                     ` (3 more replies)
  2023-09-20  6:40 ` [PATCH v2 10/11] riscv: dts: sophgo: add Milk-V Pioneer board " Chen Wang
                   ` (3 subsequent siblings)
  12 siblings, 4 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-20  6:40 UTC (permalink / raw)
  To: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang, Inochi Amaoto

Milk-V Pioneer motherboard is powered by SOPHON's SG2042.

SG2042 is server grade chip with high performance, low power
consumption and high data throughput.
Key features:
- 64 RISC-V cpu cores which implements IMAFDC
- 4 cores per cluster, 16 clusters on chip
- ......

More info is available at [1].

[1]: https://en.sophgo.com/product/introduce/sg2042.html

Currently only support booting into console with only uart,
other features will be added soon later.

Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1744 +++++++++++++++++++
 arch/riscv/boot/dts/sophgo/sg2042.dtsi      |  439 +++++
 2 files changed, 2183 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi

diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
new file mode 100644
index 000000000000..9fc79b1cf3bf
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -0,0 +1,1744 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
+ */
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <50000000>;
+
+		cpu-map {
+			socket0 {
+				cluster0 {
+					 core0 {
+						cpu = <&cpu0>;
+					 };
+					 core1 {
+						cpu = <&cpu1>;
+					 };
+					 core2 {
+						cpu = <&cpu2>;
+					 };
+					 core3 {
+						cpu = <&cpu3>;
+					 };
+				};
+
+				cluster1 {
+					 core0 {
+						cpu = <&cpu4>;
+					 };
+					 core1 {
+						cpu = <&cpu5>;
+					 };
+					 core2 {
+						cpu = <&cpu6>;
+					 };
+					 core3 {
+						cpu = <&cpu7>;
+					 };
+				};
+
+				cluster2 {
+					 core0 {
+						cpu = <&cpu16>;
+					 };
+					 core1 {
+						cpu = <&cpu17>;
+					 };
+					 core2 {
+						cpu = <&cpu18>;
+					 };
+					 core3 {
+						cpu = <&cpu19>;
+					 };
+				};
+
+				cluster3 {
+					 core0 {
+						cpu = <&cpu20>;
+					 };
+					 core1 {
+						cpu = <&cpu21>;
+					 };
+					 core2 {
+						cpu = <&cpu22>;
+					 };
+					 core3 {
+						cpu = <&cpu23>;
+					 };
+				};
+
+				cluster4 {
+					 core0 {
+						cpu = <&cpu8>;
+					 };
+					 core1 {
+						cpu = <&cpu9>;
+					 };
+					 core2 {
+						cpu = <&cpu10>;
+					 };
+					 core3 {
+						cpu = <&cpu11>;
+					 };
+				};
+
+				cluster5 {
+					 core0 {
+						cpu = <&cpu12>;
+					 };
+					 core1 {
+						cpu = <&cpu13>;
+					 };
+					 core2 {
+						cpu = <&cpu14>;
+					 };
+					 core3 {
+						cpu = <&cpu15>;
+					 };
+				};
+
+				cluster6 {
+					 core0 {
+						cpu = <&cpu24>;
+					 };
+					 core1 {
+						cpu = <&cpu25>;
+					 };
+					 core2 {
+						cpu = <&cpu26>;
+					 };
+					 core3 {
+						cpu = <&cpu27>;
+					 };
+				};
+
+				cluster7 {
+					 core0 {
+						cpu = <&cpu28>;
+					 };
+					 core1 {
+						cpu = <&cpu29>;
+					 };
+					 core2 {
+						cpu = <&cpu30>;
+					 };
+					 core3 {
+						cpu = <&cpu31>;
+					 };
+				};
+
+				cluster8 {
+					 core0 {
+						cpu = <&cpu32>;
+					 };
+					 core1 {
+						cpu = <&cpu33>;
+					 };
+					 core2 {
+						cpu = <&cpu34>;
+					 };
+					 core3 {
+						cpu = <&cpu35>;
+					 };
+				};
+
+				cluster9 {
+					 core0 {
+						cpu = <&cpu36>;
+					 };
+					 core1 {
+						cpu = <&cpu37>;
+					 };
+					 core2 {
+						cpu = <&cpu38>;
+					 };
+					 core3 {
+						cpu = <&cpu39>;
+					 };
+				};
+
+				cluster10 {
+					 core0 {
+						cpu = <&cpu48>;
+					 };
+					 core1 {
+						cpu = <&cpu49>;
+					 };
+					 core2 {
+						cpu = <&cpu50>;
+					 };
+					 core3 {
+						cpu = <&cpu51>;
+					 };
+				};
+
+				cluster11 {
+					 core0 {
+						cpu = <&cpu52>;
+					 };
+					 core1 {
+						cpu = <&cpu53>;
+					 };
+					 core2 {
+						cpu = <&cpu54>;
+					 };
+					 core3 {
+						cpu = <&cpu55>;
+					 };
+				};
+
+				cluster12 {
+					 core0 {
+						cpu = <&cpu40>;
+					 };
+					 core1 {
+						cpu = <&cpu41>;
+					 };
+					 core2 {
+						cpu = <&cpu42>;
+					 };
+					 core3 {
+						cpu = <&cpu43>;
+					 };
+				};
+
+				cluster13 {
+					 core0 {
+						cpu = <&cpu44>;
+					 };
+					 core1 {
+						cpu = <&cpu45>;
+					 };
+					 core2 {
+						cpu = <&cpu46>;
+					 };
+					 core3 {
+						cpu = <&cpu47>;
+					 };
+				};
+
+				cluster14 {
+					 core0 {
+						cpu = <&cpu56>;
+					 };
+					 core1 {
+						cpu = <&cpu57>;
+					 };
+					 core2 {
+						cpu = <&cpu58>;
+					 };
+					 core3 {
+						cpu = <&cpu59>;
+					 };
+				};
+
+				cluster15 {
+					 core0 {
+						cpu = <&cpu60>;
+					 };
+					 core1 {
+						cpu = <&cpu61>;
+					 };
+					 core2 {
+						cpu = <&cpu62>;
+					 };
+					 core3 {
+						cpu = <&cpu63>;
+					 };
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <0>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache0>;
+			mmu-type = "riscv,sv39";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu1: cpu@1 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <1>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache0>;
+			mmu-type = "riscv,sv39";
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu2: cpu@2 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <2>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache0>;
+			mmu-type = "riscv,sv39";
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu3: cpu@3 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <3>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache0>;
+			mmu-type = "riscv,sv39";
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu4: cpu@4 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <4>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache1>;
+			mmu-type = "riscv,sv39";
+
+			cpu4_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu5: cpu@5 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <5>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache1>;
+			mmu-type = "riscv,sv39";
+
+			cpu5_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu6: cpu@6 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <6>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache1>;
+			mmu-type = "riscv,sv39";
+
+			cpu6_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu7: cpu@7 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <7>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache1>;
+			mmu-type = "riscv,sv39";
+
+			cpu7_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu8: cpu@8 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <8>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache4>;
+			mmu-type = "riscv,sv39";
+
+			cpu8_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu9: cpu@9 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <9>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache4>;
+			mmu-type = "riscv,sv39";
+
+			cpu9_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu10: cpu@10 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <10>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache4>;
+			mmu-type = "riscv,sv39";
+
+			cpu10_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu11: cpu@11 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <11>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache4>;
+			mmu-type = "riscv,sv39";
+
+			cpu11_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu12: cpu@12 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <12>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache5>;
+			mmu-type = "riscv,sv39";
+
+			cpu12_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu13: cpu@13 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <13>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache5>;
+			mmu-type = "riscv,sv39";
+
+			cpu13_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu14: cpu@14 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <14>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache5>;
+			mmu-type = "riscv,sv39";
+
+			cpu14_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu15: cpu@15 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <15>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache5>;
+			mmu-type = "riscv,sv39";
+
+			cpu15_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu16: cpu@16 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <16>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache2>;
+			mmu-type = "riscv,sv39";
+
+			cpu16_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu17: cpu@17 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <17>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache2>;
+			mmu-type = "riscv,sv39";
+
+			cpu17_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu18: cpu@18 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <18>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache2>;
+			mmu-type = "riscv,sv39";
+
+			cpu18_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu19: cpu@19 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <19>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache2>;
+			mmu-type = "riscv,sv39";
+
+			cpu19_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu20: cpu@20 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <20>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache3>;
+			mmu-type = "riscv,sv39";
+
+			cpu20_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu21: cpu@21 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <21>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache3>;
+			mmu-type = "riscv,sv39";
+
+			cpu21_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu22: cpu@22 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <22>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache3>;
+			mmu-type = "riscv,sv39";
+
+			cpu22_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu23: cpu@23 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <23>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache3>;
+			mmu-type = "riscv,sv39";
+
+			cpu23_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu24: cpu@24 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <24>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache6>;
+			mmu-type = "riscv,sv39";
+
+			cpu24_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu25: cpu@25 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <25>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache6>;
+			mmu-type = "riscv,sv39";
+
+			cpu25_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu26: cpu@26 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <26>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache6>;
+			mmu-type = "riscv,sv39";
+
+			cpu26_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu27: cpu@27 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <27>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache6>;
+			mmu-type = "riscv,sv39";
+
+			cpu27_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu28: cpu@28 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <28>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache7>;
+			mmu-type = "riscv,sv39";
+
+			cpu28_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu29: cpu@29 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <29>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache7>;
+			mmu-type = "riscv,sv39";
+
+			cpu29_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu30: cpu@30 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <30>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache7>;
+			mmu-type = "riscv,sv39";
+
+			cpu30_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu31: cpu@31 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <31>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache7>;
+			mmu-type = "riscv,sv39";
+
+			cpu31_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu32: cpu@32 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <32>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache8>;
+			mmu-type = "riscv,sv39";
+
+			cpu32_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu33: cpu@33 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <33>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache8>;
+			mmu-type = "riscv,sv39";
+
+			cpu33_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu34: cpu@34 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <34>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache8>;
+			mmu-type = "riscv,sv39";
+
+			cpu34_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu35: cpu@35 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <35>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache8>;
+			mmu-type = "riscv,sv39";
+
+			cpu35_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu36: cpu@36 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <36>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache9>;
+			mmu-type = "riscv,sv39";
+
+			cpu36_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu37: cpu@37 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <37>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache9>;
+			mmu-type = "riscv,sv39";
+
+			cpu37_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu38: cpu@38 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <38>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache9>;
+			mmu-type = "riscv,sv39";
+
+			cpu38_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu39: cpu@39 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <39>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache9>;
+			mmu-type = "riscv,sv39";
+
+			cpu39_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu40: cpu@40 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <40>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache12>;
+			mmu-type = "riscv,sv39";
+
+			cpu40_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu41: cpu@41 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <41>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache12>;
+			mmu-type = "riscv,sv39";
+
+			cpu41_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu42: cpu@42 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <42>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache12>;
+			mmu-type = "riscv,sv39";
+
+			cpu42_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu43: cpu@43 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <43>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache12>;
+			mmu-type = "riscv,sv39";
+
+			cpu43_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu44: cpu@44 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <44>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache13>;
+			mmu-type = "riscv,sv39";
+
+			cpu44_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu45: cpu@45 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <45>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache13>;
+			mmu-type = "riscv,sv39";
+
+			cpu45_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu46: cpu@46 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <46>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache13>;
+			mmu-type = "riscv,sv39";
+
+			cpu46_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu47: cpu@47 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <47>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache13>;
+			mmu-type = "riscv,sv39";
+
+			cpu47_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu48: cpu@48 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <48>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache10>;
+			mmu-type = "riscv,sv39";
+
+			cpu48_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu49: cpu@49 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <49>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache10>;
+			mmu-type = "riscv,sv39";
+
+			cpu49_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu50: cpu@50 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <50>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache10>;
+			mmu-type = "riscv,sv39";
+
+			cpu50_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu51: cpu@51 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <51>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache10>;
+			mmu-type = "riscv,sv39";
+
+			cpu51_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu52: cpu@52 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <52>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache11>;
+			mmu-type = "riscv,sv39";
+
+			cpu52_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu53: cpu@53 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <53>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache11>;
+			mmu-type = "riscv,sv39";
+
+			cpu53_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu54: cpu@54 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <54>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache11>;
+			mmu-type = "riscv,sv39";
+
+			cpu54_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu55: cpu@55 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <55>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache11>;
+			mmu-type = "riscv,sv39";
+
+			cpu55_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu56: cpu@56 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <56>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache14>;
+			mmu-type = "riscv,sv39";
+
+			cpu56_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu57: cpu@57 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <57>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache14>;
+			mmu-type = "riscv,sv39";
+
+			cpu57_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu58: cpu@58 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <58>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache14>;
+			mmu-type = "riscv,sv39";
+
+			cpu58_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu59: cpu@59 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <59>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache14>;
+			mmu-type = "riscv,sv39";
+
+			cpu59_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu60: cpu@60 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <60>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache15>;
+			mmu-type = "riscv,sv39";
+
+			cpu60_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu61: cpu@61 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <61>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache15>;
+			mmu-type = "riscv,sv39";
+
+			cpu61_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu62: cpu@62 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <62>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache15>;
+			mmu-type = "riscv,sv39";
+
+			cpu62_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu63: cpu@63 {
+			compatible = "thead,c920", "riscv";
+			device_type = "cpu";
+			riscv,isa = "rv64imafdc";
+			reg = <63>;
+			i-cache-block-size = <64>;
+			i-cache-size = <65536>;
+			i-cache-sets = <512>;
+			d-cache-block-size = <64>;
+			d-cache-size = <65536>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_cache15>;
+			mmu-type = "riscv,sv39";
+
+			cpu63_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		l2_cache0: l2-cache@0 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache1: l2-cache@1 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache2: l2-cache@2 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache3: l2-cache@3 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache4: l2-cache@4 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache5: l2-cache@5 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache6: l2-cache@6 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache7: l2-cache@7 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache8: l2-cache@8 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache9: l2-cache@9 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache10: l2-cache@10 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache11: l2-cache@11 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache12: l2-cache@12 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache13: l2-cache@13 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache14: l2-cache@14 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+
+		l2_cache15: l2-cache@15 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <1048576>;
+			cache-sets = <1024>;
+			cache-unified;
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
new file mode 100644
index 000000000000..747fd9764c95
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
+ */
+
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "sg2042-cpus.dtsi"
+
+#define SOC_PERIPHERAL_IRQ(nr) (nr)
+
+/ {
+	compatible = "sophgo,sg2042";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	dma-noncoherent;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	/* the mem node will be updated by ZSBL. */
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
+	};
+
+	memory@1 {
+		device_type = "memory";
+		reg = <0x00000000 0x00000001 0x00000000 0x00000000>;
+	};
+
+	memory@2 {
+		device_type = "memory";
+		reg = <0x00000000 0x00000002 0x00000000 0x00000000>;
+	};
+
+	memory@3 {
+		device_type = "memory";
+		reg = <0x00000000 0x00000003 0x00000000 0x00000000>;
+	};
+
+	pmu {
+		compatible = "riscv,pmu";
+		riscv,event-to-mhpmevent =
+			<0x00003 0x00000000 0x00000010>,
+			<0x00004 0x00000000 0x00000011>,
+			<0x00005 0x00000000 0x00000007>,
+			<0x00006 0x00000000 0x00000006>,
+			<0x00008 0x00000000 0x00000027>,
+			<0x00009 0x00000000 0x00000028>,
+			<0x10000 0x00000000 0x0000000c>,
+			<0x10001 0x00000000 0x0000000d>,
+			<0x10002 0x00000000 0x0000000e>,
+			<0x10003 0x00000000 0x0000000f>,
+			<0x10008 0x00000000 0x00000001>,
+			<0x10009 0x00000000 0x00000002>,
+			<0x10010 0x00000000 0x00000010>,
+			<0x10011 0x00000000 0x00000011>,
+			<0x10012 0x00000000 0x00000012>,
+			<0x10013 0x00000000 0x00000013>,
+			<0x10019 0x00000000 0x00000004>,
+			<0x10021 0x00000000 0x00000003>,
+			<0x10030 0x00000000 0x0000001c>,
+			<0x10031 0x00000000 0x0000001b>;
+		riscv,event-to-mhpmcounters =
+			<0x00003 0x00003 0xfffffff8>,
+			<0x00004 0x00004 0xfffffff8>,
+			<0x00005 0x00005 0xfffffff8>,
+			<0x00006 0x00006 0xfffffff8>,
+			<0x00007 0x00007 0xfffffff8>,
+			<0x00008 0x00008 0xfffffff8>,
+			<0x00009 0x00009 0xfffffff8>,
+			<0x0000a 0x0000a 0xfffffff8>,
+			<0x10000 0x10000 0xfffffff8>,
+			<0x10001 0x10001 0xfffffff8>,
+			<0x10002 0x10002 0xfffffff8>,
+			<0x10003 0x10003 0xfffffff8>,
+			<0x10008 0x10008 0xfffffff8>,
+			<0x10009 0x10009 0xfffffff8>,
+			<0x10010 0x10010 0xfffffff8>,
+			<0x10011 0x10011 0xfffffff8>,
+			<0x10012 0x10012 0xfffffff8>,
+			<0x10013 0x10013 0xfffffff8>,
+			<0x10019 0x10019 0xfffffff8>,
+			<0x10021 0x10021 0xfffffff8>,
+			<0x10030 0x10030 0xfffffff8>,
+			<0x10031 0x10031 0xfffffff8>;
+		riscv,raw-event-to-mhpmcounters =
+			<0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>,
+			<0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>;
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		clint_mswi: interrupt-controller@7094000000 {
+			compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi";
+			reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
+			interrupts-extended = <&cpu0_intc 3>,
+					      <&cpu1_intc 3>,
+					      <&cpu2_intc 3>,
+					      <&cpu3_intc 3>,
+					      <&cpu4_intc 3>,
+					      <&cpu5_intc 3>,
+					      <&cpu6_intc 3>,
+					      <&cpu7_intc 3>,
+					      <&cpu8_intc 3>,
+					      <&cpu9_intc 3>,
+					      <&cpu10_intc 3>,
+					      <&cpu11_intc 3>,
+					      <&cpu12_intc 3>,
+					      <&cpu13_intc 3>,
+					      <&cpu14_intc 3>,
+					      <&cpu15_intc 3>,
+					      <&cpu16_intc 3>,
+					      <&cpu17_intc 3>,
+					      <&cpu18_intc 3>,
+					      <&cpu19_intc 3>,
+					      <&cpu20_intc 3>,
+					      <&cpu21_intc 3>,
+					      <&cpu22_intc 3>,
+					      <&cpu23_intc 3>,
+					      <&cpu24_intc 3>,
+					      <&cpu25_intc 3>,
+					      <&cpu26_intc 3>,
+					      <&cpu27_intc 3>,
+					      <&cpu28_intc 3>,
+					      <&cpu29_intc 3>,
+					      <&cpu30_intc 3>,
+					      <&cpu31_intc 3>,
+					      <&cpu32_intc 3>,
+					      <&cpu33_intc 3>,
+					      <&cpu34_intc 3>,
+					      <&cpu35_intc 3>,
+					      <&cpu36_intc 3>,
+					      <&cpu37_intc 3>,
+					      <&cpu38_intc 3>,
+					      <&cpu39_intc 3>,
+					      <&cpu40_intc 3>,
+					      <&cpu41_intc 3>,
+					      <&cpu42_intc 3>,
+					      <&cpu43_intc 3>,
+					      <&cpu44_intc 3>,
+					      <&cpu45_intc 3>,
+					      <&cpu46_intc 3>,
+					      <&cpu47_intc 3>,
+					      <&cpu48_intc 3>,
+					      <&cpu49_intc 3>,
+					      <&cpu50_intc 3>,
+					      <&cpu51_intc 3>,
+					      <&cpu52_intc 3>,
+					      <&cpu53_intc 3>,
+					      <&cpu54_intc 3>,
+					      <&cpu55_intc 3>,
+					      <&cpu56_intc 3>,
+					      <&cpu57_intc 3>,
+					      <&cpu58_intc 3>,
+					      <&cpu59_intc 3>,
+					      <&cpu60_intc 3>,
+					      <&cpu61_intc 3>,
+					      <&cpu62_intc 3>,
+					      <&cpu63_intc 3>;
+		};
+
+		clint_mtimer0: timer@70ac000000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu0_intc 7>,
+					      <&cpu1_intc 7>,
+					      <&cpu2_intc 7>,
+					      <&cpu3_intc 7>;
+		};
+
+		clint_mtimer1: timer@70ac010000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu4_intc 7>,
+					      <&cpu5_intc 7>,
+					      <&cpu6_intc 7>,
+					      <&cpu7_intc 7>;
+		};
+
+		clint_mtimer2: timer@70ac020000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu8_intc 7>,
+					      <&cpu9_intc 7>,
+					      <&cpu10_intc 7>,
+					      <&cpu11_intc 7>;
+		};
+
+		clint_mtimer3: timer@70ac030000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu12_intc 7>,
+					      <&cpu13_intc 7>,
+					      <&cpu14_intc 7>,
+					      <&cpu15_intc 7>;
+		};
+
+		clint_mtimer4: timer@70ac040000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu16_intc 7>,
+					      <&cpu17_intc 7>,
+					      <&cpu18_intc 7>,
+					      <&cpu19_intc 7>;
+		};
+
+		clint_mtimer5: timer@70ac050000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu20_intc 7>,
+					      <&cpu21_intc 7>,
+					      <&cpu22_intc 7>,
+					      <&cpu23_intc 7>;
+		};
+
+		clint_mtimer6: timer@70ac060000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu24_intc 7>,
+					      <&cpu25_intc 7>,
+					      <&cpu26_intc 7>,
+					      <&cpu27_intc 7>;
+		};
+
+		clint_mtimer7: timer@70ac070000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu28_intc 7>,
+					      <&cpu29_intc 7>,
+					      <&cpu30_intc 7>,
+					      <&cpu31_intc 7>;
+		};
+
+		clint_mtimer8: timer@70ac080000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu32_intc 7>,
+					      <&cpu33_intc 7>,
+					      <&cpu34_intc 7>,
+					      <&cpu35_intc 7>;
+		};
+
+		clint_mtimer9: timer@70ac090000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu36_intc 7>,
+					      <&cpu37_intc 7>,
+					      <&cpu38_intc 7>,
+					      <&cpu39_intc 7>;
+		};
+
+		clint_mtimer10: timer@70ac0a0000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu40_intc 7>,
+					      <&cpu41_intc 7>,
+					      <&cpu42_intc 7>,
+					      <&cpu43_intc 7>;
+		};
+
+		clint_mtimer11: timer@70ac0b0000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu44_intc 7>,
+					      <&cpu45_intc 7>,
+					      <&cpu46_intc 7>,
+					      <&cpu47_intc 7>;
+		};
+
+		clint_mtimer12: timer@70ac0c0000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu48_intc 7>,
+					      <&cpu49_intc 7>,
+					      <&cpu50_intc 7>,
+					      <&cpu51_intc 7>;
+		};
+
+		clint_mtimer13: timer@70ac0d0000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu52_intc 7>,
+					      <&cpu53_intc 7>,
+					      <&cpu54_intc 7>,
+					      <&cpu55_intc 7>;
+		};
+
+		clint_mtimer14: timer@70ac0e0000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu56_intc 7>,
+					      <&cpu57_intc 7>,
+					      <&cpu58_intc 7>,
+					      <&cpu59_intc 7>;
+		};
+
+		clint_mtimer15: timer@70ac0f0000 {
+			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
+			reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
+			interrupts-extended = <&cpu60_intc 7>,
+					      <&cpu61_intc 7>,
+					      <&cpu62_intc 7>,
+					      <&cpu63_intc 7>;
+		};
+
+		intc: interrupt-controller@7090000000 {
+			compatible = "sophgo,sg2042-plic", "thead,c900-plic";
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
+			interrupt-controller;
+			interrupts-extended =
+				<&cpu0_intc 0xffffffff>,  <&cpu0_intc 9>,
+				<&cpu1_intc 0xffffffff>,  <&cpu1_intc 9>,
+				<&cpu2_intc 0xffffffff>,  <&cpu2_intc 9>,
+				<&cpu3_intc 0xffffffff>,  <&cpu3_intc 9>,
+				<&cpu4_intc 0xffffffff>,  <&cpu4_intc 9>,
+				<&cpu5_intc 0xffffffff>,  <&cpu5_intc 9>,
+				<&cpu6_intc 0xffffffff>,  <&cpu6_intc 9>,
+				<&cpu7_intc 0xffffffff>,  <&cpu7_intc 9>,
+				<&cpu8_intc 0xffffffff>,  <&cpu8_intc 9>,
+				<&cpu9_intc 0xffffffff>,  <&cpu9_intc 9>,
+				<&cpu10_intc 0xffffffff>, <&cpu10_intc 9>,
+				<&cpu11_intc 0xffffffff>, <&cpu11_intc 9>,
+				<&cpu12_intc 0xffffffff>, <&cpu12_intc 9>,
+				<&cpu13_intc 0xffffffff>, <&cpu13_intc 9>,
+				<&cpu14_intc 0xffffffff>, <&cpu14_intc 9>,
+				<&cpu15_intc 0xffffffff>, <&cpu15_intc 9>,
+				<&cpu16_intc 0xffffffff>, <&cpu16_intc 9>,
+				<&cpu17_intc 0xffffffff>, <&cpu17_intc 9>,
+				<&cpu18_intc 0xffffffff>, <&cpu18_intc 9>,
+				<&cpu19_intc 0xffffffff>, <&cpu19_intc 9>,
+				<&cpu20_intc 0xffffffff>, <&cpu20_intc 9>,
+				<&cpu21_intc 0xffffffff>, <&cpu21_intc 9>,
+				<&cpu22_intc 0xffffffff>, <&cpu22_intc 9>,
+				<&cpu23_intc 0xffffffff>, <&cpu23_intc 9>,
+				<&cpu24_intc 0xffffffff>, <&cpu24_intc 9>,
+				<&cpu25_intc 0xffffffff>, <&cpu25_intc 9>,
+				<&cpu26_intc 0xffffffff>, <&cpu26_intc 9>,
+				<&cpu27_intc 0xffffffff>, <&cpu27_intc 9>,
+				<&cpu28_intc 0xffffffff>, <&cpu28_intc 9>,
+				<&cpu29_intc 0xffffffff>, <&cpu29_intc 9>,
+				<&cpu30_intc 0xffffffff>, <&cpu30_intc 9>,
+				<&cpu31_intc 0xffffffff>, <&cpu31_intc 9>,
+				<&cpu32_intc 0xffffffff>, <&cpu32_intc 9>,
+				<&cpu33_intc 0xffffffff>, <&cpu33_intc 9>,
+				<&cpu34_intc 0xffffffff>, <&cpu34_intc 9>,
+				<&cpu35_intc 0xffffffff>, <&cpu35_intc 9>,
+				<&cpu36_intc 0xffffffff>, <&cpu36_intc 9>,
+				<&cpu37_intc 0xffffffff>, <&cpu37_intc 9>,
+				<&cpu38_intc 0xffffffff>, <&cpu38_intc 9>,
+				<&cpu39_intc 0xffffffff>, <&cpu39_intc 9>,
+				<&cpu40_intc 0xffffffff>, <&cpu40_intc 9>,
+				<&cpu41_intc 0xffffffff>, <&cpu41_intc 9>,
+				<&cpu42_intc 0xffffffff>, <&cpu42_intc 9>,
+				<&cpu43_intc 0xffffffff>, <&cpu43_intc 9>,
+				<&cpu44_intc 0xffffffff>, <&cpu44_intc 9>,
+				<&cpu45_intc 0xffffffff>, <&cpu45_intc 9>,
+				<&cpu46_intc 0xffffffff>, <&cpu46_intc 9>,
+				<&cpu47_intc 0xffffffff>, <&cpu47_intc 9>,
+				<&cpu48_intc 0xffffffff>, <&cpu48_intc 9>,
+				<&cpu49_intc 0xffffffff>, <&cpu49_intc 9>,
+				<&cpu50_intc 0xffffffff>, <&cpu50_intc 9>,
+				<&cpu51_intc 0xffffffff>, <&cpu51_intc 9>,
+				<&cpu52_intc 0xffffffff>, <&cpu52_intc 9>,
+				<&cpu53_intc 0xffffffff>, <&cpu53_intc 9>,
+				<&cpu54_intc 0xffffffff>, <&cpu54_intc 9>,
+				<&cpu55_intc 0xffffffff>, <&cpu55_intc 9>,
+				<&cpu56_intc 0xffffffff>, <&cpu56_intc 9>,
+				<&cpu57_intc 0xffffffff>, <&cpu57_intc 9>,
+				<&cpu58_intc 0xffffffff>, <&cpu58_intc 9>,
+				<&cpu59_intc 0xffffffff>, <&cpu59_intc 9>,
+				<&cpu60_intc 0xffffffff>, <&cpu60_intc 9>,
+				<&cpu61_intc 0xffffffff>, <&cpu61_intc 9>,
+				<&cpu62_intc 0xffffffff>, <&cpu62_intc 9>,
+				<&cpu63_intc 0xffffffff>, <&cpu63_intc 9>;
+			riscv,ndev = <224>;
+		};
+
+		uart0: serial@7040000000 {
+			compatible = "sophgo,sg2042-uart", "snps,dw-apb-uart";
+			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
+			interrupt-parent = <&intc>;
+			interrupts = <SOC_PERIPHERAL_IRQ(112) IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <500000000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+	};
+};
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
  2023-09-20  6:40 ` [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree Chen Wang
@ 2023-09-20  8:04   ` Guo Ren
  2023-09-20  8:57   ` Conor Dooley
                     ` (2 subsequent siblings)
  3 siblings, 0 replies; 67+ messages in thread
From: Guo Ren @ 2023-09-20  8:04 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang, Inochi Amaoto

On Wed, Sep 20, 2023 at 2:40 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> Milk-V Pioneer motherboard is powered by SOPHON's SG2042.
>
> SG2042 is server grade chip with high performance, low power
> consumption and high data throughput.
> Key features:
> - 64 RISC-V cpu cores which implements IMAFDC
> - 4 cores per cluster, 16 clusters on chip
> - ......
>
> More info is available at [1].
>
> [1]: https://en.sophgo.com/product/introduce/sg2042.html
>
> Currently only support booting into console with only uart,
> other features will be added soon later.
>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1744 +++++++++++++++++++
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi      |  439 +++++
>  2 files changed, 2183 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> new file mode 100644
> index 000000000000..9fc79b1cf3bf
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> @@ -0,0 +1,1744 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +/ {
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               timebase-frequency = <50000000>;
> +
> +               cpu-map {
> +                       socket0 {
> +                               cluster0 {
> +                                        core0 {
> +                                               cpu = <&cpu0>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu1>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu2>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu3>;
> +                                        };
> +                               };
> +
> +                               cluster1 {
> +                                        core0 {
> +                                               cpu = <&cpu4>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu5>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu6>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu7>;
> +                                        };
> +                               };
> +
> +                               cluster2 {
> +                                        core0 {
> +                                               cpu = <&cpu16>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu17>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu18>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu19>;
> +                                        };
> +                               };
> +
> +                               cluster3 {
> +                                        core0 {
> +                                               cpu = <&cpu20>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu21>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu22>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu23>;
> +                                        };
> +                               };
> +
> +                               cluster4 {
> +                                        core0 {
> +                                               cpu = <&cpu8>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu9>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu10>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu11>;
> +                                        };
> +                               };
> +
> +                               cluster5 {
> +                                        core0 {
> +                                               cpu = <&cpu12>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu13>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu14>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu15>;
> +                                        };
> +                               };
> +
> +                               cluster6 {
> +                                        core0 {
> +                                               cpu = <&cpu24>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu25>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu26>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu27>;
> +                                        };
> +                               };
> +
> +                               cluster7 {
> +                                        core0 {
> +                                               cpu = <&cpu28>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu29>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu30>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu31>;
> +                                        };
> +                               };
> +
> +                               cluster8 {
> +                                        core0 {
> +                                               cpu = <&cpu32>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu33>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu34>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu35>;
> +                                        };
> +                               };
> +
> +                               cluster9 {
> +                                        core0 {
> +                                               cpu = <&cpu36>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu37>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu38>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu39>;
> +                                        };
> +                               };
> +
> +                               cluster10 {
> +                                        core0 {
> +                                               cpu = <&cpu48>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu49>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu50>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu51>;
> +                                        };
> +                               };
> +
> +                               cluster11 {
> +                                        core0 {
> +                                               cpu = <&cpu52>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu53>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu54>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu55>;
> +                                        };
> +                               };
> +
> +                               cluster12 {
> +                                        core0 {
> +                                               cpu = <&cpu40>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu41>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu42>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu43>;
> +                                        };
> +                               };
> +
> +                               cluster13 {
> +                                        core0 {
> +                                               cpu = <&cpu44>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu45>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu46>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu47>;
> +                                        };
> +                               };
> +
> +                               cluster14 {
> +                                        core0 {
> +                                               cpu = <&cpu56>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu57>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu58>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu59>;
> +                                        };
> +                               };
> +
> +                               cluster15 {
> +                                        core0 {
> +                                               cpu = <&cpu60>;
> +                                        };
> +                                        core1 {
> +                                               cpu = <&cpu61>;
> +                                        };
> +                                        core2 {
> +                                               cpu = <&cpu62>;
> +                                        };
> +                                        core3 {
> +                                               cpu = <&cpu63>;
> +                                        };
> +                               };
> +                       };
> +               };
> +
> +               cpu0: cpu@0 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <0>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache0>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu0_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu1: cpu@1 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <1>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache0>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu1_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu2: cpu@2 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <2>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache0>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu2_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu3: cpu@3 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <3>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache0>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu3_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu4: cpu@4 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <4>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache1>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu4_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu5: cpu@5 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <5>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache1>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu5_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu6: cpu@6 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <6>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache1>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu6_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu7: cpu@7 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <7>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache1>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu7_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu8: cpu@8 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <8>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache4>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu8_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu9: cpu@9 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <9>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache4>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu9_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu10: cpu@10 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <10>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache4>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu10_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu11: cpu@11 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <11>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache4>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu11_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu12: cpu@12 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <12>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache5>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu12_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu13: cpu@13 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <13>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache5>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu13_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu14: cpu@14 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <14>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache5>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu14_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu15: cpu@15 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <15>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache5>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu15_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu16: cpu@16 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <16>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache2>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu16_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu17: cpu@17 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <17>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache2>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu17_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu18: cpu@18 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <18>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache2>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu18_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu19: cpu@19 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <19>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache2>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu19_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu20: cpu@20 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <20>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache3>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu20_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu21: cpu@21 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <21>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache3>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu21_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu22: cpu@22 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <22>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache3>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu22_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu23: cpu@23 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <23>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache3>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu23_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu24: cpu@24 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <24>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache6>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu24_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu25: cpu@25 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <25>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache6>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu25_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu26: cpu@26 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <26>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache6>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu26_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu27: cpu@27 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <27>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache6>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu27_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu28: cpu@28 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <28>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache7>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu28_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu29: cpu@29 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <29>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache7>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu29_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu30: cpu@30 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <30>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache7>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu30_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu31: cpu@31 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <31>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache7>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu31_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu32: cpu@32 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <32>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache8>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu32_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu33: cpu@33 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <33>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache8>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu33_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu34: cpu@34 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <34>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache8>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu34_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu35: cpu@35 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <35>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache8>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu35_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu36: cpu@36 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <36>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache9>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu36_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu37: cpu@37 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <37>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache9>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu37_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu38: cpu@38 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <38>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache9>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu38_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu39: cpu@39 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <39>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache9>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu39_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu40: cpu@40 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <40>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache12>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu40_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu41: cpu@41 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <41>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache12>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu41_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu42: cpu@42 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <42>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache12>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu42_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu43: cpu@43 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <43>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache12>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu43_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu44: cpu@44 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <44>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache13>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu44_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu45: cpu@45 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <45>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache13>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu45_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu46: cpu@46 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <46>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache13>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu46_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu47: cpu@47 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <47>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache13>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu47_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu48: cpu@48 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <48>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache10>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu48_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu49: cpu@49 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <49>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache10>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu49_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu50: cpu@50 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <50>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache10>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu50_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu51: cpu@51 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <51>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache10>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu51_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu52: cpu@52 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <52>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache11>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu52_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu53: cpu@53 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <53>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache11>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu53_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu54: cpu@54 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <54>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache11>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu54_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu55: cpu@55 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <55>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache11>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu55_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu56: cpu@56 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <56>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache14>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu56_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu57: cpu@57 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <57>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache14>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu57_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu58: cpu@58 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <58>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache14>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu58_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu59: cpu@59 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <59>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache14>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu59_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu60: cpu@60 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <60>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache15>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu60_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu61: cpu@61 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <61>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache15>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu61_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu62: cpu@62 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <62>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache15>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu62_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               cpu63: cpu@63 {
> +                       compatible = "thead,c920", "riscv";
> +                       device_type = "cpu";
> +                       riscv,isa = "rv64imafdc";
> +                       reg = <63>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-size = <65536>;
> +                       i-cache-sets = <512>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-size = <65536>;
> +                       d-cache-sets = <512>;
> +                       next-level-cache = <&l2_cache15>;
> +                       mmu-type = "riscv,sv39";
> +
> +                       cpu63_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +
> +               l2_cache0: l2-cache@0 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache1: l2-cache@1 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache2: l2-cache@2 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache3: l2-cache@3 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache4: l2-cache@4 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache5: l2-cache@5 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache6: l2-cache@6 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache7: l2-cache@7 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache8: l2-cache@8 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache9: l2-cache@9 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache10: l2-cache@10 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache11: l2-cache@11 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache12: l2-cache@12 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache13: l2-cache@13 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache14: l2-cache@14 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +
> +               l2_cache15: l2-cache@15 {
> +                       compatible = "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-size = <1048576>;
> +                       cache-sets = <1024>;
> +                       cache-unified;
> +               };
> +       };
> +};
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> new file mode 100644
> index 000000000000..747fd9764c95
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -0,0 +1,439 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +#include "sg2042-cpus.dtsi"
> +
> +#define SOC_PERIPHERAL_IRQ(nr) (nr)
> +
> +/ {
> +       compatible = "sophgo,sg2042";
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +       dma-noncoherent;
> +
> +       aliases {
> +               serial0 = &uart0;
> +       };
> +
> +       /* the mem node will be updated by ZSBL. */
> +       memory@0 {
> +               device_type = "memory";
> +               reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
> +       };
> +
> +       memory@1 {
> +               device_type = "memory";
> +               reg = <0x00000000 0x00000001 0x00000000 0x00000000>;
> +       };
> +
> +       memory@2 {
> +               device_type = "memory";
> +               reg = <0x00000000 0x00000002 0x00000000 0x00000000>;
> +       };
> +
> +       memory@3 {
> +               device_type = "memory";
> +               reg = <0x00000000 0x00000003 0x00000000 0x00000000>;
> +       };
> +
> +       pmu {
> +               compatible = "riscv,pmu";
> +               riscv,event-to-mhpmevent =
> +                       <0x00003 0x00000000 0x00000010>,
> +                       <0x00004 0x00000000 0x00000011>,
> +                       <0x00005 0x00000000 0x00000007>,
> +                       <0x00006 0x00000000 0x00000006>,
> +                       <0x00008 0x00000000 0x00000027>,
> +                       <0x00009 0x00000000 0x00000028>,
> +                       <0x10000 0x00000000 0x0000000c>,
> +                       <0x10001 0x00000000 0x0000000d>,
> +                       <0x10002 0x00000000 0x0000000e>,
> +                       <0x10003 0x00000000 0x0000000f>,
> +                       <0x10008 0x00000000 0x00000001>,
> +                       <0x10009 0x00000000 0x00000002>,
> +                       <0x10010 0x00000000 0x00000010>,
> +                       <0x10011 0x00000000 0x00000011>,
> +                       <0x10012 0x00000000 0x00000012>,
> +                       <0x10013 0x00000000 0x00000013>,
> +                       <0x10019 0x00000000 0x00000004>,
> +                       <0x10021 0x00000000 0x00000003>,
> +                       <0x10030 0x00000000 0x0000001c>,
> +                       <0x10031 0x00000000 0x0000001b>;
> +               riscv,event-to-mhpmcounters =
> +                       <0x00003 0x00003 0xfffffff8>,
> +                       <0x00004 0x00004 0xfffffff8>,
> +                       <0x00005 0x00005 0xfffffff8>,
> +                       <0x00006 0x00006 0xfffffff8>,
> +                       <0x00007 0x00007 0xfffffff8>,
> +                       <0x00008 0x00008 0xfffffff8>,
> +                       <0x00009 0x00009 0xfffffff8>,
> +                       <0x0000a 0x0000a 0xfffffff8>,
> +                       <0x10000 0x10000 0xfffffff8>,
> +                       <0x10001 0x10001 0xfffffff8>,
> +                       <0x10002 0x10002 0xfffffff8>,
> +                       <0x10003 0x10003 0xfffffff8>,
> +                       <0x10008 0x10008 0xfffffff8>,
> +                       <0x10009 0x10009 0xfffffff8>,
> +                       <0x10010 0x10010 0xfffffff8>,
> +                       <0x10011 0x10011 0xfffffff8>,
> +                       <0x10012 0x10012 0xfffffff8>,
> +                       <0x10013 0x10013 0xfffffff8>,
> +                       <0x10019 0x10019 0xfffffff8>,
> +                       <0x10021 0x10021 0xfffffff8>,
> +                       <0x10030 0x10030 0xfffffff8>,
> +                       <0x10031 0x10031 0xfffffff8>;
> +               riscv,raw-event-to-mhpmcounters =
> +                       <0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>,
> +                       <0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>;
> +       };
> +
> +       soc: soc {
> +               compatible = "simple-bus";
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               clint_mswi: interrupt-controller@7094000000 {
> +                       compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi";
> +                       reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
> +                       interrupts-extended = <&cpu0_intc 3>,
> +                                             <&cpu1_intc 3>,
> +                                             <&cpu2_intc 3>,
> +                                             <&cpu3_intc 3>,
> +                                             <&cpu4_intc 3>,
> +                                             <&cpu5_intc 3>,
> +                                             <&cpu6_intc 3>,
> +                                             <&cpu7_intc 3>,
> +                                             <&cpu8_intc 3>,
> +                                             <&cpu9_intc 3>,
> +                                             <&cpu10_intc 3>,
> +                                             <&cpu11_intc 3>,
> +                                             <&cpu12_intc 3>,
> +                                             <&cpu13_intc 3>,
> +                                             <&cpu14_intc 3>,
> +                                             <&cpu15_intc 3>,
> +                                             <&cpu16_intc 3>,
> +                                             <&cpu17_intc 3>,
> +                                             <&cpu18_intc 3>,
> +                                             <&cpu19_intc 3>,
> +                                             <&cpu20_intc 3>,
> +                                             <&cpu21_intc 3>,
> +                                             <&cpu22_intc 3>,
> +                                             <&cpu23_intc 3>,
> +                                             <&cpu24_intc 3>,
> +                                             <&cpu25_intc 3>,
> +                                             <&cpu26_intc 3>,
> +                                             <&cpu27_intc 3>,
> +                                             <&cpu28_intc 3>,
> +                                             <&cpu29_intc 3>,
> +                                             <&cpu30_intc 3>,
> +                                             <&cpu31_intc 3>,
> +                                             <&cpu32_intc 3>,
> +                                             <&cpu33_intc 3>,
> +                                             <&cpu34_intc 3>,
> +                                             <&cpu35_intc 3>,
> +                                             <&cpu36_intc 3>,
> +                                             <&cpu37_intc 3>,
> +                                             <&cpu38_intc 3>,
> +                                             <&cpu39_intc 3>,
> +                                             <&cpu40_intc 3>,
> +                                             <&cpu41_intc 3>,
> +                                             <&cpu42_intc 3>,
> +                                             <&cpu43_intc 3>,
> +                                             <&cpu44_intc 3>,
> +                                             <&cpu45_intc 3>,
> +                                             <&cpu46_intc 3>,
> +                                             <&cpu47_intc 3>,
> +                                             <&cpu48_intc 3>,
> +                                             <&cpu49_intc 3>,
> +                                             <&cpu50_intc 3>,
> +                                             <&cpu51_intc 3>,
> +                                             <&cpu52_intc 3>,
> +                                             <&cpu53_intc 3>,
> +                                             <&cpu54_intc 3>,
> +                                             <&cpu55_intc 3>,
> +                                             <&cpu56_intc 3>,
> +                                             <&cpu57_intc 3>,
> +                                             <&cpu58_intc 3>,
> +                                             <&cpu59_intc 3>,
> +                                             <&cpu60_intc 3>,
> +                                             <&cpu61_intc 3>,
> +                                             <&cpu62_intc 3>,
> +                                             <&cpu63_intc 3>;
> +               };
> +
> +               clint_mtimer0: timer@70ac000000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu0_intc 7>,
> +                                             <&cpu1_intc 7>,
> +                                             <&cpu2_intc 7>,
> +                                             <&cpu3_intc 7>;
> +               };
> +
> +               clint_mtimer1: timer@70ac010000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu4_intc 7>,
> +                                             <&cpu5_intc 7>,
> +                                             <&cpu6_intc 7>,
> +                                             <&cpu7_intc 7>;
> +               };
> +
> +               clint_mtimer2: timer@70ac020000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu8_intc 7>,
> +                                             <&cpu9_intc 7>,
> +                                             <&cpu10_intc 7>,
> +                                             <&cpu11_intc 7>;
> +               };
> +
> +               clint_mtimer3: timer@70ac030000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu12_intc 7>,
> +                                             <&cpu13_intc 7>,
> +                                             <&cpu14_intc 7>,
> +                                             <&cpu15_intc 7>;
> +               };
> +
> +               clint_mtimer4: timer@70ac040000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu16_intc 7>,
> +                                             <&cpu17_intc 7>,
> +                                             <&cpu18_intc 7>,
> +                                             <&cpu19_intc 7>;
> +               };
> +
> +               clint_mtimer5: timer@70ac050000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu20_intc 7>,
> +                                             <&cpu21_intc 7>,
> +                                             <&cpu22_intc 7>,
> +                                             <&cpu23_intc 7>;
> +               };
> +
> +               clint_mtimer6: timer@70ac060000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu24_intc 7>,
> +                                             <&cpu25_intc 7>,
> +                                             <&cpu26_intc 7>,
> +                                             <&cpu27_intc 7>;
> +               };
> +
> +               clint_mtimer7: timer@70ac070000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu28_intc 7>,
> +                                             <&cpu29_intc 7>,
> +                                             <&cpu30_intc 7>,
> +                                             <&cpu31_intc 7>;
> +               };
> +
> +               clint_mtimer8: timer@70ac080000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu32_intc 7>,
> +                                             <&cpu33_intc 7>,
> +                                             <&cpu34_intc 7>,
> +                                             <&cpu35_intc 7>;
> +               };
> +
> +               clint_mtimer9: timer@70ac090000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu36_intc 7>,
> +                                             <&cpu37_intc 7>,
> +                                             <&cpu38_intc 7>,
> +                                             <&cpu39_intc 7>;
> +               };
> +
> +               clint_mtimer10: timer@70ac0a0000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu40_intc 7>,
> +                                             <&cpu41_intc 7>,
> +                                             <&cpu42_intc 7>,
> +                                             <&cpu43_intc 7>;
> +               };
> +
> +               clint_mtimer11: timer@70ac0b0000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu44_intc 7>,
> +                                             <&cpu45_intc 7>,
> +                                             <&cpu46_intc 7>,
> +                                             <&cpu47_intc 7>;
> +               };
> +
> +               clint_mtimer12: timer@70ac0c0000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu48_intc 7>,
> +                                             <&cpu49_intc 7>,
> +                                             <&cpu50_intc 7>,
> +                                             <&cpu51_intc 7>;
> +               };
> +
> +               clint_mtimer13: timer@70ac0d0000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu52_intc 7>,
> +                                             <&cpu53_intc 7>,
> +                                             <&cpu54_intc 7>,
> +                                             <&cpu55_intc 7>;
> +               };
> +
> +               clint_mtimer14: timer@70ac0e0000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu56_intc 7>,
> +                                             <&cpu57_intc 7>,
> +                                             <&cpu58_intc 7>,
> +                                             <&cpu59_intc 7>;
> +               };
> +
> +               clint_mtimer15: timer@70ac0f0000 {
> +                       compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +                       reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
> +                       interrupts-extended = <&cpu60_intc 7>,
> +                                             <&cpu61_intc 7>,
> +                                             <&cpu62_intc 7>,
> +                                             <&cpu63_intc 7>;
> +               };
> +
> +               intc: interrupt-controller@7090000000 {
> +                       compatible = "sophgo,sg2042-plic", "thead,c900-plic";
> +                       #address-cells = <0>;
> +                       #interrupt-cells = <2>;
> +                       reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
> +                       interrupt-controller;
> +                       interrupts-extended =
> +                               <&cpu0_intc 0xffffffff>,  <&cpu0_intc 9>,
> +                               <&cpu1_intc 0xffffffff>,  <&cpu1_intc 9>,
> +                               <&cpu2_intc 0xffffffff>,  <&cpu2_intc 9>,
> +                               <&cpu3_intc 0xffffffff>,  <&cpu3_intc 9>,
> +                               <&cpu4_intc 0xffffffff>,  <&cpu4_intc 9>,
> +                               <&cpu5_intc 0xffffffff>,  <&cpu5_intc 9>,
> +                               <&cpu6_intc 0xffffffff>,  <&cpu6_intc 9>,
> +                               <&cpu7_intc 0xffffffff>,  <&cpu7_intc 9>,
> +                               <&cpu8_intc 0xffffffff>,  <&cpu8_intc 9>,
> +                               <&cpu9_intc 0xffffffff>,  <&cpu9_intc 9>,
> +                               <&cpu10_intc 0xffffffff>, <&cpu10_intc 9>,
> +                               <&cpu11_intc 0xffffffff>, <&cpu11_intc 9>,
> +                               <&cpu12_intc 0xffffffff>, <&cpu12_intc 9>,
> +                               <&cpu13_intc 0xffffffff>, <&cpu13_intc 9>,
> +                               <&cpu14_intc 0xffffffff>, <&cpu14_intc 9>,
> +                               <&cpu15_intc 0xffffffff>, <&cpu15_intc 9>,
> +                               <&cpu16_intc 0xffffffff>, <&cpu16_intc 9>,
> +                               <&cpu17_intc 0xffffffff>, <&cpu17_intc 9>,
> +                               <&cpu18_intc 0xffffffff>, <&cpu18_intc 9>,
> +                               <&cpu19_intc 0xffffffff>, <&cpu19_intc 9>,
> +                               <&cpu20_intc 0xffffffff>, <&cpu20_intc 9>,
> +                               <&cpu21_intc 0xffffffff>, <&cpu21_intc 9>,
> +                               <&cpu22_intc 0xffffffff>, <&cpu22_intc 9>,
> +                               <&cpu23_intc 0xffffffff>, <&cpu23_intc 9>,
> +                               <&cpu24_intc 0xffffffff>, <&cpu24_intc 9>,
> +                               <&cpu25_intc 0xffffffff>, <&cpu25_intc 9>,
> +                               <&cpu26_intc 0xffffffff>, <&cpu26_intc 9>,
> +                               <&cpu27_intc 0xffffffff>, <&cpu27_intc 9>,
> +                               <&cpu28_intc 0xffffffff>, <&cpu28_intc 9>,
> +                               <&cpu29_intc 0xffffffff>, <&cpu29_intc 9>,
> +                               <&cpu30_intc 0xffffffff>, <&cpu30_intc 9>,
> +                               <&cpu31_intc 0xffffffff>, <&cpu31_intc 9>,
> +                               <&cpu32_intc 0xffffffff>, <&cpu32_intc 9>,
> +                               <&cpu33_intc 0xffffffff>, <&cpu33_intc 9>,
> +                               <&cpu34_intc 0xffffffff>, <&cpu34_intc 9>,
> +                               <&cpu35_intc 0xffffffff>, <&cpu35_intc 9>,
> +                               <&cpu36_intc 0xffffffff>, <&cpu36_intc 9>,
> +                               <&cpu37_intc 0xffffffff>, <&cpu37_intc 9>,
> +                               <&cpu38_intc 0xffffffff>, <&cpu38_intc 9>,
> +                               <&cpu39_intc 0xffffffff>, <&cpu39_intc 9>,
> +                               <&cpu40_intc 0xffffffff>, <&cpu40_intc 9>,
> +                               <&cpu41_intc 0xffffffff>, <&cpu41_intc 9>,
> +                               <&cpu42_intc 0xffffffff>, <&cpu42_intc 9>,
> +                               <&cpu43_intc 0xffffffff>, <&cpu43_intc 9>,
> +                               <&cpu44_intc 0xffffffff>, <&cpu44_intc 9>,
> +                               <&cpu45_intc 0xffffffff>, <&cpu45_intc 9>,
> +                               <&cpu46_intc 0xffffffff>, <&cpu46_intc 9>,
> +                               <&cpu47_intc 0xffffffff>, <&cpu47_intc 9>,
> +                               <&cpu48_intc 0xffffffff>, <&cpu48_intc 9>,
> +                               <&cpu49_intc 0xffffffff>, <&cpu49_intc 9>,
> +                               <&cpu50_intc 0xffffffff>, <&cpu50_intc 9>,
> +                               <&cpu51_intc 0xffffffff>, <&cpu51_intc 9>,
> +                               <&cpu52_intc 0xffffffff>, <&cpu52_intc 9>,
> +                               <&cpu53_intc 0xffffffff>, <&cpu53_intc 9>,
> +                               <&cpu54_intc 0xffffffff>, <&cpu54_intc 9>,
> +                               <&cpu55_intc 0xffffffff>, <&cpu55_intc 9>,
> +                               <&cpu56_intc 0xffffffff>, <&cpu56_intc 9>,
> +                               <&cpu57_intc 0xffffffff>, <&cpu57_intc 9>,
> +                               <&cpu58_intc 0xffffffff>, <&cpu58_intc 9>,
> +                               <&cpu59_intc 0xffffffff>, <&cpu59_intc 9>,
> +                               <&cpu60_intc 0xffffffff>, <&cpu60_intc 9>,
> +                               <&cpu61_intc 0xffffffff>, <&cpu61_intc 9>,
> +                               <&cpu62_intc 0xffffffff>, <&cpu62_intc 9>,
> +                               <&cpu63_intc 0xffffffff>, <&cpu63_intc 9>;
> +                       riscv,ndev = <224>;
> +               };
> +
> +               uart0: serial@7040000000 {
> +                       compatible = "sophgo,sg2042-uart", "snps,dw-apb-uart";
> +                       reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
> +                       interrupt-parent = <&intc>;
> +                       interrupts = <SOC_PERIPHERAL_IRQ(112) IRQ_TYPE_LEVEL_HIGH>;
> +                       clock-frequency = <500000000>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       status = "disabled";
> +               };
> +       };
> +};
> --
> 2.25.1
>
Thx for the job on clint-mtimer & clint-mswi.
LGTM

Reviewed-by: Guo Ren <guoren@kernel.org>


-- 
Best Regards
 Guo Ren

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
  2023-09-20  6:40 ` [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree Chen Wang
  2023-09-20  8:04   ` Guo Ren
@ 2023-09-20  8:57   ` Conor Dooley
  2023-09-21  9:56     ` Chen Wang
  2023-09-20 11:32   ` Emil Renner Berthing
  2023-09-20 15:19   ` Palmer Dabbelt
  3 siblings, 1 reply; 67+ messages in thread
From: Conor Dooley @ 2023-09-20  8:57 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang,
	Inochi Amaoto

[-- Attachment #1: Type: text/plain, Size: 3479 bytes --]

Yo,

On Wed, Sep 20, 2023 at 02:40:32PM +0800, Chen Wang wrote:
> Milk-V Pioneer motherboard is powered by SOPHON's SG2042.
> 
> SG2042 is server grade chip with high performance, low power
> consumption and high data throughput.
> Key features:
> - 64 RISC-V cpu cores which implements IMAFDC

That's not quite true though, is it?

> - 4 cores per cluster, 16 clusters on chip
> - ......

What's a "....."? ;)

> 
> More info is available at [1].
> 
> [1]: https://en.sophgo.com/product/introduce/sg2042.html

Link: please.

> Currently only support booting into console with only uart,
> other features will be added soon later.
> 
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>

There are 4 sign-offs here. Surely some of these should be
co-developed-bys?

> +		cpu0: cpu@0 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";

Please also add riscv,isa-base & riscv,isa-extensions.

> +			reg = <0>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache0>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu0_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};

> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> new file mode 100644
> index 000000000000..747fd9764c95
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -0,0 +1,439 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT

You should add () around the GPL-2.0 OR MIT.

> +/*
> + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +#include "sg2042-cpus.dtsi"
> +
> +#define SOC_PERIPHERAL_IRQ(nr) (nr)

Why? What does this do? Where was it copied from?

> +
> +/ {
> +	compatible = "sophgo,sg2042";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	dma-noncoherent;
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	/* the mem node will be updated by ZSBL. */

huh? So these are random numbers below? Either put something useful here
or delete it please.

> +	memory@0 {
> +		device_type = "memory";
> +		reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
> +	};
> +
> +	memory@1 {
> +		device_type = "memory";
> +		reg = <0x00000000 0x00000001 0x00000000 0x00000000>;
> +	};
> +
> +	memory@2 {
> +		device_type = "memory";
> +		reg = <0x00000000 0x00000002 0x00000000 0x00000000>;
> +	};
> +
> +	memory@3 {
> +		device_type = "memory";
> +		reg = <0x00000000 0x00000003 0x00000000 0x00000000>;
> +	};

> +	soc: soc {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		clint_mswi: interrupt-controller@7094000000 {
> +			compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi";
> +			reg = <0x00000070 0x94000000 0x00000000 0x00004000>;

& nak to this without further explanation!

Thanks,
Conor.


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^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
  2023-09-20  8:57   ` Conor Dooley
@ 2023-09-21  9:56     ` Chen Wang
  2023-09-21 10:15       ` Conor Dooley
  0 siblings, 1 reply; 67+ messages in thread
From: Chen Wang @ 2023-09-21  9:56 UTC (permalink / raw)
  To: Conor Dooley
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang,
	Inochi Amaoto

Regards,

unicornx

Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 16:58写道：
>
> Yo,
>
> On Wed, Sep 20, 2023 at 02:40:32PM +0800, Chen Wang wrote:
> > Milk-V Pioneer motherboard is powered by SOPHON's SG2042.
> >
> > SG2042 is server grade chip with high performance, low power
> > consumption and high data throughput.
> > Key features:
> > - 64 RISC-V cpu cores which implements IMAFDC
>
> That's not quite true though, is it?

The cpu cores of SG2042 is c902 from T-HEAD, it supports vector, but
it's v0.7, not official v1.0. If we declare it as supporting
v-extension, the latest kernel(since 6.5) will issue rvv1.0
instructions during booting and make c902 crash. So we have to remove
"v" from the capability of ISA to pass the booting of machine. You can
check the "riscv,isa = "rv64imafdc";" in DTS.

>
> > - 4 cores per cluster, 16 clusters on chip
> > - ......
>
> What's a "....."? ;)
I just cited a description from TRM of SG2042 and it looks too long. I
will give a better description here and avoid using "......" in the
next revision.

>
> >
> > More info is available at [1].
> >
> > [1]: https://en.sophgo.com/product/introduce/sg2042.html
>
> Link: please.
>
> > Currently only support booting into console with only uart,
> > other features will be added soon later.
> >
> > Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
>
> There are 4 sign-offs here. Surely some of these should be
> co-developed-bys?
>
> > +             cpu0: cpu@0 {
> > +                     compatible = "thead,c920", "riscv";
> > +                     device_type = "cpu";
> > +                     riscv,isa = "rv64imafdc";
>
> Please also add riscv,isa-base & riscv,isa-extensions.
>
> > +                     reg = <0>;
> > +                     i-cache-block-size = <64>;
> > +                     i-cache-size = <65536>;
> > +                     i-cache-sets = <512>;
> > +                     d-cache-block-size = <64>;
> > +                     d-cache-size = <65536>;
> > +                     d-cache-sets = <512>;
> > +                     next-level-cache = <&l2_cache0>;
> > +                     mmu-type = "riscv,sv39";
> > +
> > +                     cpu0_intc: interrupt-controller {
> > +                             compatible = "riscv,cpu-intc";
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <1>;
> > +                     };
> > +             };
>
> > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > new file mode 100644
> > index 000000000000..747fd9764c95
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > @@ -0,0 +1,439 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
>
> You should add () around the GPL-2.0 OR MIT.
>
> > +/*
> > + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> > + */
> > +
> > +/dts-v1/;
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +#include "sg2042-cpus.dtsi"
> > +
> > +#define SOC_PERIPHERAL_IRQ(nr) (nr)
>
> Why? What does this do? Where was it copied from?
>
It should be unnecessary， I will remove it in the next revision.

> > +
> > +/ {
> > +     compatible = "sophgo,sg2042";
> > +     #address-cells = <2>;
> > +     #size-cells = <2>;
> > +     dma-noncoherent;
> > +
> > +     aliases {
> > +             serial0 = &uart0;
> > +     };
> > +
> > +     /* the mem node will be updated by ZSBL. */
>
> huh? So these are random numbers below? Either put something useful here
> or delete it please.

The memory for SG2042 is not fixed, the bootloader will detect memory
installed on board during booting and fill the actual address and size
in the memory node. The comment " /* the mem node will be updated by
ZSBL. */" is telling this.
We write memory nodes like this to make them act just as placeholders
and the value is by default written as zero.


>
> > +     memory@0 {
> > +             device_type = "memory";
> > +             reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
> > +     };
> > +
> > +     memory@1 {
> > +             device_type = "memory";
> > +             reg = <0x00000000 0x00000001 0x00000000 0x00000000>;
> > +     };
> > +
> > +     memory@2 {
> > +             device_type = "memory";
> > +             reg = <0x00000000 0x00000002 0x00000000 0x00000000>;
> > +     };
> > +
> > +     memory@3 {
> > +             device_type = "memory";
> > +             reg = <0x00000000 0x00000003 0x00000000 0x00000000>;
> > +     };
>
> > +     soc: soc {
> > +             compatible = "simple-bus";
> > +             #address-cells = <2>;
> > +             #size-cells = <2>;
> > +             ranges;
> > +
> > +             clint_mswi: interrupt-controller@7094000000 {
> > +                     compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi";
> > +                     reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
>
> & nak to this without further explanation!
>
> Thanks,
> Conor.
>

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
  2023-09-21  9:56     ` Chen Wang
@ 2023-09-21 10:15       ` Conor Dooley
  2023-09-21 10:27         ` Chen Wang
  0 siblings, 1 reply; 67+ messages in thread
From: Conor Dooley @ 2023-09-21 10:15 UTC (permalink / raw)
  To: Chen Wang
  Cc: Conor Dooley, aou, chao.wei, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing,
	Chen Wang, Inochi Amaoto

[-- Attachment #1: Type: text/plain, Size: 6378 bytes --]

On Thu, Sep 21, 2023 at 05:56:28PM +0800, Chen Wang wrote:
> Regards,
> 
> unicornx
> 
> Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 16:58写道：
> >
> > Yo,
> >
> > On Wed, Sep 20, 2023 at 02:40:32PM +0800, Chen Wang wrote:
> > > Milk-V Pioneer motherboard is powered by SOPHON's SG2042.
> > >
> > > SG2042 is server grade chip with high performance, low power
> > > consumption and high data throughput.
> > > Key features:
> > > - 64 RISC-V cpu cores which implements IMAFDC
> >
> > That's not quite true though, is it?
> 
> The cpu cores of SG2042 is c902 from T-HEAD, it supports vector, but
> it's v0.7, not official v1.0. If we declare it as supporting
> v-extension, the latest kernel(since 6.5) will issue rvv1.0
> instructions during booting and make c902 crash. So we have to remove
> "v" from the capability of ISA to pass the booting of machine. You can
> check the "riscv,isa = "rv64imafdc";" in DTS.

I know all of this, not my first rodeo looking at stuff using T-Head
cores ;)
What I meant was, imafdc is only a subset of what is supported,
there are other things like the T-Head bitmanip extensions too, right?
I'm not asking for it to be listed in the devicetree (yet), just
actually curious what else is on the c920 as I do not speak a language
that allows me to read the documentation for the cpu that I have been
able to find online.

> > > - 4 cores per cluster, 16 clusters on chip
> > > - ......
> >
> > What's a "....."? ;)
> I just cited a description from TRM of SG2042 and it looks too long. I
> will give a better description here and avoid using "......" in the
> next revision.
> 
> >
> > >
> > > More info is available at [1].
> > >
> > > [1]: https://en.sophgo.com/product/introduce/sg2042.html
> >
> > Link: please.
> >
> > > Currently only support booting into console with only uart,
> > > other features will be added soon later.
> > >
> > > Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > > Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > > Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> >
> > There are 4 sign-offs here. Surely some of these should be
> > co-developed-bys?
> >
> > > +             cpu0: cpu@0 {
> > > +                     compatible = "thead,c920", "riscv";
> > > +                     device_type = "cpu";
> > > +                     riscv,isa = "rv64imafdc";
> >
> > Please also add riscv,isa-base & riscv,isa-extensions.
> >
> > > +                     reg = <0>;
> > > +                     i-cache-block-size = <64>;
> > > +                     i-cache-size = <65536>;
> > > +                     i-cache-sets = <512>;
> > > +                     d-cache-block-size = <64>;
> > > +                     d-cache-size = <65536>;
> > > +                     d-cache-sets = <512>;
> > > +                     next-level-cache = <&l2_cache0>;
> > > +                     mmu-type = "riscv,sv39";
> > > +
> > > +                     cpu0_intc: interrupt-controller {
> > > +                             compatible = "riscv,cpu-intc";
> > > +                             interrupt-controller;
> > > +                             #interrupt-cells = <1>;
> > > +                     };
> > > +             };
> >
> > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > > new file mode 100644
> > > index 000000000000..747fd9764c95
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > > @@ -0,0 +1,439 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> >
> > You should add () around the GPL-2.0 OR MIT.
> >
> > > +/*
> > > + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> > > + */
> > > +
> > > +/dts-v1/;
> > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > +
> > > +#include "sg2042-cpus.dtsi"
> > > +
> > > +#define SOC_PERIPHERAL_IRQ(nr) (nr)
> >
> > Why? What does this do? Where was it copied from?
> >
> It should be unnecessary， I will remove it in the next revision.
> 
> > > +
> > > +/ {
> > > +     compatible = "sophgo,sg2042";
> > > +     #address-cells = <2>;
> > > +     #size-cells = <2>;
> > > +     dma-noncoherent;
> > > +
> > > +     aliases {
> > > +             serial0 = &uart0;
> > > +     };
> > > +
> > > +     /* the mem node will be updated by ZSBL. */
> >
> > huh? So these are random numbers below? Either put something useful here
> > or delete it please.
> 
> The memory for SG2042 is not fixed, the bootloader will detect memory
> installed on board during booting and fill the actual address and size
> in the memory node. The comment " /* the mem node will be updated by
> ZSBL. */" is telling this.

Yes, I read the comment!

> We write memory nodes like this to make them act just as placeholders
> and the value is by default written as zero.

Why knowingly add something that is wrong, rather than omitting them
entirely?

Thanks,
Conor.

> 
> 
> >
> > > +     memory@0 {
> > > +             device_type = "memory";
> > > +             reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
> > > +     };
> > > +
> > > +     memory@1 {
> > > +             device_type = "memory";
> > > +             reg = <0x00000000 0x00000001 0x00000000 0x00000000>;
> > > +     };
> > > +
> > > +     memory@2 {
> > > +             device_type = "memory";
> > > +             reg = <0x00000000 0x00000002 0x00000000 0x00000000>;
> > > +     };
> > > +
> > > +     memory@3 {
> > > +             device_type = "memory";
> > > +             reg = <0x00000000 0x00000003 0x00000000 0x00000000>;
> > > +     };
> >
> > > +     soc: soc {
> > > +             compatible = "simple-bus";
> > > +             #address-cells = <2>;
> > > +             #size-cells = <2>;
> > > +             ranges;
> > > +
> > > +             clint_mswi: interrupt-controller@7094000000 {
> > > +                     compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi";
> > > +                     reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
> >
> > & nak to this without further explanation!
> >
> > Thanks,
> > Conor.
> >

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^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
  2023-09-21 10:15       ` Conor Dooley
@ 2023-09-21 10:27         ` Chen Wang
  2023-09-21 12:06           ` Conor Dooley
  0 siblings, 1 reply; 67+ messages in thread
From: Chen Wang @ 2023-09-21 10:27 UTC (permalink / raw)
  To: Conor Dooley
  Cc: Conor Dooley, aou, chao.wei, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing,
	Chen Wang, Inochi Amaoto

Regards,

unicornx

Conor Dooley <conor@kernel.org> 于2023年9月21日周四 18:15写道：
>
> On Thu, Sep 21, 2023 at 05:56:28PM +0800, Chen Wang wrote:
> > Regards,
> >
> > unicornx
> >
......
> > > > +
> > > > +/ {
> > > > +     compatible = "sophgo,sg2042";
> > > > +     #address-cells = <2>;
> > > > +     #size-cells = <2>;
> > > > +     dma-noncoherent;
> > > > +
> > > > +     aliases {
> > > > +             serial0 = &uart0;
> > > > +     };
> > > > +
> > > > +     /* the mem node will be updated by ZSBL. */
> > >
> > > huh? So these are random numbers below? Either put something useful here
> > > or delete it please.
> >
> > The memory for SG2042 is not fixed, the bootloader will detect memory
> > installed on board during booting and fill the actual address and size
> > in the memory node. The comment " /* the mem node will be updated by
> > ZSBL. */" is telling this.
>
> Yes, I read the comment!
>
> > We write memory nodes like this to make them act just as placeholders
> > and the value is by default written as zero.
>
> Why knowingly add something that is wrong, rather than omitting them
> entirely?
>
> Thanks,
> Conor.
>

We learn this from arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts,
it writes DTS as following:

```
        memory@0 {
                device_type = "memory";
                /* rewrite this at bootloader */
                reg = <0x0 0x0 0x0 0x0>;
        };
```
So you mean we can totally remove the memory nodes in DTS and make
bootloader add it by itself? That sounds a good idea, I will have a
try. I used to think memory nodes are must-have in DTS.


> >
> >
> > >
> > > > +     memory@0 {
> > > > +             device_type = "memory";
> > > > +             reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
> > > > +     };
> > > > +

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
  2023-09-21 10:27         ` Chen Wang
@ 2023-09-21 12:06           ` Conor Dooley
  0 siblings, 0 replies; 67+ messages in thread
From: Conor Dooley @ 2023-09-21 12:06 UTC (permalink / raw)
  To: Chen Wang
  Cc: Conor Dooley, aou, chao.wei, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing,
	Chen Wang, Inochi Amaoto

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On Thu, Sep 21, 2023 at 06:27:09PM +0800, Chen Wang wrote:
> Conor Dooley <conor@kernel.org> 于2023年9月21日周四 18:15写道：
> >
> > On Thu, Sep 21, 2023 at 05:56:28PM +0800, Chen Wang wrote:

> > > > > +
> > > > > +/ {
> > > > > +     compatible = "sophgo,sg2042";
> > > > > +     #address-cells = <2>;
> > > > > +     #size-cells = <2>;
> > > > > +     dma-noncoherent;
> > > > > +
> > > > > +     aliases {
> > > > > +             serial0 = &uart0;
> > > > > +     };
> > > > > +
> > > > > +     /* the mem node will be updated by ZSBL. */
> > > >
> > > > huh? So these are random numbers below? Either put something useful here
> > > > or delete it please.
> > >
> > > The memory for SG2042 is not fixed, the bootloader will detect memory
> > > installed on board during booting and fill the actual address and size
> > > in the memory node. The comment " /* the mem node will be updated by
> > > ZSBL. */" is telling this.
> >
> > Yes, I read the comment!
> >
> > > We write memory nodes like this to make them act just as placeholders
> > > and the value is by default written as zero.
> >
> > Why knowingly add something that is wrong, rather than omitting them
> > entirely?
> 
> We learn this from arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts,
> it writes DTS as following:
> 
> ```
>         memory@0 {
>                 device_type = "memory";
>                 /* rewrite this at bootloader */
>                 reg = <0x0 0x0 0x0 0x0>;
>         };
> ```
> So you mean we can totally remove the memory nodes in DTS and make
> bootloader add it by itself? That sounds a good idea, I will have a
> try. I used to think memory nodes are must-have in DTS.

AFAIR, the ones for the d1 based systems (like the nezha I have) don't
have a memory node at all.

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^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
  2023-09-20  6:40 ` [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree Chen Wang
  2023-09-20  8:04   ` Guo Ren
  2023-09-20  8:57   ` Conor Dooley
@ 2023-09-20 11:32   ` Emil Renner Berthing
  2023-09-20 12:09     ` 汪辰
  2023-09-20 15:19   ` Palmer Dabbelt
  3 siblings, 1 reply; 67+ messages in thread
From: Emil Renner Berthing @ 2023-09-20 11:32 UTC (permalink / raw)
  To: Chen Wang, aou, chao.wei, conor, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang, Inochi Amaoto

Chen Wang wrote:
> Milk-V Pioneer motherboard is powered by SOPHON's SG2042.

Hi,

I'm just wondering what is the relation between SOPHON and SOPHGO?
I think most of the content refers to the SoC as Sophgo SG2042 or SOPHGO
SG2042, but here you're using SOPHON.

Also it would be great if you could decide if it's spelled SOPHGO or Sophgo and
be consistent in all these patches.

/Emil

>
> SG2042 is server grade chip with high performance, low power
> consumption and high data throughput.
> Key features:
> - 64 RISC-V cpu cores which implements IMAFDC
> - 4 cores per cluster, 16 clusters on chip
> - ......
>
> More info is available at [1].
>
> [1]: https://en.sophgo.com/product/introduce/sg2042.html
>
> Currently only support booting into console with only uart,
> other features will be added soon later.
>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1744 +++++++++++++++++++
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi      |  439 +++++
>  2 files changed, 2183 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> new file mode 100644
> index 000000000000..9fc79b1cf3bf
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> @@ -0,0 +1,1744 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +/ {
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <50000000>;
> +
> +		cpu-map {
> +			socket0 {
> +				cluster0 {
> +					 core0 {
> +						cpu = <&cpu0>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu1>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu2>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu3>;
> +					 };
> +				};
> +
> +				cluster1 {
> +					 core0 {
> +						cpu = <&cpu4>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu5>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu6>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu7>;
> +					 };
> +				};
> +
> +				cluster2 {
> +					 core0 {
> +						cpu = <&cpu16>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu17>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu18>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu19>;
> +					 };
> +				};
> +
> +				cluster3 {
> +					 core0 {
> +						cpu = <&cpu20>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu21>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu22>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu23>;
> +					 };
> +				};
> +
> +				cluster4 {
> +					 core0 {
> +						cpu = <&cpu8>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu9>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu10>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu11>;
> +					 };
> +				};
> +
> +				cluster5 {
> +					 core0 {
> +						cpu = <&cpu12>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu13>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu14>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu15>;
> +					 };
> +				};
> +
> +				cluster6 {
> +					 core0 {
> +						cpu = <&cpu24>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu25>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu26>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu27>;
> +					 };
> +				};
> +
> +				cluster7 {
> +					 core0 {
> +						cpu = <&cpu28>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu29>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu30>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu31>;
> +					 };
> +				};
> +
> +				cluster8 {
> +					 core0 {
> +						cpu = <&cpu32>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu33>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu34>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu35>;
> +					 };
> +				};
> +
> +				cluster9 {
> +					 core0 {
> +						cpu = <&cpu36>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu37>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu38>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu39>;
> +					 };
> +				};
> +
> +				cluster10 {
> +					 core0 {
> +						cpu = <&cpu48>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu49>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu50>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu51>;
> +					 };
> +				};
> +
> +				cluster11 {
> +					 core0 {
> +						cpu = <&cpu52>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu53>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu54>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu55>;
> +					 };
> +				};
> +
> +				cluster12 {
> +					 core0 {
> +						cpu = <&cpu40>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu41>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu42>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu43>;
> +					 };
> +				};
> +
> +				cluster13 {
> +					 core0 {
> +						cpu = <&cpu44>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu45>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu46>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu47>;
> +					 };
> +				};
> +
> +				cluster14 {
> +					 core0 {
> +						cpu = <&cpu56>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu57>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu58>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu59>;
> +					 };
> +				};
> +
> +				cluster15 {
> +					 core0 {
> +						cpu = <&cpu60>;
> +					 };
> +					 core1 {
> +						cpu = <&cpu61>;
> +					 };
> +					 core2 {
> +						cpu = <&cpu62>;
> +					 };
> +					 core3 {
> +						cpu = <&cpu63>;
> +					 };
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu@0 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <0>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache0>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu0_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu1: cpu@1 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <1>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache0>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu1_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu2: cpu@2 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <2>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache0>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu2_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu3: cpu@3 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <3>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache0>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu3_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu4: cpu@4 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <4>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache1>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu4_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu5: cpu@5 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <5>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache1>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu5_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu6: cpu@6 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <6>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache1>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu6_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu7: cpu@7 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <7>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache1>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu7_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu8: cpu@8 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <8>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache4>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu8_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu9: cpu@9 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <9>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache4>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu9_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu10: cpu@10 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <10>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache4>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu10_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu11: cpu@11 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <11>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache4>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu11_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu12: cpu@12 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <12>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache5>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu12_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu13: cpu@13 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <13>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache5>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu13_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu14: cpu@14 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <14>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache5>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu14_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu15: cpu@15 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <15>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache5>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu15_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu16: cpu@16 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <16>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache2>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu16_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu17: cpu@17 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <17>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache2>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu17_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu18: cpu@18 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <18>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache2>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu18_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu19: cpu@19 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <19>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache2>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu19_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu20: cpu@20 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <20>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache3>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu20_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu21: cpu@21 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <21>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache3>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu21_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu22: cpu@22 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <22>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache3>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu22_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu23: cpu@23 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <23>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache3>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu23_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu24: cpu@24 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <24>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache6>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu24_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu25: cpu@25 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <25>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache6>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu25_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu26: cpu@26 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <26>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache6>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu26_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu27: cpu@27 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <27>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache6>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu27_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu28: cpu@28 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <28>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache7>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu28_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu29: cpu@29 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <29>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache7>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu29_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu30: cpu@30 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <30>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache7>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu30_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu31: cpu@31 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <31>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache7>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu31_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu32: cpu@32 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <32>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache8>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu32_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu33: cpu@33 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <33>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache8>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu33_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu34: cpu@34 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <34>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache8>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu34_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu35: cpu@35 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <35>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache8>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu35_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu36: cpu@36 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <36>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache9>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu36_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu37: cpu@37 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <37>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache9>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu37_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu38: cpu@38 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <38>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache9>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu38_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu39: cpu@39 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <39>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache9>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu39_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu40: cpu@40 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <40>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache12>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu40_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu41: cpu@41 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <41>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache12>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu41_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu42: cpu@42 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <42>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache12>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu42_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu43: cpu@43 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <43>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache12>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu43_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu44: cpu@44 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <44>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache13>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu44_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu45: cpu@45 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <45>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache13>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu45_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu46: cpu@46 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <46>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache13>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu46_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu47: cpu@47 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <47>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache13>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu47_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu48: cpu@48 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <48>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache10>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu48_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu49: cpu@49 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <49>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache10>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu49_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu50: cpu@50 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <50>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache10>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu50_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu51: cpu@51 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <51>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache10>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu51_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu52: cpu@52 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <52>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache11>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu52_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu53: cpu@53 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <53>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache11>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu53_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu54: cpu@54 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <54>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache11>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu54_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu55: cpu@55 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <55>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache11>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu55_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu56: cpu@56 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <56>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache14>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu56_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu57: cpu@57 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <57>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache14>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu57_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu58: cpu@58 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <58>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache14>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu58_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu59: cpu@59 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <59>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache14>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu59_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu60: cpu@60 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <60>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache15>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu60_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu61: cpu@61 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <61>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache15>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu61_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu62: cpu@62 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <62>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache15>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu62_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		cpu63: cpu@63 {
> +			compatible = "thead,c920", "riscv";
> +			device_type = "cpu";
> +			riscv,isa = "rv64imafdc";
> +			reg = <63>;
> +			i-cache-block-size = <64>;
> +			i-cache-size = <65536>;
> +			i-cache-sets = <512>;
> +			d-cache-block-size = <64>;
> +			d-cache-size = <65536>;
> +			d-cache-sets = <512>;
> +			next-level-cache = <&l2_cache15>;
> +			mmu-type = "riscv,sv39";
> +
> +			cpu63_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +
> +		l2_cache0: l2-cache@0 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache1: l2-cache@1 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache2: l2-cache@2 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache3: l2-cache@3 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache4: l2-cache@4 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache5: l2-cache@5 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache6: l2-cache@6 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache7: l2-cache@7 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache8: l2-cache@8 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache9: l2-cache@9 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache10: l2-cache@10 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache11: l2-cache@11 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache12: l2-cache@12 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache13: l2-cache@13 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache14: l2-cache@14 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +
> +		l2_cache15: l2-cache@15 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-size = <1048576>;
> +			cache-sets = <1024>;
> +			cache-unified;
> +		};
> +	};
> +};
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> new file mode 100644
> index 000000000000..747fd9764c95
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -0,0 +1,439 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +#include "sg2042-cpus.dtsi"
> +
> +#define SOC_PERIPHERAL_IRQ(nr) (nr)
> +
> +/ {
> +	compatible = "sophgo,sg2042";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +	dma-noncoherent;
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	/* the mem node will be updated by ZSBL. */
> +	memory@0 {
> +		device_type = "memory";
> +		reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
> +	};
> +
> +	memory@1 {
> +		device_type = "memory";
> +		reg = <0x00000000 0x00000001 0x00000000 0x00000000>;
> +	};
> +
> +	memory@2 {
> +		device_type = "memory";
> +		reg = <0x00000000 0x00000002 0x00000000 0x00000000>;
> +	};
> +
> +	memory@3 {
> +		device_type = "memory";
> +		reg = <0x00000000 0x00000003 0x00000000 0x00000000>;
> +	};
> +
> +	pmu {
> +		compatible = "riscv,pmu";
> +		riscv,event-to-mhpmevent =
> +			<0x00003 0x00000000 0x00000010>,
> +			<0x00004 0x00000000 0x00000011>,
> +			<0x00005 0x00000000 0x00000007>,
> +			<0x00006 0x00000000 0x00000006>,
> +			<0x00008 0x00000000 0x00000027>,
> +			<0x00009 0x00000000 0x00000028>,
> +			<0x10000 0x00000000 0x0000000c>,
> +			<0x10001 0x00000000 0x0000000d>,
> +			<0x10002 0x00000000 0x0000000e>,
> +			<0x10003 0x00000000 0x0000000f>,
> +			<0x10008 0x00000000 0x00000001>,
> +			<0x10009 0x00000000 0x00000002>,
> +			<0x10010 0x00000000 0x00000010>,
> +			<0x10011 0x00000000 0x00000011>,
> +			<0x10012 0x00000000 0x00000012>,
> +			<0x10013 0x00000000 0x00000013>,
> +			<0x10019 0x00000000 0x00000004>,
> +			<0x10021 0x00000000 0x00000003>,
> +			<0x10030 0x00000000 0x0000001c>,
> +			<0x10031 0x00000000 0x0000001b>;
> +		riscv,event-to-mhpmcounters =
> +			<0x00003 0x00003 0xfffffff8>,
> +			<0x00004 0x00004 0xfffffff8>,
> +			<0x00005 0x00005 0xfffffff8>,
> +			<0x00006 0x00006 0xfffffff8>,
> +			<0x00007 0x00007 0xfffffff8>,
> +			<0x00008 0x00008 0xfffffff8>,
> +			<0x00009 0x00009 0xfffffff8>,
> +			<0x0000a 0x0000a 0xfffffff8>,
> +			<0x10000 0x10000 0xfffffff8>,
> +			<0x10001 0x10001 0xfffffff8>,
> +			<0x10002 0x10002 0xfffffff8>,
> +			<0x10003 0x10003 0xfffffff8>,
> +			<0x10008 0x10008 0xfffffff8>,
> +			<0x10009 0x10009 0xfffffff8>,
> +			<0x10010 0x10010 0xfffffff8>,
> +			<0x10011 0x10011 0xfffffff8>,
> +			<0x10012 0x10012 0xfffffff8>,
> +			<0x10013 0x10013 0xfffffff8>,
> +			<0x10019 0x10019 0xfffffff8>,
> +			<0x10021 0x10021 0xfffffff8>,
> +			<0x10030 0x10030 0xfffffff8>,
> +			<0x10031 0x10031 0xfffffff8>;
> +		riscv,raw-event-to-mhpmcounters =
> +			<0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>,
> +			<0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>;
> +	};
> +
> +	soc: soc {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		clint_mswi: interrupt-controller@7094000000 {
> +			compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi";
> +			reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
> +			interrupts-extended = <&cpu0_intc 3>,
> +					      <&cpu1_intc 3>,
> +					      <&cpu2_intc 3>,
> +					      <&cpu3_intc 3>,
> +					      <&cpu4_intc 3>,
> +					      <&cpu5_intc 3>,
> +					      <&cpu6_intc 3>,
> +					      <&cpu7_intc 3>,
> +					      <&cpu8_intc 3>,
> +					      <&cpu9_intc 3>,
> +					      <&cpu10_intc 3>,
> +					      <&cpu11_intc 3>,
> +					      <&cpu12_intc 3>,
> +					      <&cpu13_intc 3>,
> +					      <&cpu14_intc 3>,
> +					      <&cpu15_intc 3>,
> +					      <&cpu16_intc 3>,
> +					      <&cpu17_intc 3>,
> +					      <&cpu18_intc 3>,
> +					      <&cpu19_intc 3>,
> +					      <&cpu20_intc 3>,
> +					      <&cpu21_intc 3>,
> +					      <&cpu22_intc 3>,
> +					      <&cpu23_intc 3>,
> +					      <&cpu24_intc 3>,
> +					      <&cpu25_intc 3>,
> +					      <&cpu26_intc 3>,
> +					      <&cpu27_intc 3>,
> +					      <&cpu28_intc 3>,
> +					      <&cpu29_intc 3>,
> +					      <&cpu30_intc 3>,
> +					      <&cpu31_intc 3>,
> +					      <&cpu32_intc 3>,
> +					      <&cpu33_intc 3>,
> +					      <&cpu34_intc 3>,
> +					      <&cpu35_intc 3>,
> +					      <&cpu36_intc 3>,
> +					      <&cpu37_intc 3>,
> +					      <&cpu38_intc 3>,
> +					      <&cpu39_intc 3>,
> +					      <&cpu40_intc 3>,
> +					      <&cpu41_intc 3>,
> +					      <&cpu42_intc 3>,
> +					      <&cpu43_intc 3>,
> +					      <&cpu44_intc 3>,
> +					      <&cpu45_intc 3>,
> +					      <&cpu46_intc 3>,
> +					      <&cpu47_intc 3>,
> +					      <&cpu48_intc 3>,
> +					      <&cpu49_intc 3>,
> +					      <&cpu50_intc 3>,
> +					      <&cpu51_intc 3>,
> +					      <&cpu52_intc 3>,
> +					      <&cpu53_intc 3>,
> +					      <&cpu54_intc 3>,
> +					      <&cpu55_intc 3>,
> +					      <&cpu56_intc 3>,
> +					      <&cpu57_intc 3>,
> +					      <&cpu58_intc 3>,
> +					      <&cpu59_intc 3>,
> +					      <&cpu60_intc 3>,
> +					      <&cpu61_intc 3>,
> +					      <&cpu62_intc 3>,
> +					      <&cpu63_intc 3>;
> +		};
> +
> +		clint_mtimer0: timer@70ac000000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu0_intc 7>,
> +					      <&cpu1_intc 7>,
> +					      <&cpu2_intc 7>,
> +					      <&cpu3_intc 7>;
> +		};
> +
> +		clint_mtimer1: timer@70ac010000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu4_intc 7>,
> +					      <&cpu5_intc 7>,
> +					      <&cpu6_intc 7>,
> +					      <&cpu7_intc 7>;
> +		};
> +
> +		clint_mtimer2: timer@70ac020000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu8_intc 7>,
> +					      <&cpu9_intc 7>,
> +					      <&cpu10_intc 7>,
> +					      <&cpu11_intc 7>;
> +		};
> +
> +		clint_mtimer3: timer@70ac030000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu12_intc 7>,
> +					      <&cpu13_intc 7>,
> +					      <&cpu14_intc 7>,
> +					      <&cpu15_intc 7>;
> +		};
> +
> +		clint_mtimer4: timer@70ac040000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu16_intc 7>,
> +					      <&cpu17_intc 7>,
> +					      <&cpu18_intc 7>,
> +					      <&cpu19_intc 7>;
> +		};
> +
> +		clint_mtimer5: timer@70ac050000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu20_intc 7>,
> +					      <&cpu21_intc 7>,
> +					      <&cpu22_intc 7>,
> +					      <&cpu23_intc 7>;
> +		};
> +
> +		clint_mtimer6: timer@70ac060000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu24_intc 7>,
> +					      <&cpu25_intc 7>,
> +					      <&cpu26_intc 7>,
> +					      <&cpu27_intc 7>;
> +		};
> +
> +		clint_mtimer7: timer@70ac070000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu28_intc 7>,
> +					      <&cpu29_intc 7>,
> +					      <&cpu30_intc 7>,
> +					      <&cpu31_intc 7>;
> +		};
> +
> +		clint_mtimer8: timer@70ac080000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu32_intc 7>,
> +					      <&cpu33_intc 7>,
> +					      <&cpu34_intc 7>,
> +					      <&cpu35_intc 7>;
> +		};
> +
> +		clint_mtimer9: timer@70ac090000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu36_intc 7>,
> +					      <&cpu37_intc 7>,
> +					      <&cpu38_intc 7>,
> +					      <&cpu39_intc 7>;
> +		};
> +
> +		clint_mtimer10: timer@70ac0a0000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu40_intc 7>,
> +					      <&cpu41_intc 7>,
> +					      <&cpu42_intc 7>,
> +					      <&cpu43_intc 7>;
> +		};
> +
> +		clint_mtimer11: timer@70ac0b0000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu44_intc 7>,
> +					      <&cpu45_intc 7>,
> +					      <&cpu46_intc 7>,
> +					      <&cpu47_intc 7>;
> +		};
> +
> +		clint_mtimer12: timer@70ac0c0000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu48_intc 7>,
> +					      <&cpu49_intc 7>,
> +					      <&cpu50_intc 7>,
> +					      <&cpu51_intc 7>;
> +		};
> +
> +		clint_mtimer13: timer@70ac0d0000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu52_intc 7>,
> +					      <&cpu53_intc 7>,
> +					      <&cpu54_intc 7>,
> +					      <&cpu55_intc 7>;
> +		};
> +
> +		clint_mtimer14: timer@70ac0e0000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu56_intc 7>,
> +					      <&cpu57_intc 7>,
> +					      <&cpu58_intc 7>,
> +					      <&cpu59_intc 7>;
> +		};
> +
> +		clint_mtimer15: timer@70ac0f0000 {
> +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> +			reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
> +			interrupts-extended = <&cpu60_intc 7>,
> +					      <&cpu61_intc 7>,
> +					      <&cpu62_intc 7>,
> +					      <&cpu63_intc 7>;
> +		};
> +
> +		intc: interrupt-controller@7090000000 {
> +			compatible = "sophgo,sg2042-plic", "thead,c900-plic";
> +			#address-cells = <0>;
> +			#interrupt-cells = <2>;
> +			reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
> +			interrupt-controller;
> +			interrupts-extended =
> +				<&cpu0_intc 0xffffffff>,  <&cpu0_intc 9>,
> +				<&cpu1_intc 0xffffffff>,  <&cpu1_intc 9>,
> +				<&cpu2_intc 0xffffffff>,  <&cpu2_intc 9>,
> +				<&cpu3_intc 0xffffffff>,  <&cpu3_intc 9>,
> +				<&cpu4_intc 0xffffffff>,  <&cpu4_intc 9>,
> +				<&cpu5_intc 0xffffffff>,  <&cpu5_intc 9>,
> +				<&cpu6_intc 0xffffffff>,  <&cpu6_intc 9>,
> +				<&cpu7_intc 0xffffffff>,  <&cpu7_intc 9>,
> +				<&cpu8_intc 0xffffffff>,  <&cpu8_intc 9>,
> +				<&cpu9_intc 0xffffffff>,  <&cpu9_intc 9>,
> +				<&cpu10_intc 0xffffffff>, <&cpu10_intc 9>,
> +				<&cpu11_intc 0xffffffff>, <&cpu11_intc 9>,
> +				<&cpu12_intc 0xffffffff>, <&cpu12_intc 9>,
> +				<&cpu13_intc 0xffffffff>, <&cpu13_intc 9>,
> +				<&cpu14_intc 0xffffffff>, <&cpu14_intc 9>,
> +				<&cpu15_intc 0xffffffff>, <&cpu15_intc 9>,
> +				<&cpu16_intc 0xffffffff>, <&cpu16_intc 9>,
> +				<&cpu17_intc 0xffffffff>, <&cpu17_intc 9>,
> +				<&cpu18_intc 0xffffffff>, <&cpu18_intc 9>,
> +				<&cpu19_intc 0xffffffff>, <&cpu19_intc 9>,
> +				<&cpu20_intc 0xffffffff>, <&cpu20_intc 9>,
> +				<&cpu21_intc 0xffffffff>, <&cpu21_intc 9>,
> +				<&cpu22_intc 0xffffffff>, <&cpu22_intc 9>,
> +				<&cpu23_intc 0xffffffff>, <&cpu23_intc 9>,
> +				<&cpu24_intc 0xffffffff>, <&cpu24_intc 9>,
> +				<&cpu25_intc 0xffffffff>, <&cpu25_intc 9>,
> +				<&cpu26_intc 0xffffffff>, <&cpu26_intc 9>,
> +				<&cpu27_intc 0xffffffff>, <&cpu27_intc 9>,
> +				<&cpu28_intc 0xffffffff>, <&cpu28_intc 9>,
> +				<&cpu29_intc 0xffffffff>, <&cpu29_intc 9>,
> +				<&cpu30_intc 0xffffffff>, <&cpu30_intc 9>,
> +				<&cpu31_intc 0xffffffff>, <&cpu31_intc 9>,
> +				<&cpu32_intc 0xffffffff>, <&cpu32_intc 9>,
> +				<&cpu33_intc 0xffffffff>, <&cpu33_intc 9>,
> +				<&cpu34_intc 0xffffffff>, <&cpu34_intc 9>,
> +				<&cpu35_intc 0xffffffff>, <&cpu35_intc 9>,
> +				<&cpu36_intc 0xffffffff>, <&cpu36_intc 9>,
> +				<&cpu37_intc 0xffffffff>, <&cpu37_intc 9>,
> +				<&cpu38_intc 0xffffffff>, <&cpu38_intc 9>,
> +				<&cpu39_intc 0xffffffff>, <&cpu39_intc 9>,
> +				<&cpu40_intc 0xffffffff>, <&cpu40_intc 9>,
> +				<&cpu41_intc 0xffffffff>, <&cpu41_intc 9>,
> +				<&cpu42_intc 0xffffffff>, <&cpu42_intc 9>,
> +				<&cpu43_intc 0xffffffff>, <&cpu43_intc 9>,
> +				<&cpu44_intc 0xffffffff>, <&cpu44_intc 9>,
> +				<&cpu45_intc 0xffffffff>, <&cpu45_intc 9>,
> +				<&cpu46_intc 0xffffffff>, <&cpu46_intc 9>,
> +				<&cpu47_intc 0xffffffff>, <&cpu47_intc 9>,
> +				<&cpu48_intc 0xffffffff>, <&cpu48_intc 9>,
> +				<&cpu49_intc 0xffffffff>, <&cpu49_intc 9>,
> +				<&cpu50_intc 0xffffffff>, <&cpu50_intc 9>,
> +				<&cpu51_intc 0xffffffff>, <&cpu51_intc 9>,
> +				<&cpu52_intc 0xffffffff>, <&cpu52_intc 9>,
> +				<&cpu53_intc 0xffffffff>, <&cpu53_intc 9>,
> +				<&cpu54_intc 0xffffffff>, <&cpu54_intc 9>,
> +				<&cpu55_intc 0xffffffff>, <&cpu55_intc 9>,
> +				<&cpu56_intc 0xffffffff>, <&cpu56_intc 9>,
> +				<&cpu57_intc 0xffffffff>, <&cpu57_intc 9>,
> +				<&cpu58_intc 0xffffffff>, <&cpu58_intc 9>,
> +				<&cpu59_intc 0xffffffff>, <&cpu59_intc 9>,
> +				<&cpu60_intc 0xffffffff>, <&cpu60_intc 9>,
> +				<&cpu61_intc 0xffffffff>, <&cpu61_intc 9>,
> +				<&cpu62_intc 0xffffffff>, <&cpu62_intc 9>,
> +				<&cpu63_intc 0xffffffff>, <&cpu63_intc 9>;
> +			riscv,ndev = <224>;
> +		};
> +
> +		uart0: serial@7040000000 {
> +			compatible = "sophgo,sg2042-uart", "snps,dw-apb-uart";
> +			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
> +			interrupt-parent = <&intc>;
> +			interrupts = <SOC_PERIPHERAL_IRQ(112) IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <500000000>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			status = "disabled";
> +		};
> +	};
> +};
> --
> 2.25.1

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
  2023-09-20 11:32   ` Emil Renner Berthing
@ 2023-09-20 12:09     ` 汪辰
  2023-09-20 12:32       ` Emil Renner Berthing
  0 siblings, 1 reply; 67+ messages in thread
From: 汪辰 @ 2023-09-20 12:09 UTC (permalink / raw)
  To: Emil Renner Berthing
  Cc: Chen Wang, aou, chao.wei, conor, devicetree, guoren, jszhang,
	linux-kernel, linux-riscv, palmer, paul.walmsley, xiaoguang.xing,
	Inochi Amaoto


&gt; -----原始邮件-----
&gt; 发件人: "Emil Renner Berthing" <emil.renner.berthing@canonical.com>
&gt; 发送时间: 2023-09-20 19:32:19 (星期三)
&gt; 收件人: "Chen Wang" <unicornxw@gmail.com>, aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, emil.renner.berthing@canonical.com, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com
&gt; 抄送: "Chen Wang" <wangchen20@iscas.ac.cn>, "Inochi Amaoto" <inochiama@outlook.com>
&gt; 主题: Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
&gt; 
&gt; Chen Wang wrote:
&gt; &gt; Milk-V Pioneer motherboard is powered by SOPHON's SG2042.
&gt; 
&gt; Hi,
&gt; 
&gt; I'm just wondering what is the relation between SOPHON and SOPHGO?
&gt; I think most of the content refers to the SoC as Sophgo SG2042 or SOPHGO
&gt; SG2042, but here you're using SOPHON.

"SOPHGO" is the company name, "SOPHON" is the brand name. The whole name of SG2042 is "SOPHON SG2042".

&gt; 
&gt; Also it would be great if you could decide if it's spelled SOPHGO or Sophgo and
&gt; be consistent in all these patches.

Thanks, I will double check this in next revision.

&gt; 
&gt; /Emil
&gt; 
&gt; &gt;
&gt; &gt; SG2042 is server grade chip with high performance, low power
&gt; &gt; consumption and high data throughput.
&gt; &gt; Key features:
&gt; &gt; - 64 RISC-V cpu cores which implements IMAFDC
&gt; &gt; - 4 cores per cluster, 16 clusters on chip
&gt; &gt; - ......
&gt; &gt;
&gt; &gt; More info is available at [1].
&gt; &gt;
&gt; &gt; [1]: https://en.sophgo.com/product/introduce/sg2042.html
&gt; &gt;
&gt; &gt; Currently only support booting into console with only uart,
&gt; &gt; other features will be added soon later.
&gt; &gt;
&gt; &gt; Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
&gt; &gt; Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
&gt; &gt; Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
&gt; &gt; Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
&gt; &gt; Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
&gt; &gt; ---
&gt; &gt;  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1744 +++++++++++++++++++
&gt; &gt;  arch/riscv/boot/dts/sophgo/sg2042.dtsi      |  439 +++++
&gt; &gt;  2 files changed, 2183 insertions(+)
&gt; &gt;  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
&gt; &gt;  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
&gt; &gt;
&gt; &gt; diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
&gt; &gt; new file mode 100644
&gt; &gt; index 000000000000..9fc79b1cf3bf
&gt; &gt; --- /dev/null
&gt; &gt; +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
&gt; &gt; @@ -0,0 +1,1744 @@
&gt; &gt; +// SPDX-License-Identifier: GPL-2.0 OR MIT
&gt; &gt; +/*
&gt; &gt; + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
&gt; &gt; + */
&gt; &gt; +
&gt; &gt; +/ {
&gt; &gt; +	cpus {
&gt; &gt; +		#address-cells = &lt;1&gt;;
&gt; &gt; +		#size-cells = &lt;0&gt;;
&gt; &gt; +		timebase-frequency = &lt;50000000&gt;;
&gt; &gt; +
&gt; &gt; +		cpu-map {
&gt; &gt; +			socket0 {
&gt; &gt; +				cluster0 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu0&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu1&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu2&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu3&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster1 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu4&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu5&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu6&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu7&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster2 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu16&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu17&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu18&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu19&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster3 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu20&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu21&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu22&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu23&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster4 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu8&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu9&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu10&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu11&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster5 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu12&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu13&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu14&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu15&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster6 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu24&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu25&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu26&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu27&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster7 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu28&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu29&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu30&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu31&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster8 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu32&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu33&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu34&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu35&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster9 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu36&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu37&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu38&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu39&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster10 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu48&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu49&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu50&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu51&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster11 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu52&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu53&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu54&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu55&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster12 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu40&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu41&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu42&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu43&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster13 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu44&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu45&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu46&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu47&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster14 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu56&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu57&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu58&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu59&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +
&gt; &gt; +				cluster15 {
&gt; &gt; +					 core0 {
&gt; &gt; +						cpu = &lt;&amp;cpu60&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core1 {
&gt; &gt; +						cpu = &lt;&amp;cpu61&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core2 {
&gt; &gt; +						cpu = &lt;&amp;cpu62&gt;;
&gt; &gt; +					 };
&gt; &gt; +					 core3 {
&gt; &gt; +						cpu = &lt;&amp;cpu63&gt;;
&gt; &gt; +					 };
&gt; &gt; +				};
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu0: cpu@0 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;0&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache0&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu0_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu1: cpu@1 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;1&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache0&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu1_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu2: cpu@2 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;2&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache0&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu2_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu3: cpu@3 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;3&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache0&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu3_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu4: cpu@4 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;4&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache1&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu4_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu5: cpu@5 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;5&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache1&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu5_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu6: cpu@6 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;6&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache1&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu6_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu7: cpu@7 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;7&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache1&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu7_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu8: cpu@8 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;8&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache4&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu8_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu9: cpu@9 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;9&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache4&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu9_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu10: cpu@10 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;10&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache4&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu10_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu11: cpu@11 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;11&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache4&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu11_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu12: cpu@12 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;12&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache5&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu12_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu13: cpu@13 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;13&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache5&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu13_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu14: cpu@14 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;14&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache5&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu14_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu15: cpu@15 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;15&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache5&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu15_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu16: cpu@16 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;16&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache2&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu16_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu17: cpu@17 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;17&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache2&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu17_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu18: cpu@18 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;18&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache2&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu18_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu19: cpu@19 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;19&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache2&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu19_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu20: cpu@20 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;20&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache3&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu20_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu21: cpu@21 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;21&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache3&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu21_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu22: cpu@22 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;22&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache3&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu22_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu23: cpu@23 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;23&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache3&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu23_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu24: cpu@24 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;24&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache6&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu24_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu25: cpu@25 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;25&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache6&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu25_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu26: cpu@26 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;26&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache6&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu26_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu27: cpu@27 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;27&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache6&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu27_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu28: cpu@28 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;28&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache7&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu28_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu29: cpu@29 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;29&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache7&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu29_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu30: cpu@30 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;30&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache7&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu30_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu31: cpu@31 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;31&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache7&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu31_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu32: cpu@32 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;32&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache8&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu32_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu33: cpu@33 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;33&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache8&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu33_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu34: cpu@34 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;34&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache8&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu34_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu35: cpu@35 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;35&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache8&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu35_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu36: cpu@36 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;36&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache9&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu36_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu37: cpu@37 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;37&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache9&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu37_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu38: cpu@38 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;38&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache9&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu38_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu39: cpu@39 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;39&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache9&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu39_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu40: cpu@40 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;40&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache12&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu40_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu41: cpu@41 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;41&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache12&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu41_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu42: cpu@42 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;42&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache12&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu42_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu43: cpu@43 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;43&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache12&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu43_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu44: cpu@44 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;44&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache13&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu44_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu45: cpu@45 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;45&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache13&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu45_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu46: cpu@46 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;46&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache13&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu46_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu47: cpu@47 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;47&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache13&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu47_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu48: cpu@48 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;48&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache10&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu48_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu49: cpu@49 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;49&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache10&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu49_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu50: cpu@50 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;50&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache10&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu50_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu51: cpu@51 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;51&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache10&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu51_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu52: cpu@52 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;52&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache11&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu52_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu53: cpu@53 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;53&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache11&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu53_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu54: cpu@54 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;54&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache11&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu54_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu55: cpu@55 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;55&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache11&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu55_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu56: cpu@56 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;56&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache14&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu56_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu57: cpu@57 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;57&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache14&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu57_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu58: cpu@58 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;58&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache14&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu58_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu59: cpu@59 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;59&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache14&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu59_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu60: cpu@60 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;60&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache15&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu60_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu61: cpu@61 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;61&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache15&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu61_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu62: cpu@62 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;62&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache15&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu62_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		cpu63: cpu@63 {
&gt; &gt; +			compatible = "thead,c920", "riscv";
&gt; &gt; +			device_type = "cpu";
&gt; &gt; +			riscv,isa = "rv64imafdc";
&gt; &gt; +			reg = &lt;63&gt;;
&gt; &gt; +			i-cache-block-size = &lt;64&gt;;
&gt; &gt; +			i-cache-size = &lt;65536&gt;;
&gt; &gt; +			i-cache-sets = &lt;512&gt;;
&gt; &gt; +			d-cache-block-size = &lt;64&gt;;
&gt; &gt; +			d-cache-size = &lt;65536&gt;;
&gt; &gt; +			d-cache-sets = &lt;512&gt;;
&gt; &gt; +			next-level-cache = &lt;&amp;l2_cache15&gt;;
&gt; &gt; +			mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; +			cpu63_intc: interrupt-controller {
&gt; &gt; +				compatible = "riscv,cpu-intc";
&gt; &gt; +				interrupt-controller;
&gt; &gt; +				#interrupt-cells = &lt;1&gt;;
&gt; &gt; +			};
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache0: l2-cache@0 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache1: l2-cache@1 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache2: l2-cache@2 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache3: l2-cache@3 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache4: l2-cache@4 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache5: l2-cache@5 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache6: l2-cache@6 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache7: l2-cache@7 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache8: l2-cache@8 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache9: l2-cache@9 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache10: l2-cache@10 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache11: l2-cache@11 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache12: l2-cache@12 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache13: l2-cache@13 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache14: l2-cache@14 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		l2_cache15: l2-cache@15 {
&gt; &gt; +			compatible = "cache";
&gt; &gt; +			cache-block-size = &lt;64&gt;;
&gt; &gt; +			cache-level = &lt;2&gt;;
&gt; &gt; +			cache-size = &lt;1048576&gt;;
&gt; &gt; +			cache-sets = &lt;1024&gt;;
&gt; &gt; +			cache-unified;
&gt; &gt; +		};
&gt; &gt; +	};
&gt; &gt; +};
&gt; &gt; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
&gt; &gt; new file mode 100644
&gt; &gt; index 000000000000..747fd9764c95
&gt; &gt; --- /dev/null
&gt; &gt; +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
&gt; &gt; @@ -0,0 +1,439 @@
&gt; &gt; +// SPDX-License-Identifier: GPL-2.0 OR MIT
&gt; &gt; +/*
&gt; &gt; + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
&gt; &gt; + */
&gt; &gt; +
&gt; &gt; +/dts-v1/;
&gt; &gt; +#include <dt-bindings interrupt-controller="" irq.h="">
&gt; &gt; +
&gt; &gt; +#include "sg2042-cpus.dtsi"
&gt; &gt; +
&gt; &gt; +#define SOC_PERIPHERAL_IRQ(nr) (nr)
&gt; &gt; +
&gt; &gt; +/ {
&gt; &gt; +	compatible = "sophgo,sg2042";
&gt; &gt; +	#address-cells = &lt;2&gt;;
&gt; &gt; +	#size-cells = &lt;2&gt;;
&gt; &gt; +	dma-noncoherent;
&gt; &gt; +
&gt; &gt; +	aliases {
&gt; &gt; +		serial0 = &amp;uart0;
&gt; &gt; +	};
&gt; &gt; +
&gt; &gt; +	/* the mem node will be updated by ZSBL. */
&gt; &gt; +	memory@0 {
&gt; &gt; +		device_type = "memory";
&gt; &gt; +		reg = &lt;0x00000000 0x00000000 0x00000000 0x00000000&gt;;
&gt; &gt; +	};
&gt; &gt; +
&gt; &gt; +	memory@1 {
&gt; &gt; +		device_type = "memory";
&gt; &gt; +		reg = &lt;0x00000000 0x00000001 0x00000000 0x00000000&gt;;
&gt; &gt; +	};
&gt; &gt; +
&gt; &gt; +	memory@2 {
&gt; &gt; +		device_type = "memory";
&gt; &gt; +		reg = &lt;0x00000000 0x00000002 0x00000000 0x00000000&gt;;
&gt; &gt; +	};
&gt; &gt; +
&gt; &gt; +	memory@3 {
&gt; &gt; +		device_type = "memory";
&gt; &gt; +		reg = &lt;0x00000000 0x00000003 0x00000000 0x00000000&gt;;
&gt; &gt; +	};
&gt; &gt; +
&gt; &gt; +	pmu {
&gt; &gt; +		compatible = "riscv,pmu";
&gt; &gt; +		riscv,event-to-mhpmevent =
&gt; &gt; +			&lt;0x00003 0x00000000 0x00000010&gt;,
&gt; &gt; +			&lt;0x00004 0x00000000 0x00000011&gt;,
&gt; &gt; +			&lt;0x00005 0x00000000 0x00000007&gt;,
&gt; &gt; +			&lt;0x00006 0x00000000 0x00000006&gt;,
&gt; &gt; +			&lt;0x00008 0x00000000 0x00000027&gt;,
&gt; &gt; +			&lt;0x00009 0x00000000 0x00000028&gt;,
&gt; &gt; +			&lt;0x10000 0x00000000 0x0000000c&gt;,
&gt; &gt; +			&lt;0x10001 0x00000000 0x0000000d&gt;,
&gt; &gt; +			&lt;0x10002 0x00000000 0x0000000e&gt;,
&gt; &gt; +			&lt;0x10003 0x00000000 0x0000000f&gt;,
&gt; &gt; +			&lt;0x10008 0x00000000 0x00000001&gt;,
&gt; &gt; +			&lt;0x10009 0x00000000 0x00000002&gt;,
&gt; &gt; +			&lt;0x10010 0x00000000 0x00000010&gt;,
&gt; &gt; +			&lt;0x10011 0x00000000 0x00000011&gt;,
&gt; &gt; +			&lt;0x10012 0x00000000 0x00000012&gt;,
&gt; &gt; +			&lt;0x10013 0x00000000 0x00000013&gt;,
&gt; &gt; +			&lt;0x10019 0x00000000 0x00000004&gt;,
&gt; &gt; +			&lt;0x10021 0x00000000 0x00000003&gt;,
&gt; &gt; +			&lt;0x10030 0x00000000 0x0000001c&gt;,
&gt; &gt; +			&lt;0x10031 0x00000000 0x0000001b&gt;;
&gt; &gt; +		riscv,event-to-mhpmcounters =
&gt; &gt; +			&lt;0x00003 0x00003 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00004 0x00004 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00005 0x00005 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00006 0x00006 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00007 0x00007 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00008 0x00008 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00009 0x00009 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x0000a 0x0000a 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10000 0x10000 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10001 0x10001 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10002 0x10002 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10003 0x10003 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10008 0x10008 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10009 0x10009 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10010 0x10010 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10011 0x10011 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10012 0x10012 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10013 0x10013 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10019 0x10019 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10021 0x10021 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10030 0x10030 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x10031 0x10031 0xfffffff8&gt;;
&gt; &gt; +		riscv,raw-event-to-mhpmcounters =
&gt; &gt; +			&lt;0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; +			&lt;0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8&gt;;
&gt; &gt; +	};
&gt; &gt; +
&gt; &gt; +	soc: soc {
&gt; &gt; +		compatible = "simple-bus";
&gt; &gt; +		#address-cells = &lt;2&gt;;
&gt; &gt; +		#size-cells = &lt;2&gt;;
&gt; &gt; +		ranges;
&gt; &gt; +
&gt; &gt; +		clint_mswi: interrupt-controller@7094000000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi";
&gt; &gt; +			reg = &lt;0x00000070 0x94000000 0x00000000 0x00004000&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu0_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu1_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu2_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu3_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu4_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu5_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu6_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu7_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu8_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu9_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu10_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu11_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu12_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu13_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu14_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu15_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu16_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu17_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu18_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu19_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu20_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu21_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu22_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu23_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu24_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu25_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu26_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu27_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu28_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu29_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu30_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu31_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu32_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu33_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu34_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu35_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu36_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu37_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu38_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu39_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu40_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu41_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu42_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu43_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu44_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu45_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu46_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu47_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu48_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu49_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu50_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu51_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu52_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu53_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu54_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu55_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu56_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu57_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu58_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu59_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu60_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu61_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu62_intc 3&gt;,
&gt; &gt; +					      &lt;&amp;cpu63_intc 3&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer0: timer@70ac000000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac000000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu0_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu1_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu2_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu3_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer1: timer@70ac010000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac010000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu4_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu5_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu6_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu7_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer2: timer@70ac020000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac020000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu8_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu9_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu10_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu11_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer3: timer@70ac030000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac030000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu12_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu13_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu14_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu15_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer4: timer@70ac040000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac040000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu16_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu17_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu18_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu19_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer5: timer@70ac050000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac050000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu20_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu21_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu22_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu23_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer6: timer@70ac060000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac060000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu24_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu25_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu26_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu27_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer7: timer@70ac070000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac070000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu28_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu29_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu30_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu31_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer8: timer@70ac080000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac080000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu32_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu33_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu34_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu35_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer9: timer@70ac090000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac090000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu36_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu37_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu38_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu39_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer10: timer@70ac0a0000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac0a0000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu40_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu41_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu42_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu43_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer11: timer@70ac0b0000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac0b0000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu44_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu45_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu46_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu47_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer12: timer@70ac0c0000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac0c0000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu48_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu49_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu50_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu51_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer13: timer@70ac0d0000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac0d0000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu52_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu53_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu54_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu55_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer14: timer@70ac0e0000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac0e0000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu56_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu57_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu58_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu59_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		clint_mtimer15: timer@70ac0f0000 {
&gt; &gt; +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; +			reg = &lt;0x00000070 0xac0f0000 0x00000000 0x00007ff8&gt;;
&gt; &gt; +			interrupts-extended = &lt;&amp;cpu60_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu61_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu62_intc 7&gt;,
&gt; &gt; +					      &lt;&amp;cpu63_intc 7&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		intc: interrupt-controller@7090000000 {
&gt; &gt; +			compatible = "sophgo,sg2042-plic", "thead,c900-plic";
&gt; &gt; +			#address-cells = &lt;0&gt;;
&gt; &gt; +			#interrupt-cells = &lt;2&gt;;
&gt; &gt; +			reg = &lt;0x00000070 0x90000000 0x00000000 0x04000000&gt;;
&gt; &gt; +			interrupt-controller;
&gt; &gt; +			interrupts-extended =
&gt; &gt; +				&lt;&amp;cpu0_intc 0xffffffff&gt;,  &lt;&amp;cpu0_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu1_intc 0xffffffff&gt;,  &lt;&amp;cpu1_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu2_intc 0xffffffff&gt;,  &lt;&amp;cpu2_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu3_intc 0xffffffff&gt;,  &lt;&amp;cpu3_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu4_intc 0xffffffff&gt;,  &lt;&amp;cpu4_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu5_intc 0xffffffff&gt;,  &lt;&amp;cpu5_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu6_intc 0xffffffff&gt;,  &lt;&amp;cpu6_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu7_intc 0xffffffff&gt;,  &lt;&amp;cpu7_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu8_intc 0xffffffff&gt;,  &lt;&amp;cpu8_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu9_intc 0xffffffff&gt;,  &lt;&amp;cpu9_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu10_intc 0xffffffff&gt;, &lt;&amp;cpu10_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu11_intc 0xffffffff&gt;, &lt;&amp;cpu11_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu12_intc 0xffffffff&gt;, &lt;&amp;cpu12_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu13_intc 0xffffffff&gt;, &lt;&amp;cpu13_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu14_intc 0xffffffff&gt;, &lt;&amp;cpu14_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu15_intc 0xffffffff&gt;, &lt;&amp;cpu15_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu16_intc 0xffffffff&gt;, &lt;&amp;cpu16_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu17_intc 0xffffffff&gt;, &lt;&amp;cpu17_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu18_intc 0xffffffff&gt;, &lt;&amp;cpu18_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu19_intc 0xffffffff&gt;, &lt;&amp;cpu19_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu20_intc 0xffffffff&gt;, &lt;&amp;cpu20_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu21_intc 0xffffffff&gt;, &lt;&amp;cpu21_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu22_intc 0xffffffff&gt;, &lt;&amp;cpu22_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu23_intc 0xffffffff&gt;, &lt;&amp;cpu23_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu24_intc 0xffffffff&gt;, &lt;&amp;cpu24_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu25_intc 0xffffffff&gt;, &lt;&amp;cpu25_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu26_intc 0xffffffff&gt;, &lt;&amp;cpu26_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu27_intc 0xffffffff&gt;, &lt;&amp;cpu27_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu28_intc 0xffffffff&gt;, &lt;&amp;cpu28_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu29_intc 0xffffffff&gt;, &lt;&amp;cpu29_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu30_intc 0xffffffff&gt;, &lt;&amp;cpu30_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu31_intc 0xffffffff&gt;, &lt;&amp;cpu31_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu32_intc 0xffffffff&gt;, &lt;&amp;cpu32_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu33_intc 0xffffffff&gt;, &lt;&amp;cpu33_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu34_intc 0xffffffff&gt;, &lt;&amp;cpu34_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu35_intc 0xffffffff&gt;, &lt;&amp;cpu35_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu36_intc 0xffffffff&gt;, &lt;&amp;cpu36_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu37_intc 0xffffffff&gt;, &lt;&amp;cpu37_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu38_intc 0xffffffff&gt;, &lt;&amp;cpu38_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu39_intc 0xffffffff&gt;, &lt;&amp;cpu39_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu40_intc 0xffffffff&gt;, &lt;&amp;cpu40_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu41_intc 0xffffffff&gt;, &lt;&amp;cpu41_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu42_intc 0xffffffff&gt;, &lt;&amp;cpu42_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu43_intc 0xffffffff&gt;, &lt;&amp;cpu43_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu44_intc 0xffffffff&gt;, &lt;&amp;cpu44_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu45_intc 0xffffffff&gt;, &lt;&amp;cpu45_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu46_intc 0xffffffff&gt;, &lt;&amp;cpu46_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu47_intc 0xffffffff&gt;, &lt;&amp;cpu47_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu48_intc 0xffffffff&gt;, &lt;&amp;cpu48_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu49_intc 0xffffffff&gt;, &lt;&amp;cpu49_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu50_intc 0xffffffff&gt;, &lt;&amp;cpu50_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu51_intc 0xffffffff&gt;, &lt;&amp;cpu51_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu52_intc 0xffffffff&gt;, &lt;&amp;cpu52_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu53_intc 0xffffffff&gt;, &lt;&amp;cpu53_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu54_intc 0xffffffff&gt;, &lt;&amp;cpu54_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu55_intc 0xffffffff&gt;, &lt;&amp;cpu55_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu56_intc 0xffffffff&gt;, &lt;&amp;cpu56_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu57_intc 0xffffffff&gt;, &lt;&amp;cpu57_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu58_intc 0xffffffff&gt;, &lt;&amp;cpu58_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu59_intc 0xffffffff&gt;, &lt;&amp;cpu59_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu60_intc 0xffffffff&gt;, &lt;&amp;cpu60_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu61_intc 0xffffffff&gt;, &lt;&amp;cpu61_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu62_intc 0xffffffff&gt;, &lt;&amp;cpu62_intc 9&gt;,
&gt; &gt; +				&lt;&amp;cpu63_intc 0xffffffff&gt;, &lt;&amp;cpu63_intc 9&gt;;
&gt; &gt; +			riscv,ndev = &lt;224&gt;;
&gt; &gt; +		};
&gt; &gt; +
&gt; &gt; +		uart0: serial@7040000000 {
&gt; &gt; +			compatible = "sophgo,sg2042-uart", "snps,dw-apb-uart";
&gt; &gt; +			reg = &lt;0x00000070 0x40000000 0x00000000 0x00001000&gt;;
&gt; &gt; +			interrupt-parent = &lt;&amp;intc&gt;;
&gt; &gt; +			interrupts = <soc_peripheral_irq(112) irq_type_level_high="">;
&gt; &gt; +			clock-frequency = &lt;500000000&gt;;
&gt; &gt; +			reg-shift = &lt;2&gt;;
&gt; &gt; +			reg-io-width = &lt;4&gt;;
&gt; &gt; +			status = "disabled";
&gt; &gt; +		};
&gt; &gt; +	};
&gt; &gt; +};
&gt; &gt; --
&gt; &gt; 2.25.1


------------------------------

Best Regards 
 
 汪辰(Wang Chen) 

</soc_peripheral_irq(112)></dt-bindings></wangchen20@iscas.ac.cn></emil.renner.berthing@canonical.com></inochiama@outlook.com></xiaoguang.xing@sophgo.com></xiaoguang.xing@sophgo.com></inochiama@outlook.com></wangchen20@iscas.ac.cn></unicornxw@gmail.com></emil.renner.berthing@canonical.com>

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
  2023-09-20 12:09     ` 汪辰
@ 2023-09-20 12:32       ` Emil Renner Berthing
  2023-09-20 12:37         ` 汪辰
  0 siblings, 1 reply; 67+ messages in thread
From: Emil Renner Berthing @ 2023-09-20 12:32 UTC (permalink / raw)
  To: 汪辰, Emil Renner Berthing
  Cc: Chen Wang, aou, chao.wei, conor, devicetree, guoren, jszhang,
	linux-kernel, linux-riscv, palmer, paul.walmsley, xiaoguang.xing,
	Inochi Amaoto

汪辰 wrote:
>
> > -----原始邮件-----
> > 发件人: "Emil Renner Berthing" <emil.renner.berthing@canonical.com>
> > 发送时间: 2023-09-20 19:32:19 (星期三)
> > 收件人: "Chen Wang" <unicornxw@gmail.com>, aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, emil.renner.berthing@canonical.com, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com
> > 抄送: "Chen Wang" <wangchen20@iscas.ac.cn>, "Inochi Amaoto" <inochiama@outlook.com>
> > 主题: Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
> >
> > Chen Wang wrote:
> > > Milk-V Pioneer motherboard is powered by SOPHON's SG2042.
> >
> > Hi,
> >
> > I'm just wondering what is the relation between SOPHON and SOPHGO?
> > I think most of the content refers to the SoC as Sophgo SG2042 or SOPHGO
> > SG2042, but here you're using SOPHON.
>
> "SOPHGO" is the company name, "SOPHON" is the brand name. The whole name of SG2042 is "SOPHON SG2042".

Ah, so in this case (and next patch) it should be either "..powered by SOPHGO's
SG2042" or "..powered by the SOPHON SG2042", right?

>
> >
> > Also it would be great if you could decide if it's spelled SOPHGO or Sophgo and
> > be consistent in all these patches.
>
> Thanks, I will double check this in next revision.
>
> >
> > /Emil
> >
> > >
> > > SG2042 is server grade chip with high performance, low power
> > > consumption and high data throughput.
> > > Key features:
> > > - 64 RISC-V cpu cores which implements IMAFDC
> > > - 4 cores per cluster, 16 clusters on chip
> > > - ......
> > >
> > > More info is available at [1].
> > >
> > > [1]: https://en.sophgo.com/product/introduce/sg2042.html
> > >
> > > Currently only support booting into console with only uart,
> > > other features will be added soon later.
> > >
> > > Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > > Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > > Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> > > ---
> > >  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1744 +++++++++++++++++++
> > >  arch/riscv/boot/dts/sophgo/sg2042.dtsi      |  439 +++++
> > >  2 files changed, 2183 insertions(+)
> > >  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > >  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > >
> > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > > new file mode 100644
> > > index 000000000000..9fc79b1cf3bf
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > > @@ -0,0 +1,1744 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > +/*
> > > + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> > > + */
> > > +
> > > +/ {
> > > +	cpus {
> > > +		#address-cells = <1>;
> > > +		#size-cells = <0>;
> > > +		timebase-frequency = <50000000>;
> > > +
> > > +		cpu-map {
> > > +			socket0 {
> > > +				cluster0 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu0>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu1>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu2>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu3>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster1 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu4>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu5>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu6>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu7>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster2 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu16>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu17>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu18>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu19>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster3 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu20>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu21>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu22>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu23>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster4 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu8>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu9>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu10>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu11>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster5 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu12>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu13>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu14>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu15>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster6 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu24>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu25>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu26>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu27>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster7 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu28>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu29>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu30>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu31>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster8 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu32>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu33>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu34>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu35>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster9 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu36>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu37>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu38>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu39>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster10 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu48>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu49>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu50>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu51>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster11 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu52>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu53>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu54>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu55>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster12 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu40>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu41>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu42>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu43>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster13 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu44>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu45>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu46>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu47>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster14 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu56>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu57>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu58>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu59>;
> > > +					 };
> > > +				};
> > > +
> > > +				cluster15 {
> > > +					 core0 {
> > > +						cpu = <&amp;cpu60>;
> > > +					 };
> > > +					 core1 {
> > > +						cpu = <&amp;cpu61>;
> > > +					 };
> > > +					 core2 {
> > > +						cpu = <&amp;cpu62>;
> > > +					 };
> > > +					 core3 {
> > > +						cpu = <&amp;cpu63>;
> > > +					 };
> > > +				};
> > > +			};
> > > +		};
> > > +
> > > +		cpu0: cpu@0 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <0>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache0>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu0_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu1: cpu@1 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <1>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache0>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu1_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu2: cpu@2 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <2>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache0>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu2_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu3: cpu@3 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <3>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache0>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu3_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu4: cpu@4 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <4>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache1>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu4_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu5: cpu@5 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <5>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache1>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu5_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu6: cpu@6 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <6>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache1>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu6_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu7: cpu@7 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <7>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache1>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu7_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu8: cpu@8 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <8>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache4>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu8_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu9: cpu@9 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <9>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache4>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu9_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu10: cpu@10 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <10>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache4>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu10_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu11: cpu@11 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <11>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache4>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu11_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu12: cpu@12 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <12>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache5>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu12_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu13: cpu@13 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <13>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache5>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu13_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu14: cpu@14 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <14>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache5>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu14_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu15: cpu@15 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <15>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache5>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu15_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu16: cpu@16 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <16>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache2>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu16_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu17: cpu@17 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <17>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache2>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu17_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu18: cpu@18 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <18>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache2>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu18_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu19: cpu@19 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <19>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache2>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu19_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu20: cpu@20 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <20>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache3>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu20_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu21: cpu@21 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <21>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache3>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu21_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu22: cpu@22 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <22>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache3>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu22_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu23: cpu@23 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <23>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache3>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu23_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu24: cpu@24 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <24>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache6>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu24_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu25: cpu@25 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <25>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache6>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu25_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu26: cpu@26 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <26>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache6>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu26_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu27: cpu@27 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <27>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache6>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu27_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu28: cpu@28 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <28>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache7>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu28_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu29: cpu@29 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <29>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache7>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu29_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu30: cpu@30 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <30>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache7>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu30_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu31: cpu@31 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <31>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache7>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu31_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu32: cpu@32 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <32>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache8>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu32_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu33: cpu@33 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <33>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache8>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu33_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu34: cpu@34 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <34>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache8>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu34_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu35: cpu@35 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <35>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache8>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu35_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu36: cpu@36 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <36>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache9>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu36_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu37: cpu@37 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <37>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache9>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu37_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu38: cpu@38 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <38>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache9>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu38_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu39: cpu@39 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <39>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache9>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu39_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu40: cpu@40 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <40>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache12>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu40_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu41: cpu@41 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <41>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache12>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu41_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu42: cpu@42 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <42>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache12>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu42_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu43: cpu@43 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <43>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache12>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu43_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu44: cpu@44 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <44>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache13>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu44_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu45: cpu@45 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <45>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache13>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu45_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu46: cpu@46 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <46>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache13>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu46_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu47: cpu@47 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <47>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache13>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu47_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu48: cpu@48 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <48>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache10>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu48_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu49: cpu@49 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <49>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache10>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu49_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu50: cpu@50 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <50>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache10>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu50_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu51: cpu@51 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <51>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache10>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu51_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu52: cpu@52 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <52>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache11>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu52_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu53: cpu@53 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <53>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache11>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu53_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu54: cpu@54 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <54>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache11>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu54_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu55: cpu@55 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <55>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache11>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu55_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu56: cpu@56 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <56>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache14>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu56_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu57: cpu@57 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <57>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache14>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu57_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu58: cpu@58 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <58>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache14>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu58_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu59: cpu@59 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <59>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache14>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu59_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu60: cpu@60 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <60>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache15>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu60_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu61: cpu@61 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <61>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache15>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu61_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu62: cpu@62 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <62>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache15>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu62_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		cpu63: cpu@63 {
> > > +			compatible = "thead,c920", "riscv";
> > > +			device_type = "cpu";
> > > +			riscv,isa = "rv64imafdc";
> > > +			reg = <63>;
> > > +			i-cache-block-size = <64>;
> > > +			i-cache-size = <65536>;
> > > +			i-cache-sets = <512>;
> > > +			d-cache-block-size = <64>;
> > > +			d-cache-size = <65536>;
> > > +			d-cache-sets = <512>;
> > > +			next-level-cache = <&amp;l2_cache15>;
> > > +			mmu-type = "riscv,sv39";
> > > +
> > > +			cpu63_intc: interrupt-controller {
> > > +				compatible = "riscv,cpu-intc";
> > > +				interrupt-controller;
> > > +				#interrupt-cells = <1>;
> > > +			};
> > > +		};
> > > +
> > > +		l2_cache0: l2-cache@0 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache1: l2-cache@1 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache2: l2-cache@2 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache3: l2-cache@3 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache4: l2-cache@4 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache5: l2-cache@5 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache6: l2-cache@6 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache7: l2-cache@7 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache8: l2-cache@8 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache9: l2-cache@9 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache10: l2-cache@10 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache11: l2-cache@11 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache12: l2-cache@12 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache13: l2-cache@13 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache14: l2-cache@14 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +
> > > +		l2_cache15: l2-cache@15 {
> > > +			compatible = "cache";
> > > +			cache-block-size = <64>;
> > > +			cache-level = <2>;
> > > +			cache-size = <1048576>;
> > > +			cache-sets = <1024>;
> > > +			cache-unified;
> > > +		};
> > > +	};
> > > +};
> > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > > new file mode 100644
> > > index 000000000000..747fd9764c95
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > > @@ -0,0 +1,439 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > +/*
> > > + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> > > + */
> > > +
> > > +/dts-v1/;
> > > +#include <dt-bindings interrupt-controller="" irq.h="">
> > > +
> > > +#include "sg2042-cpus.dtsi"
> > > +
> > > +#define SOC_PERIPHERAL_IRQ(nr) (nr)
> > > +
> > > +/ {
> > > +	compatible = "sophgo,sg2042";
> > > +	#address-cells = <2>;
> > > +	#size-cells = <2>;
> > > +	dma-noncoherent;
> > > +
> > > +	aliases {
> > > +		serial0 = &amp;uart0;
> > > +	};
> > > +
> > > +	/* the mem node will be updated by ZSBL. */
> > > +	memory@0 {
> > > +		device_type = "memory";
> > > +		reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
> > > +	};
> > > +
> > > +	memory@1 {
> > > +		device_type = "memory";
> > > +		reg = <0x00000000 0x00000001 0x00000000 0x00000000>;
> > > +	};
> > > +
> > > +	memory@2 {
> > > +		device_type = "memory";
> > > +		reg = <0x00000000 0x00000002 0x00000000 0x00000000>;
> > > +	};
> > > +
> > > +	memory@3 {
> > > +		device_type = "memory";
> > > +		reg = <0x00000000 0x00000003 0x00000000 0x00000000>;
> > > +	};
> > > +
> > > +	pmu {
> > > +		compatible = "riscv,pmu";
> > > +		riscv,event-to-mhpmevent =
> > > +			<0x00003 0x00000000 0x00000010>,
> > > +			<0x00004 0x00000000 0x00000011>,
> > > +			<0x00005 0x00000000 0x00000007>,
> > > +			<0x00006 0x00000000 0x00000006>,
> > > +			<0x00008 0x00000000 0x00000027>,
> > > +			<0x00009 0x00000000 0x00000028>,
> > > +			<0x10000 0x00000000 0x0000000c>,
> > > +			<0x10001 0x00000000 0x0000000d>,
> > > +			<0x10002 0x00000000 0x0000000e>,
> > > +			<0x10003 0x00000000 0x0000000f>,
> > > +			<0x10008 0x00000000 0x00000001>,
> > > +			<0x10009 0x00000000 0x00000002>,
> > > +			<0x10010 0x00000000 0x00000010>,
> > > +			<0x10011 0x00000000 0x00000011>,
> > > +			<0x10012 0x00000000 0x00000012>,
> > > +			<0x10013 0x00000000 0x00000013>,
> > > +			<0x10019 0x00000000 0x00000004>,
> > > +			<0x10021 0x00000000 0x00000003>,
> > > +			<0x10030 0x00000000 0x0000001c>,
> > > +			<0x10031 0x00000000 0x0000001b>;
> > > +		riscv,event-to-mhpmcounters =
> > > +			<0x00003 0x00003 0xfffffff8>,
> > > +			<0x00004 0x00004 0xfffffff8>,
> > > +			<0x00005 0x00005 0xfffffff8>,
> > > +			<0x00006 0x00006 0xfffffff8>,
> > > +			<0x00007 0x00007 0xfffffff8>,
> > > +			<0x00008 0x00008 0xfffffff8>,
> > > +			<0x00009 0x00009 0xfffffff8>,
> > > +			<0x0000a 0x0000a 0xfffffff8>,
> > > +			<0x10000 0x10000 0xfffffff8>,
> > > +			<0x10001 0x10001 0xfffffff8>,
> > > +			<0x10002 0x10002 0xfffffff8>,
> > > +			<0x10003 0x10003 0xfffffff8>,
> > > +			<0x10008 0x10008 0xfffffff8>,
> > > +			<0x10009 0x10009 0xfffffff8>,
> > > +			<0x10010 0x10010 0xfffffff8>,
> > > +			<0x10011 0x10011 0xfffffff8>,
> > > +			<0x10012 0x10012 0xfffffff8>,
> > > +			<0x10013 0x10013 0xfffffff8>,
> > > +			<0x10019 0x10019 0xfffffff8>,
> > > +			<0x10021 0x10021 0xfffffff8>,
> > > +			<0x10030 0x10030 0xfffffff8>,
> > > +			<0x10031 0x10031 0xfffffff8>;
> > > +		riscv,raw-event-to-mhpmcounters =
> > > +			<0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>,
> > > +			<0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>;
> > > +	};
> > > +
> > > +	soc: soc {
> > > +		compatible = "simple-bus";
> > > +		#address-cells = <2>;
> > > +		#size-cells = <2>;
> > > +		ranges;
> > > +
> > > +		clint_mswi: interrupt-controller@7094000000 {
> > > +			compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi";
> > > +			reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
> > > +			interrupts-extended = <&amp;cpu0_intc 3>,
> > > +					      <&amp;cpu1_intc 3>,
> > > +					      <&amp;cpu2_intc 3>,
> > > +					      <&amp;cpu3_intc 3>,
> > > +					      <&amp;cpu4_intc 3>,
> > > +					      <&amp;cpu5_intc 3>,
> > > +					      <&amp;cpu6_intc 3>,
> > > +					      <&amp;cpu7_intc 3>,
> > > +					      <&amp;cpu8_intc 3>,
> > > +					      <&amp;cpu9_intc 3>,
> > > +					      <&amp;cpu10_intc 3>,
> > > +					      <&amp;cpu11_intc 3>,
> > > +					      <&amp;cpu12_intc 3>,
> > > +					      <&amp;cpu13_intc 3>,
> > > +					      <&amp;cpu14_intc 3>,
> > > +					      <&amp;cpu15_intc 3>,
> > > +					      <&amp;cpu16_intc 3>,
> > > +					      <&amp;cpu17_intc 3>,
> > > +					      <&amp;cpu18_intc 3>,
> > > +					      <&amp;cpu19_intc 3>,
> > > +					      <&amp;cpu20_intc 3>,
> > > +					      <&amp;cpu21_intc 3>,
> > > +					      <&amp;cpu22_intc 3>,
> > > +					      <&amp;cpu23_intc 3>,
> > > +					      <&amp;cpu24_intc 3>,
> > > +					      <&amp;cpu25_intc 3>,
> > > +					      <&amp;cpu26_intc 3>,
> > > +					      <&amp;cpu27_intc 3>,
> > > +					      <&amp;cpu28_intc 3>,
> > > +					      <&amp;cpu29_intc 3>,
> > > +					      <&amp;cpu30_intc 3>,
> > > +					      <&amp;cpu31_intc 3>,
> > > +					      <&amp;cpu32_intc 3>,
> > > +					      <&amp;cpu33_intc 3>,
> > > +					      <&amp;cpu34_intc 3>,
> > > +					      <&amp;cpu35_intc 3>,
> > > +					      <&amp;cpu36_intc 3>,
> > > +					      <&amp;cpu37_intc 3>,
> > > +					      <&amp;cpu38_intc 3>,
> > > +					      <&amp;cpu39_intc 3>,
> > > +					      <&amp;cpu40_intc 3>,
> > > +					      <&amp;cpu41_intc 3>,
> > > +					      <&amp;cpu42_intc 3>,
> > > +					      <&amp;cpu43_intc 3>,
> > > +					      <&amp;cpu44_intc 3>,
> > > +					      <&amp;cpu45_intc 3>,
> > > +					      <&amp;cpu46_intc 3>,
> > > +					      <&amp;cpu47_intc 3>,
> > > +					      <&amp;cpu48_intc 3>,
> > > +					      <&amp;cpu49_intc 3>,
> > > +					      <&amp;cpu50_intc 3>,
> > > +					      <&amp;cpu51_intc 3>,
> > > +					      <&amp;cpu52_intc 3>,
> > > +					      <&amp;cpu53_intc 3>,
> > > +					      <&amp;cpu54_intc 3>,
> > > +					      <&amp;cpu55_intc 3>,
> > > +					      <&amp;cpu56_intc 3>,
> > > +					      <&amp;cpu57_intc 3>,
> > > +					      <&amp;cpu58_intc 3>,
> > > +					      <&amp;cpu59_intc 3>,
> > > +					      <&amp;cpu60_intc 3>,
> > > +					      <&amp;cpu61_intc 3>,
> > > +					      <&amp;cpu62_intc 3>,
> > > +					      <&amp;cpu63_intc 3>;
> > > +		};
> > > +
> > > +		clint_mtimer0: timer@70ac000000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu0_intc 7>,
> > > +					      <&amp;cpu1_intc 7>,
> > > +					      <&amp;cpu2_intc 7>,
> > > +					      <&amp;cpu3_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer1: timer@70ac010000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu4_intc 7>,
> > > +					      <&amp;cpu5_intc 7>,
> > > +					      <&amp;cpu6_intc 7>,
> > > +					      <&amp;cpu7_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer2: timer@70ac020000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu8_intc 7>,
> > > +					      <&amp;cpu9_intc 7>,
> > > +					      <&amp;cpu10_intc 7>,
> > > +					      <&amp;cpu11_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer3: timer@70ac030000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu12_intc 7>,
> > > +					      <&amp;cpu13_intc 7>,
> > > +					      <&amp;cpu14_intc 7>,
> > > +					      <&amp;cpu15_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer4: timer@70ac040000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu16_intc 7>,
> > > +					      <&amp;cpu17_intc 7>,
> > > +					      <&amp;cpu18_intc 7>,
> > > +					      <&amp;cpu19_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer5: timer@70ac050000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu20_intc 7>,
> > > +					      <&amp;cpu21_intc 7>,
> > > +					      <&amp;cpu22_intc 7>,
> > > +					      <&amp;cpu23_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer6: timer@70ac060000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu24_intc 7>,
> > > +					      <&amp;cpu25_intc 7>,
> > > +					      <&amp;cpu26_intc 7>,
> > > +					      <&amp;cpu27_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer7: timer@70ac070000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu28_intc 7>,
> > > +					      <&amp;cpu29_intc 7>,
> > > +					      <&amp;cpu30_intc 7>,
> > > +					      <&amp;cpu31_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer8: timer@70ac080000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu32_intc 7>,
> > > +					      <&amp;cpu33_intc 7>,
> > > +					      <&amp;cpu34_intc 7>,
> > > +					      <&amp;cpu35_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer9: timer@70ac090000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu36_intc 7>,
> > > +					      <&amp;cpu37_intc 7>,
> > > +					      <&amp;cpu38_intc 7>,
> > > +					      <&amp;cpu39_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer10: timer@70ac0a0000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu40_intc 7>,
> > > +					      <&amp;cpu41_intc 7>,
> > > +					      <&amp;cpu42_intc 7>,
> > > +					      <&amp;cpu43_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer11: timer@70ac0b0000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu44_intc 7>,
> > > +					      <&amp;cpu45_intc 7>,
> > > +					      <&amp;cpu46_intc 7>,
> > > +					      <&amp;cpu47_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer12: timer@70ac0c0000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu48_intc 7>,
> > > +					      <&amp;cpu49_intc 7>,
> > > +					      <&amp;cpu50_intc 7>,
> > > +					      <&amp;cpu51_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer13: timer@70ac0d0000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu52_intc 7>,
> > > +					      <&amp;cpu53_intc 7>,
> > > +					      <&amp;cpu54_intc 7>,
> > > +					      <&amp;cpu55_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer14: timer@70ac0e0000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu56_intc 7>,
> > > +					      <&amp;cpu57_intc 7>,
> > > +					      <&amp;cpu58_intc 7>,
> > > +					      <&amp;cpu59_intc 7>;
> > > +		};
> > > +
> > > +		clint_mtimer15: timer@70ac0f0000 {
> > > +			compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
> > > +			reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
> > > +			interrupts-extended = <&amp;cpu60_intc 7>,
> > > +					      <&amp;cpu61_intc 7>,
> > > +					      <&amp;cpu62_intc 7>,
> > > +					      <&amp;cpu63_intc 7>;
> > > +		};
> > > +
> > > +		intc: interrupt-controller@7090000000 {
> > > +			compatible = "sophgo,sg2042-plic", "thead,c900-plic";
> > > +			#address-cells = <0>;
> > > +			#interrupt-cells = <2>;
> > > +			reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
> > > +			interrupt-controller;
> > > +			interrupts-extended =
> > > +				<&amp;cpu0_intc 0xffffffff>,  <&amp;cpu0_intc 9>,
> > > +				<&amp;cpu1_intc 0xffffffff>,  <&amp;cpu1_intc 9>,
> > > +				<&amp;cpu2_intc 0xffffffff>,  <&amp;cpu2_intc 9>,
> > > +				<&amp;cpu3_intc 0xffffffff>,  <&amp;cpu3_intc 9>,
> > > +				<&amp;cpu4_intc 0xffffffff>,  <&amp;cpu4_intc 9>,
> > > +				<&amp;cpu5_intc 0xffffffff>,  <&amp;cpu5_intc 9>,
> > > +				<&amp;cpu6_intc 0xffffffff>,  <&amp;cpu6_intc 9>,
> > > +				<&amp;cpu7_intc 0xffffffff>,  <&amp;cpu7_intc 9>,
> > > +				<&amp;cpu8_intc 0xffffffff>,  <&amp;cpu8_intc 9>,
> > > +				<&amp;cpu9_intc 0xffffffff>,  <&amp;cpu9_intc 9>,
> > > +				<&amp;cpu10_intc 0xffffffff>, <&amp;cpu10_intc 9>,
> > > +				<&amp;cpu11_intc 0xffffffff>, <&amp;cpu11_intc 9>,
> > > +				<&amp;cpu12_intc 0xffffffff>, <&amp;cpu12_intc 9>,
> > > +				<&amp;cpu13_intc 0xffffffff>, <&amp;cpu13_intc 9>,
> > > +				<&amp;cpu14_intc 0xffffffff>, <&amp;cpu14_intc 9>,
> > > +				<&amp;cpu15_intc 0xffffffff>, <&amp;cpu15_intc 9>,
> > > +				<&amp;cpu16_intc 0xffffffff>, <&amp;cpu16_intc 9>,
> > > +				<&amp;cpu17_intc 0xffffffff>, <&amp;cpu17_intc 9>,
> > > +				<&amp;cpu18_intc 0xffffffff>, <&amp;cpu18_intc 9>,
> > > +				<&amp;cpu19_intc 0xffffffff>, <&amp;cpu19_intc 9>,
> > > +				<&amp;cpu20_intc 0xffffffff>, <&amp;cpu20_intc 9>,
> > > +				<&amp;cpu21_intc 0xffffffff>, <&amp;cpu21_intc 9>,
> > > +				<&amp;cpu22_intc 0xffffffff>, <&amp;cpu22_intc 9>,
> > > +				<&amp;cpu23_intc 0xffffffff>, <&amp;cpu23_intc 9>,
> > > +				<&amp;cpu24_intc 0xffffffff>, <&amp;cpu24_intc 9>,
> > > +				<&amp;cpu25_intc 0xffffffff>, <&amp;cpu25_intc 9>,
> > > +				<&amp;cpu26_intc 0xffffffff>, <&amp;cpu26_intc 9>,
> > > +				<&amp;cpu27_intc 0xffffffff>, <&amp;cpu27_intc 9>,
> > > +				<&amp;cpu28_intc 0xffffffff>, <&amp;cpu28_intc 9>,
> > > +				<&amp;cpu29_intc 0xffffffff>, <&amp;cpu29_intc 9>,
> > > +				<&amp;cpu30_intc 0xffffffff>, <&amp;cpu30_intc 9>,
> > > +				<&amp;cpu31_intc 0xffffffff>, <&amp;cpu31_intc 9>,
> > > +				<&amp;cpu32_intc 0xffffffff>, <&amp;cpu32_intc 9>,
> > > +				<&amp;cpu33_intc 0xffffffff>, <&amp;cpu33_intc 9>,
> > > +				<&amp;cpu34_intc 0xffffffff>, <&amp;cpu34_intc 9>,
> > > +				<&amp;cpu35_intc 0xffffffff>, <&amp;cpu35_intc 9>,
> > > +				<&amp;cpu36_intc 0xffffffff>, <&amp;cpu36_intc 9>,
> > > +				<&amp;cpu37_intc 0xffffffff>, <&amp;cpu37_intc 9>,
> > > +				<&amp;cpu38_intc 0xffffffff>, <&amp;cpu38_intc 9>,
> > > +				<&amp;cpu39_intc 0xffffffff>, <&amp;cpu39_intc 9>,
> > > +				<&amp;cpu40_intc 0xffffffff>, <&amp;cpu40_intc 9>,
> > > +				<&amp;cpu41_intc 0xffffffff>, <&amp;cpu41_intc 9>,
> > > +				<&amp;cpu42_intc 0xffffffff>, <&amp;cpu42_intc 9>,
> > > +				<&amp;cpu43_intc 0xffffffff>, <&amp;cpu43_intc 9>,
> > > +				<&amp;cpu44_intc 0xffffffff>, <&amp;cpu44_intc 9>,
> > > +				<&amp;cpu45_intc 0xffffffff>, <&amp;cpu45_intc 9>,
> > > +				<&amp;cpu46_intc 0xffffffff>, <&amp;cpu46_intc 9>,
> > > +				<&amp;cpu47_intc 0xffffffff>, <&amp;cpu47_intc 9>,
> > > +				<&amp;cpu48_intc 0xffffffff>, <&amp;cpu48_intc 9>,
> > > +				<&amp;cpu49_intc 0xffffffff>, <&amp;cpu49_intc 9>,
> > > +				<&amp;cpu50_intc 0xffffffff>, <&amp;cpu50_intc 9>,
> > > +				<&amp;cpu51_intc 0xffffffff>, <&amp;cpu51_intc 9>,
> > > +				<&amp;cpu52_intc 0xffffffff>, <&amp;cpu52_intc 9>,
> > > +				<&amp;cpu53_intc 0xffffffff>, <&amp;cpu53_intc 9>,
> > > +				<&amp;cpu54_intc 0xffffffff>, <&amp;cpu54_intc 9>,
> > > +				<&amp;cpu55_intc 0xffffffff>, <&amp;cpu55_intc 9>,
> > > +				<&amp;cpu56_intc 0xffffffff>, <&amp;cpu56_intc 9>,
> > > +				<&amp;cpu57_intc 0xffffffff>, <&amp;cpu57_intc 9>,
> > > +				<&amp;cpu58_intc 0xffffffff>, <&amp;cpu58_intc 9>,
> > > +				<&amp;cpu59_intc 0xffffffff>, <&amp;cpu59_intc 9>,
> > > +				<&amp;cpu60_intc 0xffffffff>, <&amp;cpu60_intc 9>,
> > > +				<&amp;cpu61_intc 0xffffffff>, <&amp;cpu61_intc 9>,
> > > +				<&amp;cpu62_intc 0xffffffff>, <&amp;cpu62_intc 9>,
> > > +				<&amp;cpu63_intc 0xffffffff>, <&amp;cpu63_intc 9>;
> > > +			riscv,ndev = <224>;
> > > +		};
> > > +
> > > +		uart0: serial@7040000000 {
> > > +			compatible = "sophgo,sg2042-uart", "snps,dw-apb-uart";
> > > +			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
> > > +			interrupt-parent = <&amp;intc>;
> > > +			interrupts = <soc_peripheral_irq(112) irq_type_level_high="">;
> > > +			clock-frequency = <500000000>;
> > > +			reg-shift = <2>;
> > > +			reg-io-width = <4>;
> > > +			status = "disabled";
> > > +		};
> > > +	};
> > > +};
> > > --
> > > 2.25.1
>
>
> ------------------------------
>
> Best Regards
>
>  汪辰(Wang Chen)
>
> </soc_peripheral_irq(112)></dt-bindings></wangchen20@iscas.ac.cn></emil.renner.berthing@canonical.com></inochiama@outlook.com></xiaoguang.xing@sophgo.com></xiaoguang.xing@sophgo.com></inochiama@outlook.com></wangchen20@iscas.ac.cn></unicornxw@gmail.com></emil.renner.berthing@canonical.com>

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: Re: Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
  2023-09-20 12:32       ` Emil Renner Berthing
@ 2023-09-20 12:37         ` 汪辰
  0 siblings, 0 replies; 67+ messages in thread
From: 汪辰 @ 2023-09-20 12:37 UTC (permalink / raw)
  To: Emil Renner Berthing
  Cc: Chen Wang, aou, chao.wei, conor, devicetree, guoren, jszhang,
	linux-kernel, linux-riscv, palmer, paul.walmsley, xiaoguang.xing,
	Inochi Amaoto

&gt; -----原始邮件-----
&gt; 发件人: "Emil Renner Berthing" <emil.renner.berthing@canonical.com>
&gt; 发送时间: 2023-09-20 20:32:17 (星期三)
&gt; 收件人: "汪辰" <wangchen20@iscas.ac.cn>, "Emil Renner Berthing" <emil.renner.berthing@canonical.com>
&gt; 抄送: "Chen Wang" <unicornxw@gmail.com>, aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, xiaoguang.xing@sophgo.com, "Inochi Amaoto" <inochiama@outlook.com>
&gt; 主题: Re: Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
&gt; 
&gt; 汪辰 wrote:
&gt; &gt;
&gt; &gt; &gt; -----原始邮件-----
&gt; &gt; &gt; 发件人: "Emil Renner Berthing" <emil.renner.berthing@canonical.com>
&gt; &gt; &gt; 发送时间: 2023-09-20 19:32:19 (星期三)
&gt; &gt; &gt; 收件人: "Chen Wang" <unicornxw@gmail.com>, aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, emil.renner.berthing@canonical.com, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com
&gt; &gt; &gt; 抄送: "Chen Wang" <wangchen20@iscas.ac.cn>, "Inochi Amaoto" <inochiama@outlook.com>
&gt; &gt; &gt; 主题: Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
&gt; &gt; &gt;
&gt; &gt; &gt; Chen Wang wrote:
&gt; &gt; &gt; &gt; Milk-V Pioneer motherboard is powered by SOPHON's SG2042.
&gt; &gt; &gt;
&gt; &gt; &gt; Hi,
&gt; &gt; &gt;
&gt; &gt; &gt; I'm just wondering what is the relation between SOPHON and SOPHGO?
&gt; &gt; &gt; I think most of the content refers to the SoC as Sophgo SG2042 or SOPHGO
&gt; &gt; &gt; SG2042, but here you're using SOPHON.
&gt; &gt;
&gt; &gt; "SOPHGO" is the company name, "SOPHON" is the brand name. The whole name of SG2042 is "SOPHON SG2042".
&gt; 
&gt; Ah, so in this case (and next patch) it should be either "..powered by SOPHGO's
&gt; SG2042" or "..powered by the SOPHON SG2042", right?

Yes,  you are right, I will correct this in next patch, thanks for your carefulness, I'm nearly confused by this too :\

&gt; 
&gt; &gt;
&gt; &gt; &gt;
&gt; &gt; &gt; Also it would be great if you could decide if it's spelled SOPHGO or Sophgo and
&gt; &gt; &gt; be consistent in all these patches.
&gt; &gt;
&gt; &gt; Thanks, I will double check this in next revision.
&gt; &gt;
&gt; &gt; &gt;
&gt; &gt; &gt; /Emil
&gt; &gt; &gt;
&gt; &gt; &gt; &gt;
</inochiama@outlook.com></wangchen20@iscas.ac.cn></unicornxw@gmail.com></emil.renner.berthing@canonical.com></inochiama@outlook.com></unicornxw@gmail.com></emil.renner.berthing@canonical.com></wangchen20@iscas.ac.cn></emil.renner.berthing@canonical.com>

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
  2023-09-20  6:40 ` [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree Chen Wang
                     ` (2 preceding siblings ...)
  2023-09-20 11:32   ` Emil Renner Berthing
@ 2023-09-20 15:19   ` Palmer Dabbelt
  2023-09-20 15:31     ` Conor Dooley
  3 siblings, 1 reply; 67+ messages in thread
From: Palmer Dabbelt @ 2023-09-20 15:19 UTC (permalink / raw)
  To: unicornxw
  Cc: aou, chao.wei, Conor Dooley, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, Paul Walmsley, robh+dt, xiaoguang.xing, wangchen20,
	inochiama

On Tue, 19 Sep 2023 23:40:32 PDT (-0700), unicornxw@gmail.com wrote:
> Milk-V Pioneer motherboard is powered by SOPHON's SG2042.
>
> SG2042 is server grade chip with high performance, low power
> consumption and high data throughput.
> Key features:
> - 64 RISC-V cpu cores which implements IMAFDC
> - 4 cores per cluster, 16 clusters on chip
> - ......
>
> More info is available at [1].
>
> [1]: https://en.sophgo.com/product/introduce/sg2042.html
>
> Currently only support booting into console with only uart,
> other features will be added soon later.
>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1744 +++++++++++++++++++
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi      |  439 +++++
>  2 files changed, 2183 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi

Just an FYI: a handful of replies to this are getting blocked by the 
lists as they end up being too big.  I just went and allowed what was 
there, but future replies will probably require someone to be away as 
well and thus might be slow.

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
  2023-09-20 15:19   ` Palmer Dabbelt
@ 2023-09-20 15:31     ` Conor Dooley
  0 siblings, 0 replies; 67+ messages in thread
From: Conor Dooley @ 2023-09-20 15:31 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: unicornxw, aou, chao.wei, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, Paul Walmsley, robh+dt, xiaoguang.xing, wangchen20,
	inochiama

[-- Attachment #1: Type: text/plain, Size: 1757 bytes --]

On Wed, Sep 20, 2023 at 08:19:59AM -0700, Palmer Dabbelt wrote:
> On Tue, 19 Sep 2023 23:40:32 PDT (-0700), unicornxw@gmail.com wrote:
> > Milk-V Pioneer motherboard is powered by SOPHON's SG2042.
> > 
> > SG2042 is server grade chip with high performance, low power
> > consumption and high data throughput.
> > Key features:
> > - 64 RISC-V cpu cores which implements IMAFDC
> > - 4 cores per cluster, 16 clusters on chip
> > - ......
> > 
> > More info is available at [1].
> > 
> > [1]: https://en.sophgo.com/product/introduce/sg2042.html
> > 
> > Currently only support booting into console with only uart,
> > other features will be added soon later.
> > 
> > Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> > Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> > ---
> >  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1744 +++++++++++++++++++
> >  arch/riscv/boot/dts/sophgo/sg2042.dtsi      |  439 +++++
> >  2 files changed, 2183 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> >  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
> 
> Just an FYI: a handful of replies to this are getting blocked by the lists
> as they end up being too big.  I just went and allowed what was there, but
> future replies will probably require someone to be away as well and thus
> might be slow.

95% of this patch is the same, if people that reply are good citizens
& trim, it'll not be too bad. btw, if you want, you can add me as
someone that can click the "not spam" button.

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^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCH v2 10/11] riscv: dts: sophgo: add Milk-V Pioneer board device tree
  2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
                   ` (8 preceding siblings ...)
  2023-09-20  6:40 ` [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree Chen Wang
@ 2023-09-20  6:40 ` Chen Wang
  2023-09-20  8:05   ` Guo Ren
                     ` (2 more replies)
  2023-09-20  6:41 ` [PATCH v2 11/11] riscv: defconfig: enable SOPHGO SoC Chen Wang
                   ` (2 subsequent siblings)
  12 siblings, 3 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-20  6:40 UTC (permalink / raw)
  To: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang

Milk-V Pioneer [1] is a developer motherboard based on SOPHON
SG2042 in a standard mATX form factor. It is a good
choice for RISC-V developers and hardware pioneers to
experience the cutting edge technology of RISC-V.

Currently only support booting into console with only uart
enabled, other features will be added soon later.

[1]: https://milkv.io/pioneer

Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---
 arch/riscv/boot/dts/Makefile                  |  1 +
 arch/riscv/boot/dts/sophgo/Makefile           |  3 +++
 .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  | 19 +++++++++++++++++++
 3 files changed, 23 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index f60a280abb15..94788486f13e 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -6,5 +6,6 @@ subdir-y += renesas
 subdir-y += sifive
 subdir-y += starfive
 subdir-y += thead
+subdir-y += sophgo
 
 obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
new file mode 100644
index 000000000000..5a471b19df22
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
+
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
new file mode 100644
index 000000000000..d6e8c0285d1e
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
+ */
+
+#include "sg2042.dtsi"
+
+/ {
+	model = "Milk-V Pioneer";
+	compatible = "milkv,pioneer", "sophgo,sg2042";
+
+	chosen: chosen {
+		stdout-path = "serial0";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 10/11] riscv: dts: sophgo: add Milk-V Pioneer board device tree
  2023-09-20  6:40 ` [PATCH v2 10/11] riscv: dts: sophgo: add Milk-V Pioneer board " Chen Wang
@ 2023-09-20  8:05   ` Guo Ren
  2023-09-20  8:16   ` Conor Dooley
  2023-09-20 11:59   ` Krzysztof Kozlowski
  2 siblings, 0 replies; 67+ messages in thread
From: Guo Ren @ 2023-09-20  8:05 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

On Wed, Sep 20, 2023 at 2:41 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> Milk-V Pioneer [1] is a developer motherboard based on SOPHON
> SG2042 in a standard mATX form factor. It is a good
> choice for RISC-V developers and hardware pioneers to
> experience the cutting edge technology of RISC-V.
>
> Currently only support booting into console with only uart
> enabled, other features will be added soon later.
>
> [1]: https://milkv.io/pioneer
>
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  arch/riscv/boot/dts/Makefile                  |  1 +
>  arch/riscv/boot/dts/sophgo/Makefile           |  3 +++
>  .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  | 19 +++++++++++++++++++
>  3 files changed, 23 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index f60a280abb15..94788486f13e 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -6,5 +6,6 @@ subdir-y += renesas
>  subdir-y += sifive
>  subdir-y += starfive
>  subdir-y += thead
> +subdir-y += sophgo
>
>  obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> new file mode 100644
> index 000000000000..5a471b19df22
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
> +
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> new file mode 100644
> index 000000000000..d6e8c0285d1e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +#include "sg2042.dtsi"
> +
> +/ {
> +       model = "Milk-V Pioneer";
> +       compatible = "milkv,pioneer", "sophgo,sg2042";
> +
> +       chosen: chosen {
> +               stdout-path = "serial0";
> +       };
> +};
> +
> +&uart0 {
> +       status = "okay";
> +};
> --
> 2.25.1
>
LGTM

Reviewed-by: Guo Ren <guoren@kernel.org>

-- 
Best Regards
 Guo Ren

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 10/11] riscv: dts: sophgo: add Milk-V Pioneer board device tree
  2023-09-20  6:40 ` [PATCH v2 10/11] riscv: dts: sophgo: add Milk-V Pioneer board " Chen Wang
  2023-09-20  8:05   ` Guo Ren
@ 2023-09-20  8:16   ` Conor Dooley
  2023-09-20 11:59   ` Krzysztof Kozlowski
  2 siblings, 0 replies; 67+ messages in thread
From: Conor Dooley @ 2023-09-20  8:16 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

[-- Attachment #1: Type: text/plain, Size: 2531 bytes --]

Hey,

On Wed, Sep 20, 2023 at 02:40:53PM +0800, Chen Wang wrote:
> Milk-V Pioneer [1] is a developer motherboard based on SOPHON
> SG2042 in a standard mATX form factor.

> It is a good
> choice for RISC-V developers and hardware pioneers to
> experience the cutting edge technology of RISC-V.

I'd rather we didn't put advertising into commit messages.

> Currently only support booting into console with only uart
> enabled, other features will be added soon later.
> 
> [1]: https://milkv.io/pioneer

Make this a link tag please

Link: https://milkv.io/pioneer [1]
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  arch/riscv/boot/dts/Makefile                  |  1 +
>  arch/riscv/boot/dts/sophgo/Makefile           |  3 +++
>  .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  | 19 +++++++++++++++++++
>  3 files changed, 23 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> 
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index f60a280abb15..94788486f13e 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -6,5 +6,6 @@ subdir-y += renesas
>  subdir-y += sifive
>  subdir-y += starfive
>  subdir-y += thead
> +subdir-y += sophgo

Alphanumerical order please.

Thanks,
Conor.

>  
>  obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> new file mode 100644
> index 000000000000..5a471b19df22
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
> +
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> new file mode 100644
> index 000000000000..d6e8c0285d1e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +#include "sg2042.dtsi"
> +
> +/ {
> +	model = "Milk-V Pioneer";
> +	compatible = "milkv,pioneer", "sophgo,sg2042";
> +
> +	chosen: chosen {
> +		stdout-path = "serial0";
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> -- 
> 2.25.1
> 

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^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 10/11] riscv: dts: sophgo: add Milk-V Pioneer board device tree
  2023-09-20  6:40 ` [PATCH v2 10/11] riscv: dts: sophgo: add Milk-V Pioneer board " Chen Wang
  2023-09-20  8:05   ` Guo Ren
  2023-09-20  8:16   ` Conor Dooley
@ 2023-09-20 11:59   ` Krzysztof Kozlowski
  2 siblings, 0 replies; 67+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-20 11:59 UTC (permalink / raw)
  To: Chen Wang, aou, chao.wei, conor, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang

On 20/09/2023 08:40, Chen Wang wrote:
> Milk-V Pioneer [1] is a developer motherboard based on SOPHON
> SG2042 in a standard mATX form factor. It is a good
> choice for RISC-V developers and hardware pioneers to
> experience the cutting edge technology of RISC-V.
> 
> Currently only support booting into console with only uart
> enabled, other features will be added soon later.
> 
> [1]: https://milkv.io/pioneer
> 
> Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  arch/riscv/boot/dts/Makefile                  |  1 +
>  arch/riscv/boot/dts/sophgo/Makefile           |  3 +++
>  .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  | 19 +++++++++++++++++++
>  3 files changed, 23 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> 
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index f60a280abb15..94788486f13e 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -6,5 +6,6 @@ subdir-y += renesas
>  subdir-y += sifive
>  subdir-y += starfive
>  subdir-y += thead
> +subdir-y += sophgo
>  
>  obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> new file mode 100644
> index 000000000000..5a471b19df22
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
> +
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> new file mode 100644
> index 000000000000..d6e8c0285d1e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +#include "sg2042.dtsi"
> +
> +/ {
> +	model = "Milk-V Pioneer";
> +	compatible = "milkv,pioneer", "sophgo,sg2042";
> +
> +	chosen: chosen {

Drop label, not used.


Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 67+ messages in thread

* [PATCH v2 11/11] riscv: defconfig: enable SOPHGO SoC
  2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
                   ` (9 preceding siblings ...)
  2023-09-20  6:40 ` [PATCH v2 10/11] riscv: dts: sophgo: add Milk-V Pioneer board " Chen Wang
@ 2023-09-20  6:41 ` Chen Wang
  2023-09-20  8:06   ` Guo Ren
  2023-09-20  8:58   ` Conor Dooley
  2023-09-20 10:01 ` [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Conor Dooley
  2023-09-20 15:22 ` Palmer Dabbelt
  12 siblings, 2 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-20  6:41 UTC (permalink / raw)
  To: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing
  Cc: Chen Wang

Enable SOPHGO SoC config in defconfig to allow the default
upstream kernel to boot on Milk-V Pioneer board.

Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index ab86ec3b9eab..bf737cfa1d2c 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -32,6 +32,7 @@ CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SOC_VIRT=y
+CONFIG_ARCH_SOPHGO=y
 CONFIG_SMP=y
 CONFIG_HOTPLUG_CPU=y
 CONFIG_PM=y
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 11/11] riscv: defconfig: enable SOPHGO SoC
  2023-09-20  6:41 ` [PATCH v2 11/11] riscv: defconfig: enable SOPHGO SoC Chen Wang
@ 2023-09-20  8:06   ` Guo Ren
  2023-09-20  8:58   ` Conor Dooley
  1 sibling, 0 replies; 67+ messages in thread
From: Guo Ren @ 2023-09-20  8:06 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, jszhang,
	krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
	paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

On Wed, Sep 20, 2023 at 2:41 PM Chen Wang <unicornxw@gmail.com> wrote:
>
> Enable SOPHGO SoC config in defconfig to allow the default
> upstream kernel to boot on Milk-V Pioneer board.
>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> ---
>  arch/riscv/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index ab86ec3b9eab..bf737cfa1d2c 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -32,6 +32,7 @@ CONFIG_SOC_SIFIVE=y
>  CONFIG_SOC_STARFIVE=y
>  CONFIG_ARCH_SUNXI=y
>  CONFIG_SOC_VIRT=y
> +CONFIG_ARCH_SOPHGO=y
>  CONFIG_SMP=y
>  CONFIG_HOTPLUG_CPU=y
>  CONFIG_PM=y
> --
> 2.25.1
>
LGTM

Reviewed-by: Guo Ren <guoren@kernel.org>

-- 
Best Regards
 Guo Ren

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 11/11] riscv: defconfig: enable SOPHGO SoC
  2023-09-20  6:41 ` [PATCH v2 11/11] riscv: defconfig: enable SOPHGO SoC Chen Wang
  2023-09-20  8:06   ` Guo Ren
@ 2023-09-20  8:58   ` Conor Dooley
  1 sibling, 0 replies; 67+ messages in thread
From: Conor Dooley @ 2023-09-20  8:58 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

[-- Attachment #1: Type: text/plain, Size: 785 bytes --]

On Wed, Sep 20, 2023 at 02:41:12PM +0800, Chen Wang wrote:
> Enable SOPHGO SoC config in defconfig to allow the default
> upstream kernel to boot on Milk-V Pioneer board.
> 
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> ---
>  arch/riscv/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index ab86ec3b9eab..bf737cfa1d2c 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -32,6 +32,7 @@ CONFIG_SOC_SIFIVE=y
>  CONFIG_SOC_STARFIVE=y
>  CONFIG_ARCH_SUNXI=y
>  CONFIG_SOC_VIRT=y
> +CONFIG_ARCH_SOPHGO=y
>  CONFIG_SMP=y
>  CONFIG_HOTPLUG_CPU=y
>  CONFIG_PM=y
> -- 
> 2.25.1
> 

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^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support
  2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
                   ` (10 preceding siblings ...)
  2023-09-20  6:41 ` [PATCH v2 11/11] riscv: defconfig: enable SOPHGO SoC Chen Wang
@ 2023-09-20 10:01 ` Conor Dooley
  2023-09-22 10:24   ` Chen Wang
  2023-09-20 15:22 ` Palmer Dabbelt
  12 siblings, 1 reply; 67+ messages in thread
From: Conor Dooley @ 2023-09-20 10:01 UTC (permalink / raw)
  To: Chen Wang
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

[-- Attachment #1: Type: text/plain, Size: 4824 bytes --]

On Wed, Sep 20, 2023 at 02:33:48PM +0800, Chen Wang wrote:
> Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> in a standard mATX form factor. Add minimal device
> tree files for the SG2042 SOC and the Milk-V Pioneer board.

Please run dtbs_check with W=1 set & fix the below issues:

sg2042-cpus.dtsi:1600.25-1607.5: Warning (unit_address_vs_reg): /cpus/l2-cache@0: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1609.25-1616.5: Warning (unit_address_vs_reg): /cpus/l2-cache@1: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1618.25-1625.5: Warning (unit_address_vs_reg): /cpus/l2-cache@2: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1627.25-1634.5: Warning (unit_address_vs_reg): /cpus/l2-cache@3: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1636.25-1643.5: Warning (unit_address_vs_reg): /cpus/l2-cache@4: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1645.25-1652.5: Warning (unit_address_vs_reg): /cpus/l2-cache@5: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1654.25-1661.5: Warning (unit_address_vs_reg): /cpus/l2-cache@6: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1663.25-1670.5: Warning (unit_address_vs_reg): /cpus/l2-cache@7: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1672.25-1679.5: Warning (unit_address_vs_reg): /cpus/l2-cache@8: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1681.25-1688.5: Warning (unit_address_vs_reg): /cpus/l2-cache@9: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1690.27-1697.5: Warning (unit_address_vs_reg): /cpus/l2-cache@10: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1699.27-1706.5: Warning (unit_address_vs_reg): /cpus/l2-cache@11: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1708.27-1715.5: Warning (unit_address_vs_reg): /cpus/l2-cache@12: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1717.27-1724.5: Warning (unit_address_vs_reg): /cpus/l2-cache@13: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1726.27-1733.5: Warning (unit_address_vs_reg): /cpus/l2-cache@14: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:1735.27-1742.5: Warning (unit_address_vs_reg): /cpus/l2-cache@15: node has a unit name, but no reg or ranges property
sg2042-cpus.dtsi:256.15-275.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@0: duplicate unit-address (also used in node /cpus/l2-cache@0)
sg2042-cpus.dtsi:277.15-296.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@1: duplicate unit-address (also used in node /cpus/l2-cache@1)
sg2042-cpus.dtsi:298.15-317.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@2: duplicate unit-address (also used in node /cpus/l2-cache@2)
sg2042-cpus.dtsi:319.15-338.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@3: duplicate unit-address (also used in node /cpus/l2-cache@3)
sg2042-cpus.dtsi:340.15-359.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@4: duplicate unit-address (also used in node /cpus/l2-cache@4)
sg2042-cpus.dtsi:361.15-380.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@5: duplicate unit-address (also used in node /cpus/l2-cache@5)
sg2042-cpus.dtsi:382.15-401.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@6: duplicate unit-address (also used in node /cpus/l2-cache@6)
sg2042-cpus.dtsi:403.15-422.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@7: duplicate unit-address (also used in node /cpus/l2-cache@7)
sg2042-cpus.dtsi:424.15-443.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@8: duplicate unit-address (also used in node /cpus/l2-cache@8)
sg2042-cpus.dtsi:445.15-464.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@9: duplicate unit-address (also used in node /cpus/l2-cache@9)
sg2042-cpus.dtsi:466.17-485.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@10: duplicate unit-address (also used in node /cpus/l2-cache@10)
sg2042-cpus.dtsi:487.17-506.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@11: duplicate unit-address (also used in node /cpus/l2-cache@11)
sg2042-cpus.dtsi:508.17-527.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@12: duplicate unit-address (also used in node /cpus/l2-cache@12)
sg2042-cpus.dtsi:529.17-548.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@13: duplicate unit-address (also used in node /cpus/l2-cache@13)
sg2042-cpus.dtsi:550.17-569.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@14: duplicate unit-address (also used in node /cpus/l2-cache@14)
sg2042-cpus.dtsi:571.17-590.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@15: duplicate unit-address (also used in node /cpus/l2-cache@15)

Thanks,
Conor.

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^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support
  2023-09-20 10:01 ` [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Conor Dooley
@ 2023-09-22 10:24   ` Chen Wang
  2023-09-22 10:50     ` Conor Dooley
  0 siblings, 1 reply; 67+ messages in thread
From: Chen Wang @ 2023-09-22 10:24 UTC (permalink / raw)
  To: Conor Dooley
  Cc: aou, chao.wei, conor, devicetree, emil.renner.berthing, guoren,
	jszhang, krzysztof.kozlowski+dt, linux-kernel, linux-riscv,
	palmer, paul.walmsley, robh+dt, xiaoguang.xing, Chen Wang

Regards,

unicornx

Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 18:01写道：
>
> On Wed, Sep 20, 2023 at 02:33:48PM +0800, Chen Wang wrote:
> > Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> > in a standard mATX form factor. Add minimal device
> > tree files for the SG2042 SOC and the Milk-V Pioneer board.
>
> Please run dtbs_check with W=1 set & fix the below issues:
>
> sg2042-cpus.dtsi:1600.25-1607.5: Warning (unit_address_vs_reg): /cpus/l2-cache@0: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1609.25-1616.5: Warning (unit_address_vs_reg): /cpus/l2-cache@1: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1618.25-1625.5: Warning (unit_address_vs_reg): /cpus/l2-cache@2: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1627.25-1634.5: Warning (unit_address_vs_reg): /cpus/l2-cache@3: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1636.25-1643.5: Warning (unit_address_vs_reg): /cpus/l2-cache@4: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1645.25-1652.5: Warning (unit_address_vs_reg): /cpus/l2-cache@5: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1654.25-1661.5: Warning (unit_address_vs_reg): /cpus/l2-cache@6: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1663.25-1670.5: Warning (unit_address_vs_reg): /cpus/l2-cache@7: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1672.25-1679.5: Warning (unit_address_vs_reg): /cpus/l2-cache@8: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1681.25-1688.5: Warning (unit_address_vs_reg): /cpus/l2-cache@9: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1690.27-1697.5: Warning (unit_address_vs_reg): /cpus/l2-cache@10: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1699.27-1706.5: Warning (unit_address_vs_reg): /cpus/l2-cache@11: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1708.27-1715.5: Warning (unit_address_vs_reg): /cpus/l2-cache@12: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1717.27-1724.5: Warning (unit_address_vs_reg): /cpus/l2-cache@13: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1726.27-1733.5: Warning (unit_address_vs_reg): /cpus/l2-cache@14: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:1735.27-1742.5: Warning (unit_address_vs_reg): /cpus/l2-cache@15: node has a unit name, but no reg or ranges property
> sg2042-cpus.dtsi:256.15-275.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@0: duplicate unit-address (also used in node /cpus/l2-cache@0)
> sg2042-cpus.dtsi:277.15-296.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@1: duplicate unit-address (also used in node /cpus/l2-cache@1)
> sg2042-cpus.dtsi:298.15-317.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@2: duplicate unit-address (also used in node /cpus/l2-cache@2)
> sg2042-cpus.dtsi:319.15-338.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@3: duplicate unit-address (also used in node /cpus/l2-cache@3)
> sg2042-cpus.dtsi:340.15-359.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@4: duplicate unit-address (also used in node /cpus/l2-cache@4)
> sg2042-cpus.dtsi:361.15-380.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@5: duplicate unit-address (also used in node /cpus/l2-cache@5)
> sg2042-cpus.dtsi:382.15-401.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@6: duplicate unit-address (also used in node /cpus/l2-cache@6)
> sg2042-cpus.dtsi:403.15-422.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@7: duplicate unit-address (also used in node /cpus/l2-cache@7)
> sg2042-cpus.dtsi:424.15-443.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@8: duplicate unit-address (also used in node /cpus/l2-cache@8)
> sg2042-cpus.dtsi:445.15-464.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@9: duplicate unit-address (also used in node /cpus/l2-cache@9)
> sg2042-cpus.dtsi:466.17-485.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@10: duplicate unit-address (also used in node /cpus/l2-cache@10)
> sg2042-cpus.dtsi:487.17-506.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@11: duplicate unit-address (also used in node /cpus/l2-cache@11)
> sg2042-cpus.dtsi:508.17-527.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@12: duplicate unit-address (also used in node /cpus/l2-cache@12)
> sg2042-cpus.dtsi:529.17-548.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@13: duplicate unit-address (also used in node /cpus/l2-cache@13)
> sg2042-cpus.dtsi:550.17-569.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@14: duplicate unit-address (also used in node /cpus/l2-cache@14)
> sg2042-cpus.dtsi:571.17-590.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@15: duplicate unit-address (also used in node /cpus/l2-cache@15)
>
> Thanks,
> Conor.

I find the rootcause is due to following code in DTS:
```
                l2_cache0: l2-cache@0 {
                        compatible = "cache";
                        cache-block-size = <64>;
                        cache-level = <2>;
                        cache-size = <1048576>;
                        cache-sets = <1024>;
                        cache-unified;
                };
```
To differ 16 l2-cache controller, we add <unit-address>, but due to
the l2-cache controller on sg2042 has no address, no reg property is
added here. That's why dtbs_check warns "node has a unit name, but no
reg or ranges property". I just double-confirmed with sophgo
engineers, they  told me there is really no address for the cache
controller for sg2042.

One solution I use here is to provide unique name for the l2-cache
node. I learn this from  "arch/arm64/boot/dts/hisilicon/hi3660.dtsi"
and seems this work and pass dtbs_check with W=1. For example:
```
                l2_cache0: l2-cache0 {
                        compatible = "cache";
                        cache-block-size = <64>;
                        cache-level = <2>;
                        cache-size = <1048576>;
                        cache-sets = <1024>;
                        cache-unified;
                };

                l2_cache1: l2-cache1 {
                        compatible = "cache";
                        cache-block-size = <64>;
                        cache-level = <2>;
                        cache-size = <1048576>;
                        cache-sets = <1024>;
                        cache-unified;
                };
                ......
```
But I remember as mentioned in
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation,
node names should be generic. So I have two questions here:
- Should I use "cache-controller" instead of "l2-cache", though I see
"l2-cache" is used in many places but not listed in
devicetree-specification.
- Even if I replace "l2-cache" with "cache-controller", I think
"cache-controller0", "cache-controller1" ... are not generic name, but
due to sg2042 does not have address for cache controller, how to
handle this problem?

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support
  2023-09-22 10:24   ` Chen Wang
@ 2023-09-22 10:50     ` Conor Dooley
  2023-09-22 11:28       ` Chen Wang
  0 siblings, 1 reply; 67+ messages in thread
From: Conor Dooley @ 2023-09-22 10:50 UTC (permalink / raw)
  To: Chen Wang
  Cc: Conor Dooley, aou, chao.wei, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing,
	Chen Wang

[-- Attachment #1: Type: text/plain, Size: 7831 bytes --]

On Fri, Sep 22, 2023 at 06:24:25PM +0800, Chen Wang wrote:
> Regards,
> 
> unicornx
> 
> Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 18:01写道：
> >
> > On Wed, Sep 20, 2023 at 02:33:48PM +0800, Chen Wang wrote:
> > > Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> > > in a standard mATX form factor. Add minimal device
> > > tree files for the SG2042 SOC and the Milk-V Pioneer board.
> >
> > Please run dtbs_check with W=1 set & fix the below issues:
> >
> > sg2042-cpus.dtsi:1600.25-1607.5: Warning (unit_address_vs_reg): /cpus/l2-cache@0: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1609.25-1616.5: Warning (unit_address_vs_reg): /cpus/l2-cache@1: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1618.25-1625.5: Warning (unit_address_vs_reg): /cpus/l2-cache@2: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1627.25-1634.5: Warning (unit_address_vs_reg): /cpus/l2-cache@3: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1636.25-1643.5: Warning (unit_address_vs_reg): /cpus/l2-cache@4: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1645.25-1652.5: Warning (unit_address_vs_reg): /cpus/l2-cache@5: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1654.25-1661.5: Warning (unit_address_vs_reg): /cpus/l2-cache@6: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1663.25-1670.5: Warning (unit_address_vs_reg): /cpus/l2-cache@7: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1672.25-1679.5: Warning (unit_address_vs_reg): /cpus/l2-cache@8: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1681.25-1688.5: Warning (unit_address_vs_reg): /cpus/l2-cache@9: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1690.27-1697.5: Warning (unit_address_vs_reg): /cpus/l2-cache@10: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1699.27-1706.5: Warning (unit_address_vs_reg): /cpus/l2-cache@11: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1708.27-1715.5: Warning (unit_address_vs_reg): /cpus/l2-cache@12: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1717.27-1724.5: Warning (unit_address_vs_reg): /cpus/l2-cache@13: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1726.27-1733.5: Warning (unit_address_vs_reg): /cpus/l2-cache@14: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:1735.27-1742.5: Warning (unit_address_vs_reg): /cpus/l2-cache@15: node has a unit name, but no reg or ranges property
> > sg2042-cpus.dtsi:256.15-275.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@0: duplicate unit-address (also used in node /cpus/l2-cache@0)
> > sg2042-cpus.dtsi:277.15-296.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@1: duplicate unit-address (also used in node /cpus/l2-cache@1)
> > sg2042-cpus.dtsi:298.15-317.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@2: duplicate unit-address (also used in node /cpus/l2-cache@2)
> > sg2042-cpus.dtsi:319.15-338.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@3: duplicate unit-address (also used in node /cpus/l2-cache@3)
> > sg2042-cpus.dtsi:340.15-359.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@4: duplicate unit-address (also used in node /cpus/l2-cache@4)
> > sg2042-cpus.dtsi:361.15-380.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@5: duplicate unit-address (also used in node /cpus/l2-cache@5)
> > sg2042-cpus.dtsi:382.15-401.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@6: duplicate unit-address (also used in node /cpus/l2-cache@6)
> > sg2042-cpus.dtsi:403.15-422.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@7: duplicate unit-address (also used in node /cpus/l2-cache@7)
> > sg2042-cpus.dtsi:424.15-443.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@8: duplicate unit-address (also used in node /cpus/l2-cache@8)
> > sg2042-cpus.dtsi:445.15-464.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@9: duplicate unit-address (also used in node /cpus/l2-cache@9)
> > sg2042-cpus.dtsi:466.17-485.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@10: duplicate unit-address (also used in node /cpus/l2-cache@10)
> > sg2042-cpus.dtsi:487.17-506.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@11: duplicate unit-address (also used in node /cpus/l2-cache@11)
> > sg2042-cpus.dtsi:508.17-527.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@12: duplicate unit-address (also used in node /cpus/l2-cache@12)
> > sg2042-cpus.dtsi:529.17-548.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@13: duplicate unit-address (also used in node /cpus/l2-cache@13)
> > sg2042-cpus.dtsi:550.17-569.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@14: duplicate unit-address (also used in node /cpus/l2-cache@14)
> > sg2042-cpus.dtsi:571.17-590.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@15: duplicate unit-address (also used in node /cpus/l2-cache@15)
> >
> > Thanks,
> > Conor.
> 
> I find the rootcause is due to following code in DTS:
> ```
>                 l2_cache0: l2-cache@0 {
>                         compatible = "cache";
>                         cache-block-size = <64>;
>                         cache-level = <2>;
>                         cache-size = <1048576>;
>                         cache-sets = <1024>;
>                         cache-unified;
>                 };
> ```
> To differ 16 l2-cache controller, we add <unit-address>, but due to
> the l2-cache controller on sg2042 has no address, no reg property is
> added here. That's why dtbs_check warns "node has a unit name, but no
> reg or ranges property". I just double-confirmed with sophgo
> engineers, they  told me there is really no address for the cache
> controller for sg2042.
> 
> One solution I use here is to provide unique name for the l2-cache
> node. I learn this from  "arch/arm64/boot/dts/hisilicon/hi3660.dtsi"
> and seems this work and pass dtbs_check with W=1. For example:
> ```
>                 l2_cache0: l2-cache0 {
>                         compatible = "cache";
>                         cache-block-size = <64>;
>                         cache-level = <2>;
>                         cache-size = <1048576>;
>                         cache-sets = <1024>;
>                         cache-unified;
>                 };
> 
>                 l2_cache1: l2-cache1 {
>                         compatible = "cache";
>                         cache-block-size = <64>;
>                         cache-level = <2>;
>                         cache-size = <1048576>;
>                         cache-sets = <1024>;
>                         cache-unified;
>                 };
>                 ......
> ```
> But I remember as mentioned in
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation,
> node names should be generic. So I have two questions here:
> - Should I use "cache-controller" instead of "l2-cache", though I see
> "l2-cache" is used in many places but not listed in
> devicetree-specification.
> - Even if I replace "l2-cache" with "cache-controller", I think
> "cache-controller0", "cache-controller1" ... are not generic name, but
> due to sg2042 does not have address for cache controller, how to
> handle this problem?

I would go for "cache-controller-0" "cache-controller-1". Close as
possible to the generic node name while having the required differences
between nodes. There's already some examples in-tree (eg renesas) that
do this.

Thanks,
Conor.

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support
  2023-09-22 10:50     ` Conor Dooley
@ 2023-09-22 11:28       ` Chen Wang
  0 siblings, 0 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-22 11:28 UTC (permalink / raw)
  To: Conor Dooley
  Cc: Conor Dooley, aou, chao.wei, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, palmer, paul.walmsley, robh+dt, xiaoguang.xing,
	Chen Wang

Regards,

unicornx

Conor Dooley <conor@kernel.org> 于2023年9月22日周五 18:50写道：
>
> On Fri, Sep 22, 2023 at 06:24:25PM +0800, Chen Wang wrote:
> > Regards,
> >
> > unicornx
> >
> > Conor Dooley <conor.dooley@microchip.com> 于2023年9月20日周三 18:01写道：
> > >
> > > On Wed, Sep 20, 2023 at 02:33:48PM +0800, Chen Wang wrote:
> > > > Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> > > > in a standard mATX form factor. Add minimal device
> > > > tree files for the SG2042 SOC and the Milk-V Pioneer board.
> > >
> > > Please run dtbs_check with W=1 set & fix the below issues:
> > >
> > > sg2042-cpus.dtsi:1600.25-1607.5: Warning (unit_address_vs_reg): /cpus/l2-cache@0: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1609.25-1616.5: Warning (unit_address_vs_reg): /cpus/l2-cache@1: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1618.25-1625.5: Warning (unit_address_vs_reg): /cpus/l2-cache@2: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1627.25-1634.5: Warning (unit_address_vs_reg): /cpus/l2-cache@3: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1636.25-1643.5: Warning (unit_address_vs_reg): /cpus/l2-cache@4: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1645.25-1652.5: Warning (unit_address_vs_reg): /cpus/l2-cache@5: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1654.25-1661.5: Warning (unit_address_vs_reg): /cpus/l2-cache@6: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1663.25-1670.5: Warning (unit_address_vs_reg): /cpus/l2-cache@7: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1672.25-1679.5: Warning (unit_address_vs_reg): /cpus/l2-cache@8: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1681.25-1688.5: Warning (unit_address_vs_reg): /cpus/l2-cache@9: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1690.27-1697.5: Warning (unit_address_vs_reg): /cpus/l2-cache@10: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1699.27-1706.5: Warning (unit_address_vs_reg): /cpus/l2-cache@11: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1708.27-1715.5: Warning (unit_address_vs_reg): /cpus/l2-cache@12: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1717.27-1724.5: Warning (unit_address_vs_reg): /cpus/l2-cache@13: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1726.27-1733.5: Warning (unit_address_vs_reg): /cpus/l2-cache@14: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:1735.27-1742.5: Warning (unit_address_vs_reg): /cpus/l2-cache@15: node has a unit name, but no reg or ranges property
> > > sg2042-cpus.dtsi:256.15-275.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@0: duplicate unit-address (also used in node /cpus/l2-cache@0)
> > > sg2042-cpus.dtsi:277.15-296.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@1: duplicate unit-address (also used in node /cpus/l2-cache@1)
> > > sg2042-cpus.dtsi:298.15-317.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@2: duplicate unit-address (also used in node /cpus/l2-cache@2)
> > > sg2042-cpus.dtsi:319.15-338.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@3: duplicate unit-address (also used in node /cpus/l2-cache@3)
> > > sg2042-cpus.dtsi:340.15-359.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@4: duplicate unit-address (also used in node /cpus/l2-cache@4)
> > > sg2042-cpus.dtsi:361.15-380.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@5: duplicate unit-address (also used in node /cpus/l2-cache@5)
> > > sg2042-cpus.dtsi:382.15-401.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@6: duplicate unit-address (also used in node /cpus/l2-cache@6)
> > > sg2042-cpus.dtsi:403.15-422.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@7: duplicate unit-address (also used in node /cpus/l2-cache@7)
> > > sg2042-cpus.dtsi:424.15-443.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@8: duplicate unit-address (also used in node /cpus/l2-cache@8)
> > > sg2042-cpus.dtsi:445.15-464.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@9: duplicate unit-address (also used in node /cpus/l2-cache@9)
> > > sg2042-cpus.dtsi:466.17-485.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@10: duplicate unit-address (also used in node /cpus/l2-cache@10)
> > > sg2042-cpus.dtsi:487.17-506.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@11: duplicate unit-address (also used in node /cpus/l2-cache@11)
> > > sg2042-cpus.dtsi:508.17-527.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@12: duplicate unit-address (also used in node /cpus/l2-cache@12)
> > > sg2042-cpus.dtsi:529.17-548.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@13: duplicate unit-address (also used in node /cpus/l2-cache@13)
> > > sg2042-cpus.dtsi:550.17-569.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@14: duplicate unit-address (also used in node /cpus/l2-cache@14)
> > > sg2042-cpus.dtsi:571.17-590.5: Warning (unique_unit_address_if_enabled): /cpus/cpu@15: duplicate unit-address (also used in node /cpus/l2-cache@15)
> > >
> > > Thanks,
> > > Conor.
> >
> > I find the rootcause is due to following code in DTS:
> > ```
> >                 l2_cache0: l2-cache@0 {
> >                         compatible = "cache";
> >                         cache-block-size = <64>;
> >                         cache-level = <2>;
> >                         cache-size = <1048576>;
> >                         cache-sets = <1024>;
> >                         cache-unified;
> >                 };
> > ```
> > To differ 16 l2-cache controller, we add <unit-address>, but due to
> > the l2-cache controller on sg2042 has no address, no reg property is
> > added here. That's why dtbs_check warns "node has a unit name, but no
> > reg or ranges property". I just double-confirmed with sophgo
> > engineers, they  told me there is really no address for the cache
> > controller for sg2042.
> >
> > One solution I use here is to provide unique name for the l2-cache
> > node. I learn this from  "arch/arm64/boot/dts/hisilicon/hi3660.dtsi"
> > and seems this work and pass dtbs_check with W=1. For example:
> > ```
> >                 l2_cache0: l2-cache0 {
> >                         compatible = "cache";
> >                         cache-block-size = <64>;
> >                         cache-level = <2>;
> >                         cache-size = <1048576>;
> >                         cache-sets = <1024>;
> >                         cache-unified;
> >                 };
> >
> >                 l2_cache1: l2-cache1 {
> >                         compatible = "cache";
> >                         cache-block-size = <64>;
> >                         cache-level = <2>;
> >                         cache-size = <1048576>;
> >                         cache-sets = <1024>;
> >                         cache-unified;
> >                 };
> >                 ......
> > ```
> > But I remember as mentioned in
> > https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation,
> > node names should be generic. So I have two questions here:
> > - Should I use "cache-controller" instead of "l2-cache", though I see
> > "l2-cache" is used in many places but not listed in
> > devicetree-specification.
> > - Even if I replace "l2-cache" with "cache-controller", I think
> > "cache-controller0", "cache-controller1" ... are not generic name, but
> > due to sg2042 does not have address for cache controller, how to
> > handle this problem?
>
> I would go for "cache-controller-0" "cache-controller-1". Close as
> possible to the generic node name while having the required differences
> between nodes. There's already some examples in-tree (eg renesas) that
> do this.
>
> Thanks,
> Conor.

Got, thanks.

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support
  2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
                   ` (11 preceding siblings ...)
  2023-09-20 10:01 ` [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Conor Dooley
@ 2023-09-20 15:22 ` Palmer Dabbelt
  2023-09-26 10:29   ` Chen Wang
  12 siblings, 1 reply; 67+ messages in thread
From: Palmer Dabbelt @ 2023-09-20 15:22 UTC (permalink / raw)
  To: unicornxw
  Cc: aou, chao.wei, Conor Dooley, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, Paul Walmsley, robh+dt, xiaoguang.xing, wangchen20

On Tue, 19 Sep 2023 23:33:48 PDT (-0700), unicornxw@gmail.com wrote:
> Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> in a standard mATX form factor. Add minimal device
> tree files for the SG2042 SOC and the Milk-V Pioneer board.
>
> Now only support basic uart drivers to boot up into a basic console.
>
> Thanks,
> Chen
>
> ---
>
> Changes in v2:
>   The patch series is based on v6.6-rc1. You can simply review or test
>   the patches at the link [4].
>   - Improve format for comment of commitments as per input from last review.
>   - Improve format of DTS as per input from last review.
>   - Remove numa related stuff from DTS. This part is just for optimization, may
>     add it later if really needed.
>
> Previous versions:
> v1: due to it is not sent in thread, I have listed permlinks of the patchset
>     [v1-0/12] ~ [v1-12/12] here for quick reference. You can simply review or
>     test the patches at the link [3].
>
> [1]: https://milkv.io/pioneer
> [2]: https://en.sophgo.com/product/introduce/sg2042.html
> [3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
> [4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
> [v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
> [v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
> [v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
> [v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
> [v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
> [v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
> [v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
> [v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
> [v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
> [v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
> [v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
> [v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
> [v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
>
> ---
>
> Chen Wang (8):
>   riscv: Add SOPHGO SOC family Kconfig support
>   dt-bindings: vendor-prefixes: add milkv/sophgo
>   dt-bindings: riscv: add sophgo sg2042 bindings
>   dt-bindings: riscv: Add T-HEAD C920 compatibles
>   dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC
>   riscv: dts: add initial SOPHGO SG2042 SoC device tree
>   riscv: dts: sophgo: add Milk-V Pioneer board device tree
>   riscv: defconfig: enable SOPHGO SoC
>
> Emil Renner Berthing (2):
>   dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts
>   serial: 8250_dw: Add Sophgo SG2042 support
>
> Inochi Amaoto (1):
>   dt-bindings: timer: Add Sophgo sg2042 clint
>
>  .../sifive,plic-1.0.0.yaml                    |    1 +
>  .../devicetree/bindings/riscv/cpus.yaml       |    1 +
>  .../devicetree/bindings/riscv/sophgo.yaml     |   28 +
>  .../bindings/serial/snps-dw-apb-uart.yaml     |    1 +
>  .../bindings/timer/sifive,clint.yaml          |    8 +
>  .../devicetree/bindings/vendor-prefixes.yaml  |    4 +
>  MAINTAINERS                                   |    7 +
>  arch/riscv/Kconfig.socs                       |    5 +
>  arch/riscv/boot/dts/Makefile                  |    1 +
>  arch/riscv/boot/dts/sophgo/Makefile           |    3 +
>  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi   | 1744 +++++++++++++++++
>  .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |   19 +
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  439 +++++
>  arch/riscv/configs/defconfig                  |    1 +
>  drivers/tty/serial/8250/8250_dw.c             |    5 +-
>  15 files changed, 2265 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
>  create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi

Given this is the first sg2042 and it appears to have a few errata (the 
FP rounding issues and the special fence for starvation), I think we 
want to make sure we figure out how to provide that information to 
userspace.

> base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d

^ permalink raw reply	[flat|nested] 67+ messages in thread

* Re: [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support
  2023-09-20 15:22 ` Palmer Dabbelt
@ 2023-09-26 10:29   ` Chen Wang
  0 siblings, 0 replies; 67+ messages in thread
From: Chen Wang @ 2023-09-26 10:29 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: aou, chao.wei, Conor Dooley, devicetree, emil.renner.berthing,
	guoren, jszhang, krzysztof.kozlowski+dt, linux-kernel,
	linux-riscv, Paul Walmsley, robh+dt, xiaoguang.xing, wangchen20

Palmer Dabbelt <palmer@dabbelt.com> 于2023年9月20日周三 23:22写道：
>
> On Tue, 19 Sep 2023 23:33:48 PDT (-0700), unicornxw@gmail.com wrote:
> > Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> > in a standard mATX form factor. Add minimal device
> > tree files for the SG2042 SOC and the Milk-V Pioneer board.
> >
> > Now only support basic uart drivers to boot up into a basic console.
> >
> > Thanks,
> > Chen
> >
> > ---
> >
> > Changes in v2:
> >   The patch series is based on v6.6-rc1. You can simply review or test
> >   the patches at the link [4].
> >   - Improve format for comment of commitments as per input from last review.
> >   - Improve format of DTS as per input from last review.
> >   - Remove numa related stuff from DTS. This part is just for optimization, may
> >     add it later if really needed.
> >
> > Previous versions:
> > v1: due to it is not sent in thread, I have listed permlinks of the patchset
> >     [v1-0/12] ~ [v1-12/12] here for quick reference. You can simply review or
> >     test the patches at the link [3].
> >
> > [1]: https://milkv.io/pioneer
> > [2]: https://en.sophgo.com/product/introduce/sg2042.html
> > [3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
> > [4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
> > [v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
> > [v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
> > [v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
> > [v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
> > [v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
> > [v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
> > [v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
> > [v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
> > [v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
> > [v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
> > [v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
> > [v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
> > [v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
> >
> > ---
> >
> > Chen Wang (8):
> >   riscv: Add SOPHGO SOC family Kconfig support
> >   dt-bindings: vendor-prefixes: add milkv/sophgo
> >   dt-bindings: riscv: add sophgo sg2042 bindings
> >   dt-bindings: riscv: Add T-HEAD C920 compatibles
> >   dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC
> >   riscv: dts: add initial SOPHGO SG2042 SoC device tree
> >   riscv: dts: sophgo: add Milk-V Pioneer board device tree
> >   riscv: defconfig: enable SOPHGO SoC
> >
> > Emil Renner Berthing (2):
> >   dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts
> >   serial: 8250_dw: Add Sophgo SG2042 support
> >
> > Inochi Amaoto (1):
> >   dt-bindings: timer: Add Sophgo sg2042 clint
> >
> >  .../sifive,plic-1.0.0.yaml                    |    1 +
> >  .../devicetree/bindings/riscv/cpus.yaml       |    1 +
> >  .../devicetree/bindings/riscv/sophgo.yaml     |   28 +
> >  .../bindings/serial/snps-dw-apb-uart.yaml     |    1 +
> >  .../bindings/timer/sifive,clint.yaml          |    8 +
> >  .../devicetree/bindings/vendor-prefixes.yaml  |    4 +
> >  MAINTAINERS                                   |    7 +
> >  arch/riscv/Kconfig.socs                       |    5 +
> >  arch/riscv/boot/dts/Makefile                  |    1 +
> >  arch/riscv/boot/dts/sophgo/Makefile           |    3 +
> >  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi   | 1744 +++++++++++++++++
> >  .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |   19 +
> >  arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  439 +++++
> >  arch/riscv/configs/defconfig                  |    1 +
> >  drivers/tty/serial/8250/8250_dw.c             |    5 +-
> >  15 files changed, 2265 insertions(+), 2 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
> >  create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
> >  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> >  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> >  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
>
> Given this is the first sg2042 and it appears to have a few errata (the
> FP rounding issues and the special fence for starvation), I think we
> want to make sure we figure out how to provide that information to
> userspace.
>

Hi, Palmer,
I don't  understand well what's your meaning of "provide that
information to userspace", can you please clarify more?
And for this patchset, do we still lack something else? This patchset
is the first one for sg2042, but I don't see those issues you
mentioned would block it, becasue the target of this first patchset we
just want to make sure the kernel can boot up and work with a uart
console.

Thanks in adv.
Chen


> > base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d

^ permalink raw reply	[flat|nested] 67+ messages in thread

end of thread, other threads:[~2023-09-26 10:29 UTC | newest]

Thread overview: 67+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-09-20  6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
2023-09-20  6:34 ` [PATCH v2 01/11] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
2023-09-20  7:34   ` Guo Ren
2023-09-20  8:21   ` Conor Dooley
2023-09-20  6:37 ` [PATCH v2 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo Chen Wang
2023-09-20  7:38   ` Guo Ren
2023-09-20  8:22   ` Conor Dooley
2023-09-20  9:14     ` Chen Wang
2023-09-20  6:37 ` [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings Chen Wang
2023-09-20  7:43   ` Guo Ren
2023-09-20  8:28   ` Conor Dooley
2023-09-21 10:21     ` Chen Wang
2023-09-21 12:18       ` Conor Dooley
2023-09-21 13:40         ` Chen Wang
2023-09-21 13:51         ` Chen Wang
2023-09-21 14:00           ` Conor Dooley
2023-09-22  1:48     ` Chen Wang
2023-09-20 11:55   ` Krzysztof Kozlowski
2023-09-20 12:03     ` 汪辰
2023-09-21  0:48       ` Jisheng Zhang
2023-09-20  6:38 ` [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles Chen Wang
2023-09-20  7:44   ` Guo Ren
2023-09-20  8:37   ` Conor Dooley
2023-09-20  6:39 ` [PATCH v2 05/11] dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC Chen Wang
2023-09-20  7:45   ` Guo Ren
2023-09-20  8:57   ` Conor Dooley
2023-09-20  6:39 ` [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint Chen Wang
2023-09-20  8:12   ` Guo Ren
2023-09-20  8:50   ` Conor Dooley
2023-09-20 11:57   ` Krzysztof Kozlowski
2023-09-20  6:39 ` [PATCH v2 07/11] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts Chen Wang
2023-09-20  7:51   ` Guo Ren
2023-09-20  8:37   ` Conor Dooley
2023-09-20  6:40 ` [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support Chen Wang
2023-09-20  7:53   ` Guo Ren
2023-09-20  8:05     ` Chen Wang
2023-09-20  8:08       ` Guo Ren
2023-09-22  9:41   ` Ben Dooks
2023-09-22 10:40     ` Emil Renner Berthing
2023-09-22 11:39       ` Chen Wang
2023-09-26  7:38       ` Chen Wang
2023-09-20  6:40 ` [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree Chen Wang
2023-09-20  8:04   ` Guo Ren
2023-09-20  8:57   ` Conor Dooley
2023-09-21  9:56     ` Chen Wang
2023-09-21 10:15       ` Conor Dooley
2023-09-21 10:27         ` Chen Wang
2023-09-21 12:06           ` Conor Dooley
2023-09-20 11:32   ` Emil Renner Berthing
2023-09-20 12:09     ` 汪辰
2023-09-20 12:32       ` Emil Renner Berthing
2023-09-20 12:37         ` 汪辰
2023-09-20 15:19   ` Palmer Dabbelt
2023-09-20 15:31     ` Conor Dooley
2023-09-20  6:40 ` [PATCH v2 10/11] riscv: dts: sophgo: add Milk-V Pioneer board " Chen Wang
2023-09-20  8:05   ` Guo Ren
2023-09-20  8:16   ` Conor Dooley
2023-09-20 11:59   ` Krzysztof Kozlowski
2023-09-20  6:41 ` [PATCH v2 11/11] riscv: defconfig: enable SOPHGO SoC Chen Wang
2023-09-20  8:06   ` Guo Ren
2023-09-20  8:58   ` Conor Dooley
2023-09-20 10:01 ` [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Conor Dooley
2023-09-22 10:24   ` Chen Wang
2023-09-22 10:50     ` Conor Dooley
2023-09-22 11:28       ` Chen Wang
2023-09-20 15:22 ` Palmer Dabbelt
2023-09-26 10:29   ` Chen Wang

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