Re: Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree

汪辰
2023-09-20T12:10:26Z

&gt; -----原始邮件-----
&gt; 发件人: "Emil Renner Berthing" <emil.renner.berthing@canonical.com>
&gt; 发送时间: 2023-09-20 19:32:19 (星期三)
&gt; 收件人: "Chen Wang" <unicornxw@gmail.com>, aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, emil.renner.berthing@canonical.com, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com
&gt; 抄送: "Chen Wang" <wangchen20@iscas.ac.cn>, "Inochi Amaoto" <inochiama@outlook.com>
&gt; 主题: Re: [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree
&gt;
&gt; Chen Wang wrote:
&gt; &gt; Milk-V Pioneer motherboard is powered by SOPHON's SG2042.
&gt;
&gt; Hi,
&gt;
&gt; I'm just wondering what is the relation between SOPHON and SOPHGO?
&gt; I think most of the content refers to the SoC as Sophgo SG2042 or SOPHGO
&gt; SG2042, but here you're using SOPHON.

"SOPHGO" is the company name, "SOPHON" is the brand name. The whole name of SG2042 is "SOPHON SG2042".

&gt;
&gt; Also it would be great if you could decide if it's spelled SOPHGO or Sophgo and
&gt; be consistent in all these patches.

Thanks, I will double check this in next revision.

&gt;
&gt; /Emil
&gt;
&gt; &gt;
&gt; &gt; SG2042 is server grade chip with high performance, low power
&gt; &gt; consumption and high data throughput.
&gt; &gt; Key features:
&gt; &gt; - 64 RISC-V cpu cores which implements IMAFDC
&gt; &gt; - 4 cores per cluster, 16 clusters on chip
&gt; &gt; - ......
&gt; &gt;
&gt; &gt; More info is available at [1].
&gt; &gt;
&gt; &gt; [1]: https://en.sophgo.com/product/introduce/sg2042.html
&gt; &gt;
&gt; &gt; Currently only support booting into console with only uart,
&gt; &gt; other features will be added soon later.
&gt; &gt;
&gt; &gt; Acked-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
&gt; &gt; Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
&gt; &gt; Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
&gt; &gt; Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
&gt; &gt; Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
&gt; &gt; ---
&gt; &gt; arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1744 +++++++++++++++++++
&gt; &gt; arch/riscv/boot/dts/sophgo/sg2042.dtsi | 439 +++++
&gt; &gt; 2 files changed, 2183 insertions(+)
&gt; &gt; create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
&gt; &gt; create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
&gt; &gt;
&gt; &gt; diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
&gt; &gt; new file mode 100644
&gt; &gt; index 000000000000..9fc79b1cf3bf
&gt; &gt; --- /dev/null
&gt; &gt; +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
&gt; &gt; @@ -0,0 +1,1744 @@
&gt; &gt; +// SPDX-License-Identifier: GPL-2.0 OR MIT
&gt; &gt; +/*
&gt; &gt; + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
&gt; &gt; + */
&gt; &gt; +
&gt; &gt; +/ {
&gt; &gt; + cpus {
&gt; &gt; + #address-cells = &lt;1&gt;;
&gt; &gt; + #size-cells = &lt;0&gt;;
&gt; &gt; + timebase-frequency = &lt;50000000&gt;;
&gt; &gt; +
&gt; &gt; + cpu-map {
&gt; &gt; + socket0 {
&gt; &gt; + cluster0 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu0&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu1&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu2&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu3&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster1 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu4&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu5&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu6&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu7&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster2 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu16&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu17&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu18&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu19&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster3 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu20&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu21&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu22&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu23&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster4 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu8&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu9&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu10&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu11&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster5 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu12&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu13&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu14&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu15&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster6 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu24&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu25&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu26&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu27&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster7 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu28&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu29&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu30&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu31&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster8 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu32&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu33&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu34&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu35&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster9 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu36&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu37&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu38&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu39&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster10 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu48&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu49&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu50&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu51&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster11 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu52&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu53&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu54&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu55&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster12 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu40&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu41&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu42&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu43&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster13 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu44&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu45&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu46&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu47&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster14 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu56&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu57&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu58&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu59&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cluster15 {
&gt; &gt; + core0 {
&gt; &gt; + cpu = &lt;&amp;cpu60&gt;;
&gt; &gt; + };
&gt; &gt; + core1 {
&gt; &gt; + cpu = &lt;&amp;cpu61&gt;;
&gt; &gt; + };
&gt; &gt; + core2 {
&gt; &gt; + cpu = &lt;&amp;cpu62&gt;;
&gt; &gt; + };
&gt; &gt; + core3 {
&gt; &gt; + cpu = &lt;&amp;cpu63&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu0: cpu@0 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;0&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache0&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu0_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu1: cpu@1 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;1&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache0&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu1_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu2: cpu@2 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;2&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache0&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu2_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu3: cpu@3 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;3&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache0&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu3_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu4: cpu@4 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;4&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache1&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu4_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu5: cpu@5 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;5&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache1&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu5_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu6: cpu@6 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;6&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache1&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu6_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu7: cpu@7 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;7&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache1&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu7_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu8: cpu@8 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;8&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache4&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu8_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu9: cpu@9 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;9&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache4&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu9_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu10: cpu@10 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;10&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache4&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu10_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu11: cpu@11 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;11&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache4&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu11_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu12: cpu@12 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;12&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache5&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu12_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu13: cpu@13 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;13&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache5&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu13_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu14: cpu@14 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;14&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache5&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu14_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu15: cpu@15 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;15&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache5&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu15_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu16: cpu@16 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;16&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache2&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu16_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu17: cpu@17 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;17&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache2&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu17_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu18: cpu@18 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;18&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache2&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu18_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu19: cpu@19 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;19&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache2&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu19_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu20: cpu@20 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;20&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache3&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu20_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu21: cpu@21 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;21&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache3&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu21_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu22: cpu@22 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;22&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache3&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu22_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu23: cpu@23 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;23&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache3&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu23_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu24: cpu@24 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;24&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache6&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu24_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu25: cpu@25 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;25&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache6&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu25_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu26: cpu@26 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;26&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache6&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu26_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu27: cpu@27 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;27&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache6&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu27_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu28: cpu@28 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;28&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache7&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu28_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu29: cpu@29 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;29&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache7&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu29_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu30: cpu@30 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;30&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache7&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu30_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu31: cpu@31 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;31&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache7&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu31_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu32: cpu@32 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;32&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache8&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu32_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu33: cpu@33 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;33&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache8&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu33_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu34: cpu@34 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;34&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache8&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu34_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu35: cpu@35 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;35&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache8&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu35_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu36: cpu@36 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;36&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache9&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu36_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu37: cpu@37 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;37&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache9&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu37_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu38: cpu@38 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;38&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache9&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu38_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu39: cpu@39 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;39&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache9&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu39_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu40: cpu@40 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;40&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache12&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu40_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu41: cpu@41 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;41&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache12&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu41_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu42: cpu@42 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;42&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache12&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu42_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu43: cpu@43 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;43&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache12&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu43_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu44: cpu@44 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;44&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache13&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu44_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu45: cpu@45 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;45&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache13&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu45_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu46: cpu@46 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;46&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache13&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu46_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu47: cpu@47 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;47&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache13&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu47_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu48: cpu@48 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;48&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache10&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu48_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu49: cpu@49 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;49&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache10&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu49_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu50: cpu@50 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;50&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache10&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu50_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu51: cpu@51 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;51&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache10&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu51_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu52: cpu@52 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;52&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache11&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu52_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu53: cpu@53 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;53&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache11&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu53_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu54: cpu@54 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;54&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache11&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu54_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu55: cpu@55 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;55&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache11&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu55_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu56: cpu@56 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;56&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache14&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu56_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu57: cpu@57 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;57&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache14&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu57_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu58: cpu@58 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;58&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache14&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu58_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu59: cpu@59 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;59&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache14&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu59_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu60: cpu@60 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;60&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache15&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu60_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu61: cpu@61 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;61&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache15&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu61_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu62: cpu@62 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;62&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache15&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu62_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + cpu63: cpu@63 {
&gt; &gt; + compatible = "thead,c920", "riscv";
&gt; &gt; + device_type = "cpu";
&gt; &gt; + riscv,isa = "rv64imafdc";
&gt; &gt; + reg = &lt;63&gt;;
&gt; &gt; + i-cache-block-size = &lt;64&gt;;
&gt; &gt; + i-cache-size = &lt;65536&gt;;
&gt; &gt; + i-cache-sets = &lt;512&gt;;
&gt; &gt; + d-cache-block-size = &lt;64&gt;;
&gt; &gt; + d-cache-size = &lt;65536&gt;;
&gt; &gt; + d-cache-sets = &lt;512&gt;;
&gt; &gt; + next-level-cache = &lt;&amp;l2_cache15&gt;;
&gt; &gt; + mmu-type = "riscv,sv39";
&gt; &gt; +
&gt; &gt; + cpu63_intc: interrupt-controller {
&gt; &gt; + compatible = "riscv,cpu-intc";
&gt; &gt; + interrupt-controller;
&gt; &gt; + #interrupt-cells = &lt;1&gt;;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache0: l2-cache@0 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache1: l2-cache@1 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache2: l2-cache@2 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache3: l2-cache@3 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache4: l2-cache@4 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache5: l2-cache@5 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache6: l2-cache@6 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache7: l2-cache@7 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache8: l2-cache@8 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache9: l2-cache@9 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache10: l2-cache@10 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache11: l2-cache@11 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache12: l2-cache@12 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache13: l2-cache@13 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache14: l2-cache@14 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + l2_cache15: l2-cache@15 {
&gt; &gt; + compatible = "cache";
&gt; &gt; + cache-block-size = &lt;64&gt;;
&gt; &gt; + cache-level = &lt;2&gt;;
&gt; &gt; + cache-size = &lt;1048576&gt;;
&gt; &gt; + cache-sets = &lt;1024&gt;;
&gt; &gt; + cache-unified;
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +};
&gt; &gt; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
&gt; &gt; new file mode 100644
&gt; &gt; index 000000000000..747fd9764c95
&gt; &gt; --- /dev/null
&gt; &gt; +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
&gt; &gt; @@ -0,0 +1,439 @@
&gt; &gt; +// SPDX-License-Identifier: GPL-2.0 OR MIT
&gt; &gt; +/*
&gt; &gt; + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
&gt; &gt; + */
&gt; &gt; +
&gt; &gt; +/dts-v1/;
&gt; &gt; +#include <dt-bindings interrupt-controller="" irq.h="">
&gt; &gt; +
&gt; &gt; +#include "sg2042-cpus.dtsi"
&gt; &gt; +
&gt; &gt; +#define SOC_PERIPHERAL_IRQ(nr) (nr)
&gt; &gt; +
&gt; &gt; +/ {
&gt; &gt; + compatible = "sophgo,sg2042";
&gt; &gt; + #address-cells = &lt;2&gt;;
&gt; &gt; + #size-cells = &lt;2&gt;;
&gt; &gt; + dma-noncoherent;
&gt; &gt; +
&gt; &gt; + aliases {
&gt; &gt; + serial0 = &amp;uart0;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + /* the mem node will be updated by ZSBL. */
&gt; &gt; + memory@0 {
&gt; &gt; + device_type = "memory";
&gt; &gt; + reg = &lt;0x00000000 0x00000000 0x00000000 0x00000000&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + memory@1 {
&gt; &gt; + device_type = "memory";
&gt; &gt; + reg = &lt;0x00000000 0x00000001 0x00000000 0x00000000&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + memory@2 {
&gt; &gt; + device_type = "memory";
&gt; &gt; + reg = &lt;0x00000000 0x00000002 0x00000000 0x00000000&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + memory@3 {
&gt; &gt; + device_type = "memory";
&gt; &gt; + reg = &lt;0x00000000 0x00000003 0x00000000 0x00000000&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + pmu {
&gt; &gt; + compatible = "riscv,pmu";
&gt; &gt; + riscv,event-to-mhpmevent =
&gt; &gt; + &lt;0x00003 0x00000000 0x00000010&gt;,
&gt; &gt; + &lt;0x00004 0x00000000 0x00000011&gt;,
&gt; &gt; + &lt;0x00005 0x00000000 0x00000007&gt;,
&gt; &gt; + &lt;0x00006 0x00000000 0x00000006&gt;,
&gt; &gt; + &lt;0x00008 0x00000000 0x00000027&gt;,
&gt; &gt; + &lt;0x00009 0x00000000 0x00000028&gt;,
&gt; &gt; + &lt;0x10000 0x00000000 0x0000000c&gt;,
&gt; &gt; + &lt;0x10001 0x00000000 0x0000000d&gt;,
&gt; &gt; + &lt;0x10002 0x00000000 0x0000000e&gt;,
&gt; &gt; + &lt;0x10003 0x00000000 0x0000000f&gt;,
&gt; &gt; + &lt;0x10008 0x00000000 0x00000001&gt;,
&gt; &gt; + &lt;0x10009 0x00000000 0x00000002&gt;,
&gt; &gt; + &lt;0x10010 0x00000000 0x00000010&gt;,
&gt; &gt; + &lt;0x10011 0x00000000 0x00000011&gt;,
&gt; &gt; + &lt;0x10012 0x00000000 0x00000012&gt;,
&gt; &gt; + &lt;0x10013 0x00000000 0x00000013&gt;,
&gt; &gt; + &lt;0x10019 0x00000000 0x00000004&gt;,
&gt; &gt; + &lt;0x10021 0x00000000 0x00000003&gt;,
&gt; &gt; + &lt;0x10030 0x00000000 0x0000001c&gt;,
&gt; &gt; + &lt;0x10031 0x00000000 0x0000001b&gt;;
&gt; &gt; + riscv,event-to-mhpmcounters =
&gt; &gt; + &lt;0x00003 0x00003 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00004 0x00004 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00005 0x00005 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00006 0x00006 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00007 0x00007 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00008 0x00008 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00009 0x00009 0xfffffff8&gt;,
&gt; &gt; + &lt;0x0000a 0x0000a 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10000 0x10000 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10001 0x10001 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10002 0x10002 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10003 0x10003 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10008 0x10008 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10009 0x10009 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10010 0x10010 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10011 0x10011 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10012 0x10012 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10013 0x10013 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10019 0x10019 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10021 0x10021 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10030 0x10030 0xfffffff8&gt;,
&gt; &gt; + &lt;0x10031 0x10031 0xfffffff8&gt;;
&gt; &gt; + riscv,raw-event-to-mhpmcounters =
&gt; &gt; + &lt;0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8&gt;,
&gt; &gt; + &lt;0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + soc: soc {
&gt; &gt; + compatible = "simple-bus";
&gt; &gt; + #address-cells = &lt;2&gt;;
&gt; &gt; + #size-cells = &lt;2&gt;;
&gt; &gt; + ranges;
&gt; &gt; +
&gt; &gt; + clint_mswi: interrupt-controller@7094000000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi";
&gt; &gt; + reg = &lt;0x00000070 0x94000000 0x00000000 0x00004000&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu0_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu1_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu2_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu3_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu4_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu5_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu6_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu7_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu8_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu9_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu10_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu11_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu12_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu13_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu14_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu15_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu16_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu17_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu18_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu19_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu20_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu21_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu22_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu23_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu24_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu25_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu26_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu27_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu28_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu29_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu30_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu31_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu32_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu33_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu34_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu35_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu36_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu37_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu38_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu39_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu40_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu41_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu42_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu43_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu44_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu45_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu46_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu47_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu48_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu49_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu50_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu51_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu52_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu53_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu54_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu55_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu56_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu57_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu58_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu59_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu60_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu61_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu62_intc 3&gt;,
&gt; &gt; + &lt;&amp;cpu63_intc 3&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer0: timer@70ac000000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac000000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu0_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu1_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu2_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu3_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer1: timer@70ac010000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac010000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu4_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu5_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu6_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu7_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer2: timer@70ac020000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac020000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu8_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu9_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu10_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu11_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer3: timer@70ac030000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac030000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu12_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu13_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu14_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu15_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer4: timer@70ac040000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac040000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu16_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu17_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu18_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu19_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer5: timer@70ac050000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac050000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu20_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu21_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu22_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu23_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer6: timer@70ac060000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac060000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu24_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu25_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu26_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu27_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer7: timer@70ac070000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac070000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu28_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu29_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu30_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu31_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer8: timer@70ac080000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac080000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu32_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu33_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu34_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu35_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer9: timer@70ac090000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac090000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu36_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu37_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu38_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu39_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer10: timer@70ac0a0000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac0a0000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu40_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu41_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu42_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu43_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer11: timer@70ac0b0000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac0b0000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu44_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu45_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu46_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu47_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer12: timer@70ac0c0000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac0c0000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu48_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu49_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu50_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu51_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer13: timer@70ac0d0000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac0d0000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu52_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu53_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu54_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu55_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer14: timer@70ac0e0000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac0e0000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu56_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu57_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu58_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu59_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + clint_mtimer15: timer@70ac0f0000 {
&gt; &gt; + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer";
&gt; &gt; + reg = &lt;0x00000070 0xac0f0000 0x00000000 0x00007ff8&gt;;
&gt; &gt; + interrupts-extended = &lt;&amp;cpu60_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu61_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu62_intc 7&gt;,
&gt; &gt; + &lt;&amp;cpu63_intc 7&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + intc: interrupt-controller@7090000000 {
&gt; &gt; + compatible = "sophgo,sg2042-plic", "thead,c900-plic";
&gt; &gt; + #address-cells = &lt;0&gt;;
&gt; &gt; + #interrupt-cells = &lt;2&gt;;
&gt; &gt; + reg = &lt;0x00000070 0x90000000 0x00000000 0x04000000&gt;;
&gt; &gt; + interrupt-controller;
&gt; &gt; + interrupts-extended =
&gt; &gt; + &lt;&amp;cpu0_intc 0xffffffff&gt;, &lt;&amp;cpu0_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu1_intc 0xffffffff&gt;, &lt;&amp;cpu1_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu2_intc 0xffffffff&gt;, &lt;&amp;cpu2_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu3_intc 0xffffffff&gt;, &lt;&amp;cpu3_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu4_intc 0xffffffff&gt;, &lt;&amp;cpu4_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu5_intc 0xffffffff&gt;, &lt;&amp;cpu5_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu6_intc 0xffffffff&gt;, &lt;&amp;cpu6_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu7_intc 0xffffffff&gt;, &lt;&amp;cpu7_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu8_intc 0xffffffff&gt;, &lt;&amp;cpu8_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu9_intc 0xffffffff&gt;, &lt;&amp;cpu9_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu10_intc 0xffffffff&gt;, &lt;&amp;cpu10_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu11_intc 0xffffffff&gt;, &lt;&amp;cpu11_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu12_intc 0xffffffff&gt;, &lt;&amp;cpu12_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu13_intc 0xffffffff&gt;, &lt;&amp;cpu13_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu14_intc 0xffffffff&gt;, &lt;&amp;cpu14_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu15_intc 0xffffffff&gt;, &lt;&amp;cpu15_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu16_intc 0xffffffff&gt;, &lt;&amp;cpu16_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu17_intc 0xffffffff&gt;, &lt;&amp;cpu17_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu18_intc 0xffffffff&gt;, &lt;&amp;cpu18_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu19_intc 0xffffffff&gt;, &lt;&amp;cpu19_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu20_intc 0xffffffff&gt;, &lt;&amp;cpu20_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu21_intc 0xffffffff&gt;, &lt;&amp;cpu21_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu22_intc 0xffffffff&gt;, &lt;&amp;cpu22_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu23_intc 0xffffffff&gt;, &lt;&amp;cpu23_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu24_intc 0xffffffff&gt;, &lt;&amp;cpu24_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu25_intc 0xffffffff&gt;, &lt;&amp;cpu25_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu26_intc 0xffffffff&gt;, &lt;&amp;cpu26_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu27_intc 0xffffffff&gt;, &lt;&amp;cpu27_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu28_intc 0xffffffff&gt;, &lt;&amp;cpu28_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu29_intc 0xffffffff&gt;, &lt;&amp;cpu29_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu30_intc 0xffffffff&gt;, &lt;&amp;cpu30_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu31_intc 0xffffffff&gt;, &lt;&amp;cpu31_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu32_intc 0xffffffff&gt;, &lt;&amp;cpu32_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu33_intc 0xffffffff&gt;, &lt;&amp;cpu33_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu34_intc 0xffffffff&gt;, &lt;&amp;cpu34_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu35_intc 0xffffffff&gt;, &lt;&amp;cpu35_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu36_intc 0xffffffff&gt;, &lt;&amp;cpu36_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu37_intc 0xffffffff&gt;, &lt;&amp;cpu37_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu38_intc 0xffffffff&gt;, &lt;&amp;cpu38_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu39_intc 0xffffffff&gt;, &lt;&amp;cpu39_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu40_intc 0xffffffff&gt;, &lt;&amp;cpu40_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu41_intc 0xffffffff&gt;, &lt;&amp;cpu41_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu42_intc 0xffffffff&gt;, &lt;&amp;cpu42_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu43_intc 0xffffffff&gt;, &lt;&amp;cpu43_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu44_intc 0xffffffff&gt;, &lt;&amp;cpu44_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu45_intc 0xffffffff&gt;, &lt;&amp;cpu45_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu46_intc 0xffffffff&gt;, &lt;&amp;cpu46_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu47_intc 0xffffffff&gt;, &lt;&amp;cpu47_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu48_intc 0xffffffff&gt;, &lt;&amp;cpu48_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu49_intc 0xffffffff&gt;, &lt;&amp;cpu49_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu50_intc 0xffffffff&gt;, &lt;&amp;cpu50_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu51_intc 0xffffffff&gt;, &lt;&amp;cpu51_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu52_intc 0xffffffff&gt;, &lt;&amp;cpu52_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu53_intc 0xffffffff&gt;, &lt;&amp;cpu53_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu54_intc 0xffffffff&gt;, &lt;&amp;cpu54_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu55_intc 0xffffffff&gt;, &lt;&amp;cpu55_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu56_intc 0xffffffff&gt;, &lt;&amp;cpu56_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu57_intc 0xffffffff&gt;, &lt;&amp;cpu57_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu58_intc 0xffffffff&gt;, &lt;&amp;cpu58_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu59_intc 0xffffffff&gt;, &lt;&amp;cpu59_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu60_intc 0xffffffff&gt;, &lt;&amp;cpu60_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu61_intc 0xffffffff&gt;, &lt;&amp;cpu61_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu62_intc 0xffffffff&gt;, &lt;&amp;cpu62_intc 9&gt;,
&gt; &gt; + &lt;&amp;cpu63_intc 0xffffffff&gt;, &lt;&amp;cpu63_intc 9&gt;;
&gt; &gt; + riscv,ndev = &lt;224&gt;;
&gt; &gt; + };
&gt; &gt; +
&gt; &gt; + uart0: serial@7040000000 {
&gt; &gt; + compatible = "sophgo,sg2042-uart", "snps,dw-apb-uart";
&gt; &gt; + reg = &lt;0x00000070 0x40000000 0x00000000 0x00001000&gt;;
&gt; &gt; + interrupt-parent = &lt;&amp;intc&gt;;
&gt; &gt; + interrupts = <soc_peripheral_irq(112) irq_type_level_high="">;
&gt; &gt; + clock-frequency = &lt;500000000&gt;;
&gt; &gt; + reg-shift = &lt;2&gt;;
&gt; &gt; + reg-io-width = &lt;4&gt;;
&gt; &gt; + status = "disabled";
&gt; &gt; + };
&gt; &gt; + };
&gt; &gt; +};
&gt; &gt; --
&gt; &gt; 2.25.1

------------------------------

Best Regards

汪辰(Wang Chen)

</soc_peripheral_irq(112)></dt-bindings></wangchen20@iscas.ac.cn></emil.renner.berthing@canonical.com></inochiama@outlook.com></xiaoguang.xing@sophgo.com></xiaoguang.xing@sophgo.com></inochiama@outlook.com></wangchen20@iscas.ac.cn></unicornxw@gmail.com></emil.renner.berthing@canonical.com>