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[90.5.10.86]) by smtp.gmail.com with ESMTPSA id s17-20020a1cf211000000b003fe2a40d287sm2125515wmc.1.2023.09.21.07.44.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 07:44:28 -0700 (PDT) From: David Lechner To: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-staging@lists.linux.dev Cc: linux-kernel@vger.kernel.org, Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Hennerich , =?UTF-8?q?Nuno=20S=C3=A1?= , Axel Haslam , Philip Molloy , David Lechner Subject: [PATCH v2 18/19] staging: iio: resolver: ad2s1210: add phase_lock_range attributes Date: Thu, 21 Sep 2023 09:43:59 -0500 Message-Id: <20230921144400.62380-19-dlechner@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921144400.62380-1-dlechner@baylibre.com> References: <20230921144400.62380-1-dlechner@baylibre.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net This adds new phase_lock_range and phase_lock_range_available attributes to the ad2s1210 resolver driver. These attributes allow the user to set the phase lock range bit in the control register to modify the behavior of the resolver to digital converter. Signed-off-by: David Lechner --- drivers/staging/iio/resolver/ad2s1210.c | 58 +++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/staging/iio/resolver/ad2s1210.c b/drivers/staging/iio/resolver/ad2s1210.c index 71f0913b7e2e..f5b8b290e860 100644 --- a/drivers/staging/iio/resolver/ad2s1210.c +++ b/drivers/staging/iio/resolver/ad2s1210.c @@ -259,6 +259,60 @@ static ssize_t excitation_frequency_store(struct device *dev, return ret; } +static ssize_t phase_lock_range_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); + int ret; + + mutex_lock(&st->lock); + ret = regmap_test_bits(st->regmap, AD2S1210_REG_CONTROL, + AD2S1210_PHASE_LOCK_RANGE_44); + if (ret < 0) + goto error_ret; + + ret = sprintf(buf, "%d\n", ret ? 44 : 360); + +error_ret: + mutex_unlock(&st->lock); + return ret; +} + +static ssize_t phase_lock_range_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev)); + u16 udata; + int ret; + + ret = kstrtou16(buf, 10, &udata); + if (ret < 0 || (udata != 44 && udata != 360)) + return -EINVAL; + + mutex_lock(&st->lock); + + ret = regmap_update_bits(st->regmap, AD2S1210_REG_CONTROL, + AD2S1210_PHASE_LOCK_RANGE_44, + udata == 44 ? AD2S1210_PHASE_LOCK_RANGE_44 : 0); + if (ret < 0) + goto error_ret; + + ret = len; + +error_ret: + mutex_unlock(&st->lock); + return ret; +} + +static ssize_t phase_lock_range_available_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "44 360\n"); +} + /* read the fault register since last sample */ static ssize_t ad2s1210_show_fault(struct device *dev, struct device_attribute *attr, char *buf) @@ -506,6 +560,8 @@ static int ad2s1210_write_raw(struct iio_dev *indio_dev, } static IIO_DEVICE_ATTR_RW(excitation_frequency, 0); +static IIO_DEVICE_ATTR_RW(phase_lock_range, 0); +static IIO_DEVICE_ATTR_RO(phase_lock_range_available, 0); static IIO_DEVICE_ATTR(fault, 0644, ad2s1210_show_fault, ad2s1210_clear_fault, 0); @@ -552,6 +608,8 @@ static const struct iio_chan_spec ad2s1210_channels[] = { static struct attribute *ad2s1210_attributes[] = { &iio_dev_attr_excitation_frequency.dev_attr.attr, + &iio_dev_attr_phase_lock_range.dev_attr.attr, + &iio_dev_attr_phase_lock_range_available.dev_attr.attr, &iio_dev_attr_fault.dev_attr.attr, &iio_dev_attr_los_thrd.dev_attr.attr, &iio_dev_attr_dos_ovr_thrd.dev_attr.attr, -- 2.34.1