From: Andrew Jones <ajones@ventanamicro.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Conor Dooley <conor@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Shuah Khan <shuah@kernel.org>,
Mayuresh Chitale <mchitale@ventanamicro.com>,
devicetree@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v2 1/9] dt-bindings: riscv: Add XVentanaCondOps extension entry
Date: Mon, 25 Sep 2023 16:11:39 +0200 [thread overview]
Message-ID: <20230925-e2aee59a5ea91fa14fab12ed@orel> (raw)
In-Reply-To: <20230925133859.1735879-2-apatel@ventanamicro.com>
On Mon, Sep 25, 2023 at 07:08:51PM +0530, Anup Patel wrote:
> Add an entry for the XVentanaCondOps extension to the
> riscv,isa-extensions property.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 36ff6749fbba..cad8ef68eca7 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -171,6 +171,13 @@ properties:
> memory types as ratified in the 20191213 version of the privileged
> ISA specification.
>
> + - const: xventanacondops
> + description: |
> + The Ventana specific XVentanaCondOps extension for conditional
> + arithmetic and conditional-select/move operations defined by the
> + Ventana custom extensions specification v1.0.1 (or higher) at
> + https://github.com/ventanamicro/ventana-custom-extensions/releases.
> +
> - const: zba
> description: |
> The standard Zba bit-manipulation extension for address generation
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-09-25 14:11 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-25 13:38 [PATCH v2 0/9] KVM RISC-V Conditional Operations Anup Patel
2023-09-25 13:38 ` [PATCH v2 1/9] dt-bindings: riscv: Add XVentanaCondOps extension entry Anup Patel
2023-09-25 14:11 ` Andrew Jones [this message]
2023-09-25 13:38 ` [PATCH v2 2/9] RISC-V: Detect XVentanaCondOps from ISA string Anup Patel
2023-09-25 17:48 ` Charlie Jenkins
2023-09-25 18:12 ` Charlie Jenkins
2023-09-26 4:08 ` Anup Patel
2023-09-26 4:14 ` Anup Patel
2023-09-27 2:13 ` Charlie Jenkins
2023-09-25 13:38 ` [PATCH v2 3/9] dt-bindings: riscv: Add Zicond extension entry Anup Patel
2023-09-25 14:12 ` Andrew Jones
2023-09-25 13:38 ` [PATCH v2 4/9] RISC-V: Detect Zicond from ISA string Anup Patel
2023-09-25 14:13 ` Andrew Jones
2023-09-25 13:38 ` [PATCH v2 5/9] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM Anup Patel
2023-09-25 13:38 ` [PATCH v2 6/9] RISC-V: KVM: Allow Zicond " Anup Patel
2023-09-25 13:38 ` [PATCH v2 7/9] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Anup Patel
2023-09-25 13:38 ` [PATCH v2 8/9] KVM: riscv: selftests: Add smstateen registers " Anup Patel
2023-09-25 13:38 ` [PATCH v2 9/9] KVM: riscv: selftests: Add condops extensions " Anup Patel
2023-09-25 14:16 ` Andrew Jones
2023-09-25 15:33 ` [PATCH v2 0/9] KVM RISC-V Conditional Operations Conor Dooley
2023-09-25 15:36 ` Conor Dooley
2023-09-27 14:24 ` Anup Patel
2023-09-27 14:45 ` Conor Dooley
2023-09-27 15:01 ` Palmer Dabbelt
2023-09-27 15:26 ` Anup Patel
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