* [RESEND PATCH 2/3] ARM: dts: qcom: sdx65: add missing GCC clocks
2023-09-24 18:31 [RESEND PATCH 1/3] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Krzysztof Kozlowski
@ 2023-09-24 18:31 ` Krzysztof Kozlowski
2023-09-24 22:19 ` Dmitry Baryshkov
2023-09-24 18:31 ` [RESEND PATCH 3/3] ARM: dts: qcom: sdx65: correct SPMI node name Krzysztof Kozlowski
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-24 18:31 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Rohit Agarwal,
Manivannan Sadhasivam, linux-arm-msm, devicetree, linux-kernel
Cc: Krzysztof Kozlowski
The SDX65 GCC clock controller expects two required clocks:
pcie_pipe_clk and usb3_phy_wrapper_gcc_usb30_pipe_clk. The first one is
provided by existing phy node, but second is not yet implemented.
qcom-sdx65-mtp.dtb: clock-controller@100000: clocks: [[11, 0], [11, 1], [12]] is too short
qcom-sdx65-mtp.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk'] is too short
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index c9790217320b..4a8cc28fa1db 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -204,8 +204,16 @@ soc: soc {
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sdx65";
reg = <0x00100000 0x001f7400>;
- clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
- clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&pcie_phy>,
+ <0>;
+ clock-names = "bi_tcxo",
+ "bi_tcxo_ao",
+ "sleep_clk",
+ "pcie_pipe_clk",
+ "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#power-domain-cells = <1>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [RESEND PATCH 2/3] ARM: dts: qcom: sdx65: add missing GCC clocks
2023-09-24 18:31 ` [RESEND PATCH 2/3] ARM: dts: qcom: sdx65: add missing GCC clocks Krzysztof Kozlowski
@ 2023-09-24 22:19 ` Dmitry Baryshkov
0 siblings, 0 replies; 8+ messages in thread
From: Dmitry Baryshkov @ 2023-09-24 22:19 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Rohit Agarwal,
Manivannan Sadhasivam, linux-arm-msm, devicetree, linux-kernel
On Sun, 24 Sept 2023 at 21:31, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> The SDX65 GCC clock controller expects two required clocks:
> pcie_pipe_clk and usb3_phy_wrapper_gcc_usb30_pipe_clk. The first one is
> provided by existing phy node, but second is not yet implemented.
>
> qcom-sdx65-mtp.dtb: clock-controller@100000: clocks: [[11, 0], [11, 1], [12]] is too short
> qcom-sdx65-mtp.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk'] is too short
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> index c9790217320b..4a8cc28fa1db 100644
> --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> @@ -204,8 +204,16 @@ soc: soc {
> gcc: clock-controller@100000 {
> compatible = "qcom,gcc-sdx65";
> reg = <0x00100000 0x001f7400>;
> - clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
> - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&rpmhcc RPMH_CXO_CLK_A>,
> + <&sleep_clk>,
> + <&pcie_phy>,
> + <0>;
Maybe <&usb_ssphy> or <&usb_qmpphy>?
> + clock-names = "bi_tcxo",
> + "bi_tcxo_ao",
> + "sleep_clk",
> + "pcie_pipe_clk",
> + "usb3_phy_wrapper_gcc_usb30_pipe_clk";
> #power-domain-cells = <1>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 8+ messages in thread
* [RESEND PATCH 3/3] ARM: dts: qcom: sdx65: correct SPMI node name
2023-09-24 18:31 [RESEND PATCH 1/3] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Krzysztof Kozlowski
2023-09-24 18:31 ` [RESEND PATCH 2/3] ARM: dts: qcom: sdx65: add missing GCC clocks Krzysztof Kozlowski
@ 2023-09-24 18:31 ` Krzysztof Kozlowski
2023-09-24 22:51 ` Dmitry Baryshkov
2023-09-24 22:17 ` [RESEND PATCH 1/3] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Dmitry Baryshkov
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-24 18:31 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Rohit Agarwal,
Manivannan Sadhasivam, linux-arm-msm, devicetree, linux-kernel
Cc: Krzysztof Kozlowski
Node names should not have vendor prefixes:
qcom-sdx65-mtp.dtb: qcom,spmi@c440000: $nodename:0: 'qcom,spmi@c440000' does not match '^spmi@.*
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index 4a8cc28fa1db..49c16ee2e169 100644
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -537,7 +537,7 @@ restart@c264000 {
reg = <0x0c264000 0x1000>;
};
- spmi_bus: qcom,spmi@c440000 {
+ spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0xd00>,
<0xc600000 0x2000000>,
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [RESEND PATCH 3/3] ARM: dts: qcom: sdx65: correct SPMI node name
2023-09-24 18:31 ` [RESEND PATCH 3/3] ARM: dts: qcom: sdx65: correct SPMI node name Krzysztof Kozlowski
@ 2023-09-24 22:51 ` Dmitry Baryshkov
0 siblings, 0 replies; 8+ messages in thread
From: Dmitry Baryshkov @ 2023-09-24 22:51 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Rohit Agarwal,
Manivannan Sadhasivam, linux-arm-msm, devicetree, linux-kernel
On Sun, 24 Sept 2023 at 21:31, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> Node names should not have vendor prefixes:
>
> qcom-sdx65-mtp.dtb: qcom,spmi@c440000: $nodename:0: 'qcom,spmi@c440000' does not match '^spmi@.*
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RESEND PATCH 1/3] ARM: dts: qcom: sdx65: correct PCIe EP phy-names
2023-09-24 18:31 [RESEND PATCH 1/3] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Krzysztof Kozlowski
2023-09-24 18:31 ` [RESEND PATCH 2/3] ARM: dts: qcom: sdx65: add missing GCC clocks Krzysztof Kozlowski
2023-09-24 18:31 ` [RESEND PATCH 3/3] ARM: dts: qcom: sdx65: correct SPMI node name Krzysztof Kozlowski
@ 2023-09-24 22:17 ` Dmitry Baryshkov
2023-09-26 10:42 ` Manivannan Sadhasivam
2023-12-03 4:54 ` (subset) " Bjorn Andersson
4 siblings, 0 replies; 8+ messages in thread
From: Dmitry Baryshkov @ 2023-09-24 22:17 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Rohit Agarwal,
Manivannan Sadhasivam, linux-arm-msm, devicetree, linux-kernel
On Sun, 24 Sept 2023 at 21:31, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> Qualcomm PCIe endpoint bindings expect phy-names to be "pciephy":
>
> arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dtb: pcie-ep@1c00000: phy-names:0: 'pciephy' was expected
>
> Fixes: 9c0bb38414a4 ("ARM: dts: qcom: sdx65: Add support for PCIe EP")
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [RESEND PATCH 1/3] ARM: dts: qcom: sdx65: correct PCIe EP phy-names
2023-09-24 18:31 [RESEND PATCH 1/3] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Krzysztof Kozlowski
` (2 preceding siblings ...)
2023-09-24 22:17 ` [RESEND PATCH 1/3] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Dmitry Baryshkov
@ 2023-09-26 10:42 ` Manivannan Sadhasivam
2023-12-03 4:54 ` (subset) " Bjorn Andersson
4 siblings, 0 replies; 8+ messages in thread
From: Manivannan Sadhasivam @ 2023-09-26 10:42 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Rohit Agarwal,
Manivannan Sadhasivam, linux-arm-msm, devicetree, linux-kernel
On Sun, Sep 24, 2023 at 08:31:01PM +0200, Krzysztof Kozlowski wrote:
> Qualcomm PCIe endpoint bindings expect phy-names to be "pciephy":
>
> arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dtb: pcie-ep@1c00000: phy-names:0: 'pciephy' was expected
>
> Fixes: 9c0bb38414a4 ("ARM: dts: qcom: sdx65: Add support for PCIe EP")
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> ---
> arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> index dd711484dfc9..c9790217320b 100644
> --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
> @@ -337,7 +337,7 @@ pcie_ep: pcie-ep@1c00000 {
> power-domains = <&gcc PCIE_GDSC>;
>
> phys = <&pcie_phy>;
> - phy-names = "pcie-phy";
> + phy-names = "pciephy";
>
> max-link-speed = <3>;
> num-lanes = <2>;
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: (subset) [RESEND PATCH 1/3] ARM: dts: qcom: sdx65: correct PCIe EP phy-names
2023-09-24 18:31 [RESEND PATCH 1/3] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Krzysztof Kozlowski
` (3 preceding siblings ...)
2023-09-26 10:42 ` Manivannan Sadhasivam
@ 2023-12-03 4:54 ` Bjorn Andersson
4 siblings, 0 replies; 8+ messages in thread
From: Bjorn Andersson @ 2023-12-03 4:54 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rohit Agarwal, Manivannan Sadhasivam, linux-arm-msm,
devicetree, linux-kernel, Krzysztof Kozlowski
On Sun, 24 Sep 2023 20:31:01 +0200, Krzysztof Kozlowski wrote:
> Qualcomm PCIe endpoint bindings expect phy-names to be "pciephy":
>
> arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dtb: pcie-ep@1c00000: phy-names:0: 'pciephy' was expected
>
>
Applied, thanks!
[1/3] ARM: dts: qcom: sdx65: correct PCIe EP phy-names
commit: 94da379dba88c4cdd562bad21c9ba5656e5ed5df
[2/3] ARM: dts: qcom: sdx65: add missing GCC clocks
commit: f64f653df2ef713359178c731bc8f89ff54014b1
[3/3] ARM: dts: qcom: sdx65: correct SPMI node name
commit: a900ad783f507cb396e402827052e70c0c565ae9
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread