From: Conor Dooley <conor@kernel.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Shuah Khan <shuah@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
Mayuresh Chitale <mchitale@ventanamicro.com>,
devicetree@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v2 0/9] KVM RISC-V Conditional Operations
Date: Wed, 27 Sep 2023 15:45:28 +0100 [thread overview]
Message-ID: <20230927-snowcap-stadium-2f6aeffac59e@spud> (raw)
In-Reply-To: <CAK9=C2UBgNWFTdQKt29+bNnWDgHZGd5fU+oP1bqsarkqc5+jgg@mail.gmail.com>
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On Wed, Sep 27, 2023 at 07:54:49PM +0530, Anup Patel wrote:
> On Mon, Sep 25, 2023 at 9:07 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Mon, Sep 25, 2023 at 04:33:15PM +0100, Conor Dooley wrote:
> > > On Mon, Sep 25, 2023 at 07:08:50PM +0530, Anup Patel wrote:
> > > > This series extends KVM RISC-V to allow Guest/VM discover and use
> > > > conditional operations related ISA extensions (namely XVentanaCondOps
> > > > and Zicond).
> > > >
> > > > To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
> > > > branch at: https://github.com/avpatel/kvmtool.git
> > > >
> > > > These patches are based upon the latest riscv_kvm_queue and can also be
> > > > found in the riscv_kvm_condops_v2 branch at:
> > > > https://github.com/avpatel/linux.git
> > > >
> > > > Changes since v1:
> > > > - Rebased the series on riscv_kvm_queue
> > > > - Split PATCH1 and PATCH2 of v1 series into two patches
> > > > - Added separate test configs for XVentanaCondOps and Zicond in PATCH7
> > > > of v1 series.
> > > >
> > > > Anup Patel (9):
> > > > dt-bindings: riscv: Add XVentanaCondOps extension entry
> > > > RISC-V: Detect XVentanaCondOps from ISA string
> > > > dt-bindings: riscv: Add Zicond extension entry
> > > > RISC-V: Detect Zicond from ISA string
> > >
> > > For these 4:
> > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> >
> > Actually, now that I think of it, I'm going to temporarily un-review this.
> > From patch-acceptance.rst:
> > | Additionally, the RISC-V specification allows implementers to create
> > | their own custom extensions. These custom extensions aren't required
> > | to go through any review or ratification process by the RISC-V
> > | Foundation. To avoid the maintenance complexity and potential
> > | performance impact of adding kernel code for implementor-specific
> > | RISC-V extensions, we'll only consider patches for extensions that either:
> > |
> > | - Have been officially frozen or ratified by the RISC-V Foundation, or
> > | - Have been implemented in hardware that is widely available, per standard
> > | Linux practice.
> >
> > The xventanacondops bits don't qualify under the first entry, and I
> > don't think they qualify under the second yet. Am I wrong?
>
> The Ventana Veyron V1 was announced in Dec 2022 at RISC-V summit
> followed by press releases:
> https://www.ventanamicro.com/ventana-introduces-veyron-worlds-first-data-center-class-risc-v-cpu-product-family/
> https://www.embedded.com/ventana-reveals-risc-v-cpu-compute-chiplet-for-data-center/
> https://www.prnewswire.com/news-releases/ventana-introduces-veyron-worlds-first-data-center-class-risc-v-cpu-product-family-301700985.html
>
> @Palmer if the above looks good to you then please ack PATCH1-to-4
These are announcements AFAICT & not an indication of "being implemented
in hardware that is widely available".
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next prev parent reply other threads:[~2023-09-27 14:45 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-25 13:38 [PATCH v2 0/9] KVM RISC-V Conditional Operations Anup Patel
2023-09-25 13:38 ` [PATCH v2 1/9] dt-bindings: riscv: Add XVentanaCondOps extension entry Anup Patel
2023-09-25 14:11 ` Andrew Jones
2023-09-25 13:38 ` [PATCH v2 2/9] RISC-V: Detect XVentanaCondOps from ISA string Anup Patel
2023-09-25 17:48 ` Charlie Jenkins
2023-09-25 18:12 ` Charlie Jenkins
2023-09-26 4:08 ` Anup Patel
2023-09-26 4:14 ` Anup Patel
2023-09-27 2:13 ` Charlie Jenkins
2023-09-25 13:38 ` [PATCH v2 3/9] dt-bindings: riscv: Add Zicond extension entry Anup Patel
2023-09-25 14:12 ` Andrew Jones
2023-09-25 13:38 ` [PATCH v2 4/9] RISC-V: Detect Zicond from ISA string Anup Patel
2023-09-25 14:13 ` Andrew Jones
2023-09-25 13:38 ` [PATCH v2 5/9] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM Anup Patel
2023-09-25 13:38 ` [PATCH v2 6/9] RISC-V: KVM: Allow Zicond " Anup Patel
2023-09-25 13:38 ` [PATCH v2 7/9] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Anup Patel
2023-09-25 13:38 ` [PATCH v2 8/9] KVM: riscv: selftests: Add smstateen registers " Anup Patel
2023-09-25 13:38 ` [PATCH v2 9/9] KVM: riscv: selftests: Add condops extensions " Anup Patel
2023-09-25 14:16 ` Andrew Jones
2023-09-25 15:33 ` [PATCH v2 0/9] KVM RISC-V Conditional Operations Conor Dooley
2023-09-25 15:36 ` Conor Dooley
2023-09-27 14:24 ` Anup Patel
2023-09-27 14:45 ` Conor Dooley [this message]
2023-09-27 15:01 ` Palmer Dabbelt
2023-09-27 15:26 ` Anup Patel
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