From: Manivannan Sadhasivam <mani@kernel.org>
To: Nitin Rawat <quic_nitirawa@quicinc.com>
Cc: agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, mani@kernel.org,
alim.akhtar@samsung.com, bvanassche@acm.org, avri.altman@wdc.com,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, cros-qcom-dts-watchers@chromium.org,
linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH V3 2/4] arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 soc
Date: Wed, 27 Sep 2023 14:41:49 +0200 [thread overview]
Message-ID: <20230927124149.GB18050@thinkpad> (raw)
In-Reply-To: <20230927081858.15961-3-quic_nitirawa@quicinc.com>
On Wed, Sep 27, 2023 at 01:48:56PM +0530, Nitin Rawat wrote:
> Add UFS host controller and PHY nodes for sc7280 soc.
>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 63 ++++++++++++++++++++++++++++
> 1 file changed, 63 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 66f1eb83cca7..0b50b8557311 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -3353,6 +3353,69 @@
> };
> };
>
> + ufs_mem_hc: ufs@1d84000 {
> + compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
> + "jedec,ufs-2.0";
> + reg = <0x0 0x01d84000 0x0 0x3000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&ufs_mem_phy>;
> + phy-names = "ufsphy";
> + lanes-per-direction = <2>;
> + #reset-cells = <1>;
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> +
> + power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> + required-opps = <&rpmhpd_opp_nom>;
> +
> + iommus = <&apps_smmu 0x80 0x0>;
> + dma-coherent;
> +
> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + clock-names = "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk",
> + "rx_lane1_sync_clk";
Please add the interconnect properties since mainline has the support.
- Mani
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2023-09-27 12:41 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-27 8:18 [PATCH V3 0/4] Add UFS host controller and Phy nodes for sc7280 Nitin Rawat
2023-09-27 8:18 ` [PATCH V3 1/4] scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string Nitin Rawat
2023-09-27 8:18 ` [PATCH V3 2/4] arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 soc Nitin Rawat
2023-09-27 11:40 ` Konrad Dybcio
2023-09-27 12:41 ` Manivannan Sadhasivam [this message]
2023-09-29 9:01 ` Luca Weiss
2023-09-27 8:18 ` [PATCH V3 3/4] arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 IDP board Nitin Rawat
2023-09-27 9:25 ` Konrad Dybcio
2023-09-27 10:08 ` Nitin Rawat
2023-09-27 12:43 ` Manivannan Sadhasivam
2023-09-27 8:18 ` [PATCH V3 4/4] dt-bindings: ufs: qcom: Align clk binding property for Qualcomm UFS Nitin Rawat
2023-09-27 8:29 ` Nitin Rawat
2023-09-27 9:27 ` Konrad Dybcio
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