* [PATCH v4 1/4] cpufreq: qcom-nvmem: add support for IPQ8074
@ 2023-09-28 21:04 Robert Marko
2023-09-28 21:04 ` [PATCH v4 2/4] dt-bindings: opp: opp-v2-kryo-cpu: Document named opp-microvolt property Robert Marko
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Robert Marko @ 2023-09-28 21:04 UTC (permalink / raw)
To: ilia.lin, vireshk, nm, sboyd, robh+dt, krzysztof.kozlowski+dt,
conor+dt, agross, andersson, konrad.dybcio, rafael, linux-pm,
devicetree, linux-kernel, linux-arm-msm
Cc: Robert Marko
IPQ8074 comes in 2 families:
* IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
* IPQ8172/IPQ8173/IPQ8174 (Oak) up to 1.4GHz
* IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
So, in order to be able to share one OPP table lets add support for IPQ8074
family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
will get created by NVMEM CPUFreq driver.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
Changes in v4:
* Add support for IPQ8174 (Oak) family
Changes in v3:
* Use enum for SoC versions
Changes in v2:
* Print an error if SMEM ID is not part of the IPQ8074 family
and restrict the speed to Acorn variant (1.4GHz)
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 48 ++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 02ec58a8603b..cc3ccc1519c3 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -179,6 +179,7 @@ static const struct of_device_id blocklist[] __initconst = {
{ .compatible = "ti,am62a7", },
{ .compatible = "qcom,ipq8064", },
+ { .compatible = "qcom,ipq8074", },
{ .compatible = "qcom,apq8064", },
{ .compatible = "qcom,msm8974", },
{ .compatible = "qcom,msm8960", },
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 84d7033e5efe..3fa12648ceb6 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -30,6 +30,11 @@
#include <dt-bindings/arm/qcom,ids.h>
+enum ipq8074_versions {
+ IPQ8074_HAWKEYE_VERSION = 0,
+ IPQ8074_ACORN_VERSION,
+};
+
struct qcom_cpufreq_drv;
struct qcom_cpufreq_match_data {
@@ -203,6 +208,44 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
return ret;
}
+static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
+ struct nvmem_cell *speedbin_nvmem,
+ char **pvs_name,
+ struct qcom_cpufreq_drv *drv)
+{
+ u32 msm_id;
+ int ret;
+ *pvs_name = NULL;
+
+ ret = qcom_smem_get_soc_id(&msm_id);
+ if (ret)
+ return ret;
+
+ switch (msm_id) {
+ case QCOM_ID_IPQ8070A:
+ case QCOM_ID_IPQ8071A:
+ case QCOM_ID_IPQ8172:
+ case QCOM_ID_IPQ8173:
+ case QCOM_ID_IPQ8174:
+ drv->versions = BIT(IPQ8074_ACORN_VERSION);
+ break;
+ case QCOM_ID_IPQ8072A:
+ case QCOM_ID_IPQ8074A:
+ case QCOM_ID_IPQ8076A:
+ case QCOM_ID_IPQ8078A:
+ drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
+ break;
+ default:
+ dev_err(cpu_dev,
+ "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
+ msm_id);
+ drv->versions = BIT(IPQ8074_ACORN_VERSION);
+ break;
+ }
+
+ return 0;
+}
+
static const struct qcom_cpufreq_match_data match_data_kryo = {
.get_version = qcom_cpufreq_kryo_name_version,
};
@@ -217,6 +260,10 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = {
.genpd_names = qcs404_genpd_names,
};
+static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
+ .get_version = qcom_cpufreq_ipq8074_name_version,
+};
+
static int qcom_cpufreq_probe(struct platform_device *pdev)
{
struct qcom_cpufreq_drv *drv;
@@ -360,6 +407,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
+ { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
{ .compatible = "qcom,apq8064", .data = &match_data_krait },
{ .compatible = "qcom,msm8974", .data = &match_data_krait },
{ .compatible = "qcom,msm8960", .data = &match_data_krait },
--
2.41.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v4 2/4] dt-bindings: opp: opp-v2-kryo-cpu: Document named opp-microvolt property
2023-09-28 21:04 [PATCH v4 1/4] cpufreq: qcom-nvmem: add support for IPQ8074 Robert Marko
@ 2023-09-28 21:04 ` Robert Marko
2023-09-28 22:49 ` Rob Herring
2023-09-28 21:04 ` [PATCH v4 3/4] cpufreq: qcom-nvmem: add support for IPQ8064 Robert Marko
2023-09-28 21:04 ` [PATCH v4 4/4] ARM: dts: qcom: ipq8064: Add CPU OPP table Robert Marko
2 siblings, 1 reply; 7+ messages in thread
From: Robert Marko @ 2023-09-28 21:04 UTC (permalink / raw)
To: ilia.lin, vireshk, nm, sboyd, robh+dt, krzysztof.kozlowski+dt,
conor+dt, agross, andersson, konrad.dybcio, rafael, linux-pm,
devicetree, linux-kernel, linux-arm-msm
Cc: Christian Marangi, Robert Marko
From: Christian Marangi <ansuelsmth@gmail.com>
Document named opp-microvolt property for opp-v2-kryo-cpu schema.
This property is used to declare multiple voltage ranges selected on the
different values read from efuses. The selection is done based on the
speed pvs values and the named opp-microvolt property is selected by the
qcom-cpufreq-nvmem driver.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
Changes in v4:
* Describe PVS
* Add description for opp-microvolt entries
---
.../bindings/opp/opp-v2-kryo-cpu.yaml | 38 +++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
index bbbad31ae4ca..f1b4553fd66a 100644
--- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
+++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
@@ -63,6 +63,12 @@ patternProperties:
5: MSM8996SG, speedbin 1
6: MSM8996SG, speedbin 2
7-31: unused
+
+ Bitmap for IPQ806X SoC:
+ 0: IPQ8062
+ 1: IPQ8064/IPQ8066/IPQ8068
+ 2: IPQ8065/IPQ8069
+ 3-31: unused
enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
0x9, 0xd, 0xe, 0xf,
0x10, 0x20, 0x30, 0x70]
@@ -71,6 +77,22 @@ patternProperties:
required-opps: true
+ patternProperties:
+ '^opp-microvolt-speed[0-9]+-pvs[0-9]+$':
+ description: |
+ Named opp-microvolt property following the same generic
+ binding for named opp-microvolt.
+
+ The correct voltage range is selected based on the values
+ in the efuse for the speed and the pvs (power variable
+ scaling).
+ minItems: 1
+ maxItems: 4 # Up to 4 regulators: Core, Mem, Dig and HFPLL
+ items:
+ - description: nominal voltage
+ - description: minimum voltage
+ - description: maximum voltage
+
required:
- opp-hz
@@ -256,6 +278,22 @@ examples:
};
};
+ /* Dummy opp table to give example for named opp-microvolt */
+ opp-table-2 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs2 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs3 = <800000 760000 840000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <100000>;
+ };
+ };
+
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
--
2.41.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v4 2/4] dt-bindings: opp: opp-v2-kryo-cpu: Document named opp-microvolt property
2023-09-28 21:04 ` [PATCH v4 2/4] dt-bindings: opp: opp-v2-kryo-cpu: Document named opp-microvolt property Robert Marko
@ 2023-09-28 22:49 ` Rob Herring
0 siblings, 0 replies; 7+ messages in thread
From: Rob Herring @ 2023-09-28 22:49 UTC (permalink / raw)
To: Robert Marko
Cc: robh+dt, nm, rafael, vireshk, andersson, krzysztof.kozlowski+dt,
devicetree, conor+dt, Christian Marangi, konrad.dybcio, ilia.lin,
sboyd, linux-pm, linux-kernel, agross, linux-arm-msm
On Thu, 28 Sep 2023 23:04:05 +0200, Robert Marko wrote:
> From: Christian Marangi <ansuelsmth@gmail.com>
>
> Document named opp-microvolt property for opp-v2-kryo-cpu schema.
> This property is used to declare multiple voltage ranges selected on the
> different values read from efuses. The selection is done based on the
> speed pvs values and the named opp-microvolt property is selected by the
> qcom-cpufreq-nvmem driver.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> Signed-off-by: Robert Marko <robimarko@gmail.com>
> ---
> Changes in v4:
> * Describe PVS
> * Add description for opp-microvolt entries
> ---
> .../bindings/opp/opp-v2-kryo-cpu.yaml | 38 +++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml: patternProperties:^opp-?[0-9]+$:patternProperties:^opp-microvolt-speed[0-9]+-pvs[0-9]+$: {'description': 'Named opp-microvolt property following the same generic\nbinding for named opp-microvolt.\n\nThe correct voltage range is selected based on the values\nin the efuse for the speed and the pvs (power variable\nscaling).\n', 'minItems': 1, 'maxItems': 4, 'items': [{'description': 'nominal voltage'}, {'description': 'minimum voltage'}, {'description': 'maximum voltage'}]} should not be valid under {'required': ['maxItems']}
hint: "maxItems" is not needed with an "items" list
from schema $id: http://devicetree.org/meta-schemas/items.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230928210525.1265958-2-robimarko@gmail.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v4 3/4] cpufreq: qcom-nvmem: add support for IPQ8064
2023-09-28 21:04 [PATCH v4 1/4] cpufreq: qcom-nvmem: add support for IPQ8074 Robert Marko
2023-09-28 21:04 ` [PATCH v4 2/4] dt-bindings: opp: opp-v2-kryo-cpu: Document named opp-microvolt property Robert Marko
@ 2023-09-28 21:04 ` Robert Marko
2023-09-28 21:04 ` [PATCH v4 4/4] ARM: dts: qcom: ipq8064: Add CPU OPP table Robert Marko
2 siblings, 0 replies; 7+ messages in thread
From: Robert Marko @ 2023-09-28 21:04 UTC (permalink / raw)
To: ilia.lin, vireshk, nm, sboyd, robh+dt, krzysztof.kozlowski+dt,
conor+dt, agross, andersson, konrad.dybcio, rafael, linux-pm,
devicetree, linux-kernel, linux-arm-msm
Cc: Christian Marangi, Robert Marko
From: Christian Marangi <ansuelsmth@gmail.com>
IPQ8064 comes in 3 families:
* IPQ8062 up to 1.0GHz
* IPQ8064/IPQ8066/IPQ8068 up to 1.4GHz
* IPQ8065/IPQ8069 up to 1.7Ghz
So, in order to be able to support one OPP table, add support for
IPQ8064 family based of SMEM SoC ID-s and correctly set the version so
opp-supported-hw can be correctly used.
Bit are set with the following logic:
* IPQ8062 BIT 0
* IPQ8064/IPQ8066/IPQ8068 BIT 1
* IPQ8065/IPQ8069 BIT 2
speed is never fused, only pvs values are fused.
IPQ806x SoC doesn't have pvs_version so we drop and we use the new
pattern:
opp-microvolt-speed0-pvs<PSV_VALUE>
Example:
- for ipq8062 psv2
opp-microvolt-speed0-pvs2 = < 925000 878750 971250>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
Changes in v4:
* Free speedbin in case of an error
Changes in v3:
* Use enum for SoC version
* Dont evaluate speed as its not fused, only pvs
Changes in v2:
* Include IPQ8064 support
---
drivers/cpufreq/qcom-cpufreq-nvmem.c | 68 +++++++++++++++++++++++++++-
1 file changed, 67 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 3fa12648ceb6..8ca0e7ebd184 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -35,6 +35,12 @@ enum ipq8074_versions {
IPQ8074_ACORN_VERSION,
};
+enum ipq806x_versions {
+ IPQ8062_VERSION = 0,
+ IPQ8064_VERSION,
+ IPQ8065_VERSION,
+};
+
struct qcom_cpufreq_drv;
struct qcom_cpufreq_match_data {
@@ -208,6 +214,62 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
return ret;
}
+static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev,
+ struct nvmem_cell *speedbin_nvmem,
+ char **pvs_name,
+ struct qcom_cpufreq_drv *drv)
+{
+ int speed = 0, pvs = 0, pvs_ver = 0;
+ int msm_id, ret = 0;
+ u8 *speedbin;
+ size_t len;
+
+ speedbin = nvmem_cell_read(speedbin_nvmem, &len);
+
+ if (IS_ERR(speedbin))
+ return PTR_ERR(speedbin);
+
+ if (len != 4) {
+ dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
+ kfree(speedbin);
+ return -ENODEV;
+ }
+
+ get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver, speedbin);
+
+ ret = qcom_smem_get_soc_id(&msm_id);
+ if (ret)
+ return ret;
+
+ switch (msm_id) {
+ case QCOM_ID_IPQ8062:
+ drv->versions = BIT(IPQ8062_VERSION);
+ break;
+ case QCOM_ID_IPQ8064:
+ case QCOM_ID_IPQ8066:
+ case QCOM_ID_IPQ8068:
+ drv->versions = BIT(IPQ8064_VERSION);
+ break;
+ case QCOM_ID_IPQ8065:
+ case QCOM_ID_IPQ8069:
+ drv->versions = BIT(IPQ8065_VERSION);
+ break;
+ default:
+ dev_err(cpu_dev,
+ "SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n",
+ msm_id);
+ drv->versions = BIT(IPQ8062_VERSION);
+ break;
+ }
+
+ /* IPQ8064 speed is never fused. Only pvs values are fused. */
+ snprintf(*pvs_name, sizeof("speedXX-pvsXX"), "speed%d-pvs%d",
+ speed, pvs);
+
+ kfree(speedbin);
+ return ret;
+}
+
static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
struct nvmem_cell *speedbin_nvmem,
char **pvs_name,
@@ -260,6 +322,10 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = {
.genpd_names = qcs404_genpd_names,
};
+static const struct qcom_cpufreq_match_data match_data_ipq8064 = {
+ .get_version = qcom_cpufreq_ipq8064_name_version,
+};
+
static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
.get_version = qcom_cpufreq_ipq8074_name_version,
};
@@ -406,7 +472,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
- { .compatible = "qcom,ipq8064", .data = &match_data_krait },
+ { .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
{ .compatible = "qcom,apq8064", .data = &match_data_krait },
{ .compatible = "qcom,msm8974", .data = &match_data_krait },
--
2.41.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v4 4/4] ARM: dts: qcom: ipq8064: Add CPU OPP table
2023-09-28 21:04 [PATCH v4 1/4] cpufreq: qcom-nvmem: add support for IPQ8074 Robert Marko
2023-09-28 21:04 ` [PATCH v4 2/4] dt-bindings: opp: opp-v2-kryo-cpu: Document named opp-microvolt property Robert Marko
2023-09-28 21:04 ` [PATCH v4 3/4] cpufreq: qcom-nvmem: add support for IPQ8064 Robert Marko
@ 2023-09-28 21:04 ` Robert Marko
2023-09-29 13:57 ` Konrad Dybcio
2 siblings, 1 reply; 7+ messages in thread
From: Robert Marko @ 2023-09-28 21:04 UTC (permalink / raw)
To: ilia.lin, vireshk, nm, sboyd, robh+dt, krzysztof.kozlowski+dt,
conor+dt, agross, andersson, konrad.dybcio, rafael, linux-pm,
devicetree, linux-kernel, linux-arm-msm
Cc: Christian Marangi
From: Christian Marangi <ansuelsmth@gmail.com>
Add CPU OPP table for IPQ8062, IPQ8064 and IPQ8065 SoC.
Use opp-supported-hw binding to correctly enable and disable the
frequency as IPQ8062 supports up to 1.0Ghz, IPQ8064 supports up to
1.4GHz with 1.2GHz as an additional frequency and IPQ8065 supports
1.7GHZ but doesn't have 1.2GHZ frequency and has to be disabled.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi | 30 +++++++++++
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 67 ++++++++++++++++++++++++
arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi | 65 +++++++++++++++++++++++
3 files changed, 162 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi
index 5d3ebd3e2e51..72d9782c3d6f 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi
@@ -6,3 +6,33 @@ / {
model = "Qualcomm Technologies, Inc. IPQ8062";
compatible = "qcom,ipq8062", "qcom,ipq8064";
};
+
+&opp_table_cpu {
+ opp-384000000 {
+ opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs2 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs3 = <800000 760000 840000>;
+ };
+
+ opp-600000000 {
+ opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3 = <850000 807500 892500>;
+ };
+
+ opp-800000000 {
+ opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2 = <995000 945250 1044750>;
+ opp-microvolt-speed0-pvs3 = <900000 855000 945000>;
+ };
+
+ opp-1000000000 {
+ opp-microvolt-speed0-pvs0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs3 = <950000 902500 997500>;
+ };
+};
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
index 6198f42f6a9c..cbbd28b43dc4 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
@@ -30,6 +30,7 @@ cpu0: cpu@0 {
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
+ operating-points-v2 = <&opp_table_cpu>;
};
cpu1: cpu@1 {
@@ -40,6 +41,7 @@ cpu1: cpu@1 {
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
+ operating-points-v2 = <&opp_table_cpu>;
};
L2: l2-cache {
@@ -49,6 +51,71 @@ L2: l2-cache {
};
};
+ opp_table_cpu: opp-table-cpu {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs2 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs3 = <800000 760000 840000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3 = <850000 807500 892500>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2 = <995000 945250 1044750>;
+ opp-microvolt-speed0-pvs3 = <900000 855000 945000>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt-speed0-pvs0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs3 = <950000 902500 997500>;
+ opp-supported-hw = <0x7>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt-speed0-pvs0 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs1 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs2 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs3 = <1000000 950000 1050000>;
+ opp-supported-hw = <0x2>;
+ clock-latency-ns = <100000>;
+ };
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt-speed0-pvs0 = <1250000 1187500 1312500>;
+ opp-microvolt-speed0-pvs1 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs2 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs3 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x6>;
+ clock-latency-ns = <100000>;
+ };
+ };
+
thermal-zones {
sensor0-thermal {
polling-delay-passive = <0>;
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi
index ea49f6cc416d..d9ead31b897b 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi
@@ -6,3 +6,68 @@ / {
model = "Qualcomm Technologies, Inc. IPQ8065";
compatible = "qcom,ipq8065", "qcom,ipq8064";
};
+
+&opp_table_cpu {
+ opp-384000000 {
+ opp-microvolt-speed0-pvs0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs1 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs2 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs4 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs5 = <825000 783750 866250>;
+ opp-microvolt-speed0-pvs6 = <775000 736250 813750>;
+ };
+
+ opp-600000000 {
+ opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs3 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs4 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs5 = <850000 807500 892500>;
+ opp-microvolt-speed0-pvs6 = <800000 760000 840000>;
+ };
+
+ opp-800000000 {
+ opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs3 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs4 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs5 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs6 = <850000 807500 892500>;
+ };
+
+ opp-1000000000 {
+ opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs3 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs4 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs5 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs6 = <900000 855000 945000>;
+ };
+
+ opp-1400000000 {
+ opp-microvolt-speed4-pvs0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed4-pvs1 = <1150000 1092500 1207500>;
+ opp-microvolt-speed4-pvs2 = <1125000 1068750 1181250>;
+ opp-microvolt-speed4-pvs3 = <1100000 1045000 1155000>;
+ opp-microvolt-speed4-pvs4 = <1075000 1021250 1128750>;
+ opp-microvolt-speed4-pvs5 = <1025000 973750 1076250>;
+ opp-microvolt-speed4-pvs6 = <975000 926250 1023750>;
+ };
+
+ opp-1725000000 {
+ opp-hz = /bits/ 64 <1725000000>;
+ opp-microvolt-speed0-pvs0 = <1262500 1199375 1325625>;
+ opp-microvolt-speed0-pvs1 = <1225000 1163750 1286250>;
+ opp-microvolt-speed0-pvs2 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs3 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs4 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs5 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs6 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x4>;
+ clock-latency-ns = <100000>;
+ };
+};
--
2.41.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v4 4/4] ARM: dts: qcom: ipq8064: Add CPU OPP table
2023-09-28 21:04 ` [PATCH v4 4/4] ARM: dts: qcom: ipq8064: Add CPU OPP table Robert Marko
@ 2023-09-29 13:57 ` Konrad Dybcio
2023-09-29 16:19 ` Robert Marko
0 siblings, 1 reply; 7+ messages in thread
From: Konrad Dybcio @ 2023-09-29 13:57 UTC (permalink / raw)
To: Robert Marko, ilia.lin, vireshk, nm, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, agross, andersson, rafael,
linux-pm, devicetree, linux-kernel, linux-arm-msm
Cc: Christian Marangi
On 28.09.2023 23:04, Robert Marko wrote:
> From: Christian Marangi <ansuelsmth@gmail.com>
>
> Add CPU OPP table for IPQ8062, IPQ8064 and IPQ8065 SoC.
> Use opp-supported-hw binding to correctly enable and disable the
> frequency as IPQ8062 supports up to 1.0Ghz, IPQ8064 supports up to
> 1.4GHz with 1.2GHz as an additional frequency and IPQ8065 supports
> 1.7GHZ but doesn't have 1.2GHZ frequency and has to be disabled.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
When resending somebody else's patches, you need to add your own
sign-off at the end.
Konrad
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 4/4] ARM: dts: qcom: ipq8064: Add CPU OPP table
2023-09-29 13:57 ` Konrad Dybcio
@ 2023-09-29 16:19 ` Robert Marko
0 siblings, 0 replies; 7+ messages in thread
From: Robert Marko @ 2023-09-29 16:19 UTC (permalink / raw)
To: Konrad Dybcio
Cc: ilia.lin, vireshk, nm, sboyd, robh+dt, krzysztof.kozlowski+dt,
conor+dt, agross, andersson, rafael, linux-pm, devicetree,
linux-kernel, linux-arm-msm, Christian Marangi
On Fri, 29 Sept 2023 at 15:57, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 28.09.2023 23:04, Robert Marko wrote:
> > From: Christian Marangi <ansuelsmth@gmail.com>
> >
> > Add CPU OPP table for IPQ8062, IPQ8064 and IPQ8065 SoC.
> > Use opp-supported-hw binding to correctly enable and disable the
> > frequency as IPQ8062 supports up to 1.0Ghz, IPQ8064 supports up to
> > 1.4GHz with 1.2GHz as an additional frequency and IPQ8065 supports
> > 1.7GHZ but doesn't have 1.2GHZ frequency and has to be disabled.
> >
> > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> > ---
> When resending somebody else's patches, you need to add your own
> sign-off at the end.
Yes, I spotted it only after sending and it did not make sense to
resend immediately it.
Will be part of v5 that has DT bindings sorted out.
Regards,
Robert
>
> Konrad
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-09-29 16:19 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-09-28 21:04 [PATCH v4 1/4] cpufreq: qcom-nvmem: add support for IPQ8074 Robert Marko
2023-09-28 21:04 ` [PATCH v4 2/4] dt-bindings: opp: opp-v2-kryo-cpu: Document named opp-microvolt property Robert Marko
2023-09-28 22:49 ` Rob Herring
2023-09-28 21:04 ` [PATCH v4 3/4] cpufreq: qcom-nvmem: add support for IPQ8064 Robert Marko
2023-09-28 21:04 ` [PATCH v4 4/4] ARM: dts: qcom: ipq8064: Add CPU OPP table Robert Marko
2023-09-29 13:57 ` Konrad Dybcio
2023-09-29 16:19 ` Robert Marko
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).