[PATCH v5 0/6] cpufreq: qcom-nvmem: support apq8064 cpufreq scaling

[PATCH v5 0/6] cpufreq: qcom-nvmem: support apq8064 cpufreq scaling

[Dmitry Baryshkov]

This is a split of APQ8064 cpufreq series, as requested by Viresh. This
series includes only opp and cpufreq parts, with the DT and soc parts
being split to a separate patchset.

Each core has independent power and frequency control. Additionally the
L2 cache is scaled to follow the CPU frequencies (failure to do so
results in strange semi-random crashes).

Core voltage is controlled through the SAW2 devices, one for each core.
The L2 has two regulators, vdd-mem and vdd-dig.

Changes since v4:
- Reordered variables in qcom_cpufreq_init() (Konrad)
- Fixed of_platform_device_create() error check (Konrad)
- Dropped unused ret variable in qcom_cpufreq_apq8064_name_version() (Konrad)

Changes since v3:
- Split the series (Viresh)
- Unrolled loops in krait_l2_config_regulators() (Konrad)

Dmitry Baryshkov (6):
  dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs
  cpufreq: qcom-nvmem: create L2 cache device
  cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu
  cpufreq: qcom-nvmem: drop pvs_ver for format a fuses
  cpufreq: qcom-nvmem: provide separate configuration data for apq8064
  cpufreq: qcom-nvmem: enable core voltage scaling for MSM8960

 .../bindings/opp/opp-v2-kryo-cpu.yaml         | 12 ++-
 drivers/cpufreq/qcom-cpufreq-nvmem.c          | 80 +++++++++++++++++--
 2 files changed, 81 insertions(+), 11 deletions(-)

-- 
2.39.2

[PATCH v5 1/6] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs

[Dmitry Baryshkov]

Exted the opp-v2-kryo-cpu.yaml to support defining OPP tables for the
previous generation of Qualcomm CPUs, 32-bit Krait-based platforms.

It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility
node for the Krait cores. Add support for the Krait-specific
'operating-points-v2-krait-cpu' compatibility string and the relevant
opp-microvolt subclasses properties.

The listed opp-supported-hw values are applicable only to msm8996 /
msm8996pro platforms. Remove the enum as other platforms will use other
bit values. It makes little sense to list all possible values for all
the platforms here.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/opp/opp-v2-kryo-cpu.yaml     | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
index 27ea7eca73e5..316f9c7804e4 100644
--- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
+++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
@@ -26,7 +26,9 @@ description: |
 
 properties:
   compatible:
-    const: operating-points-v2-kryo-cpu
+    enum:
+      - operating-points-v2-krait-cpu
+      - operating-points-v2-kryo-cpu
 
   nvmem-cells:
     description: |
@@ -65,14 +67,16 @@ patternProperties:
           5:  MSM8996SG, speedbin 1
           6:  MSM8996SG, speedbin 2
           7-31:  unused
-        enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
-               0x9, 0xd, 0xe, 0xf,
-               0x10, 0x20, 0x30, 0x70]
+
+          Other platforms use bits directly corresponding to speedbin index.
 
       clock-latency-ns: true
 
       required-opps: true
 
+    patternProperties:
+      '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true
+
     required:
       - opp-hz
 
-- 
2.39.2

[PATCH v5 2/6] cpufreq: qcom-nvmem: create L2 cache device

[Dmitry Baryshkov]

Scaling the frequencies on some of Qualcomm Krait platforms (e.g.
APQ8064) also requires scaling of the L2 cache frequency. As the
l2-cache device node is places under /cpus/ path, it is not created by
default by the OF code. Create corresponding device here.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/cpufreq/qcom-cpufreq-nvmem.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 84d7033e5efe..919f2ee9cafe 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -22,6 +22,7 @@
 #include <linux/module.h>
 #include <linux/nvmem-consumer.h>
 #include <linux/of.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/pm_domain.h>
 #include <linux/pm_opp.h>
@@ -377,6 +378,7 @@ static int __init qcom_cpufreq_init(void)
 {
 	struct device_node *np = of_find_node_by_path("/");
 	const struct of_device_id *match;
+	unsigned int cpu;
 	int ret;
 
 	if (!np)
@@ -387,6 +389,25 @@ static int __init qcom_cpufreq_init(void)
 	if (!match)
 		return -ENODEV;
 
+	for_each_possible_cpu(cpu) {
+		struct device *dev = get_cpu_device(cpu);
+		struct platform_device *pdev;
+		struct device_node *cache;
+
+		cache = of_find_next_cache_node(dev->of_node);
+		if (!cache)
+			continue;
+
+		if (of_device_is_compatible(cache, "qcom,krait-l2-cache")) {
+			pdev = of_platform_device_create(cache, NULL, NULL);
+			/* ignore, this error is not fatal */
+			if (!pdev)
+				pr_err("%s: %pe, failed to create L2 cache node\n", __func__, pdev);
+		}
+
+		of_node_put(cache);
+	}
+
 	ret = platform_driver_register(&qcom_cpufreq_driver);
 	if (unlikely(ret < 0))
 		return ret;
-- 
2.39.2

[PATCH v5 3/6] cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu

[Dmitry Baryshkov]

the qcom-cpufreq-nvmem driver attempts to support both Qualcomm Kryo
(newer 64-bit ARMv8 cores) and Krait (older 32-bit ARMv7 cores). It
makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node
for the Krait cores. Add support for 'operating-points-v2-krait-cpu'
compatibility string.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/cpufreq/qcom-cpufreq-nvmem.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 919f2ee9cafe..9db060bed742 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -238,7 +238,8 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 	if (!np)
 		return -ENOENT;
 
-	ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
+	ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") ||
+	      of_device_is_compatible(np, "operating-points-v2-krait-cpu");
 	if (!ret) {
 		of_node_put(np);
 		return -ENOENT;
-- 
2.39.2

[PATCH v5 4/6] cpufreq: qcom-nvmem: drop pvs_ver for format a fuses

[Dmitry Baryshkov]

The fuses used on msm8960 / apq8064 / ipq806x families of devices do not
have the pvs version. Drop this argument from parsing function.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/cpufreq/qcom-cpufreq-nvmem.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 9db060bed742..e5c17d9f5a24 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -50,7 +50,7 @@ struct qcom_cpufreq_drv {
 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
 
 static void get_krait_bin_format_a(struct device *cpu_dev,
-					  int *speed, int *pvs, int *pvs_ver,
+					  int *speed, int *pvs,
 					  u8 *buf)
 {
 	u32 pte_efuse;
@@ -181,8 +181,7 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
 
 	switch (len) {
 	case 4:
-		get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
-				       speedbin);
+		get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
 		break;
 	case 8:
 		get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
-- 
2.39.2

[PATCH v5 5/6] cpufreq: qcom-nvmem: provide separate configuration data for apq8064

[Dmitry Baryshkov]

APQ8064 can scale core voltage according to the frequency needs. Rather
than reusing the A/B format multiplexer, use a simple fuse parsing
function and configure required regulator.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/cpufreq/qcom-cpufreq-nvmem.c | 49 ++++++++++++++++++++++++++--
 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index e5c17d9f5a24..e1cf677b0c6f 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -26,6 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/pm_domain.h>
 #include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
 #include <linux/slab.h>
 #include <linux/soc/qcom/smem.h>
 
@@ -39,6 +40,7 @@ struct qcom_cpufreq_match_data {
 			   char **pvs_name,
 			   struct qcom_cpufreq_drv *drv);
 	const char **genpd_names;
+	const char * const *regulator_names;
 };
 
 struct qcom_cpufreq_drv {
@@ -203,6 +205,34 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
 	return ret;
 }
 
+static int qcom_cpufreq_apq8064_name_version(struct device *cpu_dev,
+					     struct nvmem_cell *speedbin_nvmem,
+					     char **pvs_name,
+					     struct qcom_cpufreq_drv *drv)
+{
+	int speed = 0, pvs = 0;
+	u8 *speedbin;
+	size_t len;
+
+	speedbin = nvmem_cell_read(speedbin_nvmem, &len);
+	if (IS_ERR(speedbin))
+		return PTR_ERR(speedbin);
+
+	if (len != 4)
+		return -EINVAL;
+
+	get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
+
+	snprintf(*pvs_name, sizeof("speedXX-pvsXX"), "speed%d-pvs%d",
+		 speed, pvs);
+
+	drv->versions = (1 << speed);
+
+	kfree(speedbin);
+
+	return 0;
+}
+
 static const struct qcom_cpufreq_match_data match_data_kryo = {
 	.get_version = qcom_cpufreq_kryo_name_version,
 };
@@ -217,6 +247,16 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = {
 	.genpd_names = qcs404_genpd_names,
 };
 
+static const char * apq8064_regulator_names[] = {
+	"vdd-core",
+	NULL
+};
+
+static const struct qcom_cpufreq_match_data match_data_apq8064 = {
+	.get_version = qcom_cpufreq_apq8064_name_version,
+	.regulator_names = apq8064_regulator_names,
+};
+
 static int qcom_cpufreq_probe(struct platform_device *pdev)
 {
 	struct qcom_cpufreq_drv *drv;
@@ -304,7 +344,12 @@ static int qcom_cpufreq_probe(struct platform_device *pdev)
 			config.virt_devs = NULL;
 		}
 
-		if (config.supported_hw || config.genpd_names) {
+		if (drv->data->regulator_names)
+			config.regulator_names = drv->data->regulator_names;
+
+		if (config.supported_hw ||
+		    config.genpd_names ||
+		    config.regulator_names) {
 			drv->opp_tokens[cpu] = dev_pm_opp_set_config(cpu_dev, &config);
 			if (drv->opp_tokens[cpu] < 0) {
 				ret = drv->opp_tokens[cpu];
@@ -361,7 +406,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
 	{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
 	{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
 	{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
-	{ .compatible = "qcom,apq8064", .data = &match_data_krait },
+	{ .compatible = "qcom,apq8064", .data = &match_data_apq8064 },
 	{ .compatible = "qcom,msm8974", .data = &match_data_krait },
 	{ .compatible = "qcom,msm8960", .data = &match_data_krait },
 	{},
-- 
2.39.2

[PATCH v5 6/6] cpufreq: qcom-nvmem: enable core voltage scaling for MSM8960

[Dmitry Baryshkov]

Reuse APQ8064 config for MSM8960 to enable core voltage scaling.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/cpufreq/qcom-cpufreq-nvmem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index e1cf677b0c6f..6b54a674e9ea 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -408,7 +408,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
 	{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
 	{ .compatible = "qcom,apq8064", .data = &match_data_apq8064 },
 	{ .compatible = "qcom,msm8974", .data = &match_data_krait },
-	{ .compatible = "qcom,msm8960", .data = &match_data_krait },
+	{ .compatible = "qcom,msm8960", .data = &match_data_apq8064 },
 	{},
 };
 MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
-- 
2.39.2

Re: [PATCH v5 0/6] cpufreq: qcom-nvmem: support apq8064 cpufreq scaling

[Viresh Kumar]

On 02-10-23, 21:59, Dmitry Baryshkov wrote:
> This is a split of APQ8064 cpufreq series, as requested by Viresh. This
> series includes only opp and cpufreq parts, with the DT and soc parts
> being split to a separate patchset.
> 
> Each core has independent power and frequency control. Additionally the
> L2 cache is scaled to follow the CPU frequencies (failure to do so
> results in strange semi-random crashes).
> 
> Core voltage is controlled through the SAW2 devices, one for each core.
> The L2 has two regulators, vdd-mem and vdd-dig.
> 
> Changes since v4:
> - Reordered variables in qcom_cpufreq_init() (Konrad)
> - Fixed of_platform_device_create() error check (Konrad)
> - Dropped unused ret variable in qcom_cpufreq_apq8064_name_version() (Konrad)

Applied. Thanks.

-- 
viresh

Re: [PATCH v5 0/6] cpufreq: qcom-nvmem: support apq8064 cpufreq scaling

[Viresh Kumar]

On 10-10-23, 12:02, Viresh Kumar wrote:
> On 02-10-23, 21:59, Dmitry Baryshkov wrote:
> > This is a split of APQ8064 cpufreq series, as requested by Viresh. This
> > series includes only opp and cpufreq parts, with the DT and soc parts
> > being split to a separate patchset.
> > 
> > Each core has independent power and frequency control. Additionally the
> > L2 cache is scaled to follow the CPU frequencies (failure to do so
> > results in strange semi-random crashes).
> > 
> > Core voltage is controlled through the SAW2 devices, one for each core.
> > The L2 has two regulators, vdd-mem and vdd-dig.
> > 
> > Changes since v4:
> > - Reordered variables in qcom_cpufreq_init() (Konrad)
> > - Fixed of_platform_device_create() error check (Konrad)
> > - Dropped unused ret variable in qcom_cpufreq_apq8064_name_version() (Konrad)
> 
> Applied. Thanks.

Since these are causing build issues, and it isn't entirely clear what's the
right approach for now, I have dropped the changes from my branch to avoid any
further issues. You don't need to resend these, lets finalize a solution and
then I can apply them again.

-- 
viresh

Re: [PATCH v5 0/6] cpufreq: qcom-nvmem: support apq8064 cpufreq scaling

[Christian Marangi]

On Thu, Oct 12, 2023 at 09:12:41AM +0530, Viresh Kumar wrote:
> On 10-10-23, 12:02, Viresh Kumar wrote:
> > On 02-10-23, 21:59, Dmitry Baryshkov wrote:
> > > This is a split of APQ8064 cpufreq series, as requested by Viresh. This
> > > series includes only opp and cpufreq parts, with the DT and soc parts
> > > being split to a separate patchset.
> > > 
> > > Each core has independent power and frequency control. Additionally the
> > > L2 cache is scaled to follow the CPU frequencies (failure to do so
> > > results in strange semi-random crashes).
> > > 
> > > Core voltage is controlled through the SAW2 devices, one for each core.
> > > The L2 has two regulators, vdd-mem and vdd-dig.
> > > 
> > > Changes since v4:
> > > - Reordered variables in qcom_cpufreq_init() (Konrad)
> > > - Fixed of_platform_device_create() error check (Konrad)
> > > - Dropped unused ret variable in qcom_cpufreq_apq8064_name_version() (Konrad)
> > 
> > Applied. Thanks.
> 
> Since these are causing build issues, and it isn't entirely clear what's the
> right approach for now, I have dropped the changes from my branch to avoid any
> further issues. You don't need to resend these, lets finalize a solution and
> then I can apply them again.
> 

Hi we have a qcom-cpufreq series that depends on this (or better say we
have rebased it on top of these changes to prevent merge conflicts)

Can you link where this was applied, also can I help in fixing the
compile error to speed things up?

-- 
	Ansuel

Re: [PATCH v5 0/6] cpufreq: qcom-nvmem: support apq8064 cpufreq scaling

[Viresh Kumar]

On 12-10-23, 10:40, Christian Marangi wrote:
> On Thu, Oct 12, 2023 at 09:12:41AM +0530, Viresh Kumar wrote:
> > On 10-10-23, 12:02, Viresh Kumar wrote:
> > > On 02-10-23, 21:59, Dmitry Baryshkov wrote:
> > > > This is a split of APQ8064 cpufreq series, as requested by Viresh. This
> > > > series includes only opp and cpufreq parts, with the DT and soc parts
> > > > being split to a separate patchset.
> > > > 
> > > > Each core has independent power and frequency control. Additionally the
> > > > L2 cache is scaled to follow the CPU frequencies (failure to do so
> > > > results in strange semi-random crashes).
> > > > 
> > > > Core voltage is controlled through the SAW2 devices, one for each core.
> > > > The L2 has two regulators, vdd-mem and vdd-dig.
> > > > 
> > > > Changes since v4:
> > > > - Reordered variables in qcom_cpufreq_init() (Konrad)
> > > > - Fixed of_platform_device_create() error check (Konrad)
> > > > - Dropped unused ret variable in qcom_cpufreq_apq8064_name_version() (Konrad)
> > > 
> > > Applied. Thanks.
> > 
> > Since these are causing build issues, and it isn't entirely clear what's the
> > right approach for now, I have dropped the changes from my branch to avoid any
> > further issues. You don't need to resend these, lets finalize a solution and
> > then I can apply them again.
> > 
> 
> Hi we have a qcom-cpufreq series that depends on this (or better say we
> have rebased it on top of these changes to prevent merge conflicts)

That shouldn't be an issue I guess, we are likely not going to change anything
in these patches but something else:

https://lore.kernel.org/all/20231011112726.166052-1-dmitry.baryshkov@linaro.org/

> Can you link where this was applied, also can I help in fixing the
> compile error to speed things up?

I applied them here earlier.

git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git opp/linux-next

-- 
viresh

Re: [PATCH v5 0/6] cpufreq: qcom-nvmem: support apq8064 cpufreq scaling

[Christian Marangi]

On Thu, Oct 12, 2023 at 02:30:56PM +0530, Viresh Kumar wrote:
> On 12-10-23, 10:40, Christian Marangi wrote:
> > On Thu, Oct 12, 2023 at 09:12:41AM +0530, Viresh Kumar wrote:
> > > On 10-10-23, 12:02, Viresh Kumar wrote:
> > > > On 02-10-23, 21:59, Dmitry Baryshkov wrote:
> > > > > This is a split of APQ8064 cpufreq series, as requested by Viresh. This
> > > > > series includes only opp and cpufreq parts, with the DT and soc parts
> > > > > being split to a separate patchset.
> > > > > 
> > > > > Each core has independent power and frequency control. Additionally the
> > > > > L2 cache is scaled to follow the CPU frequencies (failure to do so
> > > > > results in strange semi-random crashes).
> > > > > 
> > > > > Core voltage is controlled through the SAW2 devices, one for each core.
> > > > > The L2 has two regulators, vdd-mem and vdd-dig.
> > > > > 
> > > > > Changes since v4:
> > > > > - Reordered variables in qcom_cpufreq_init() (Konrad)
> > > > > - Fixed of_platform_device_create() error check (Konrad)
> > > > > - Dropped unused ret variable in qcom_cpufreq_apq8064_name_version() (Konrad)
> > > > 
> > > > Applied. Thanks.
> > > 
> > > Since these are causing build issues, and it isn't entirely clear what's the
> > > right approach for now, I have dropped the changes from my branch to avoid any
> > > further issues. You don't need to resend these, lets finalize a solution and
> > > then I can apply them again.
> > > 
> > 
> > Hi we have a qcom-cpufreq series that depends on this (or better say we
> > have rebased it on top of these changes to prevent merge conflicts)
> 
> That shouldn't be an issue I guess, we are likely not going to change anything
> in these patches but something else:
> 
> https://lore.kernel.org/all/20231011112726.166052-1-dmitry.baryshkov@linaro.org/
> 
> > Can you link where this was applied, also can I help in fixing the
> > compile error to speed things up?
> 
> I applied them here earlier.
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git opp/linux-next
>

Thanks a lot for the quick answer.

-- 
	Ansuel