Re: [PATCH v1 07/10] arm64: dts: qcom: ipq5332: populate the opp table based on the eFuse

[Varadarajan Narayanan <quic_varada@quicinc.com>]

On Thu, Sep 07, 2023 at 04:59:28PM +0300, Dmitry Baryshkov wrote:
> On Thu, 7 Sept 2023 at 08:23, Varadarajan Narayanan
> <quic_varada@quicinc.com> wrote:
> >
> > IPQ53xx have different OPPs available for the CPU based on
> > SoC variant. This can be determined through use of an eFuse
> > register present in the silicon.
> >
> > Add support to read the eFuse and populate the OPPs based on it.
> >
> > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> >  arch/arm64/boot/dts/qcom/ipq5332.dtsi | 34 +++++++++++++++++++++++++++++++---
> >  1 file changed, 31 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> > index 82761ae..3ca3f34 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> > @@ -91,11 +91,34 @@
> >         };
> >
> >         cpu_opp_table: opp-table-cpu {
> > -               compatible = "operating-points-v2";
> > +               compatible = "operating-points-v2-kryo-cpu";
> >                 opp-shared;
> > +               nvmem-cells = <&cpu_speed_bin>;
> > +               nvmem-cell-names = "speed_bin";
> > +
> > +               /*
> > +                * Listed all supported CPU frequencies and opp-supported-hw
> > +                * values to select CPU frequencies based on the limits fused.
> > +                * ------------------------------------------------------------
> > +                * Frequency     BIT3   BIT2   BIT1    BIT0    opp-supported-hw
> > +                *              1.0GHz 1.2GHz 1.5GHz No Limit
> > +                * ------------------------------------------------------------
> > +                * 1100000000     1      1      1       1            0xF
> > +                * 1500000000     0      0      1       1            0x3
> > +                * -----------------------------------------------------------
> > +                */
>
> This can probably go to the commit message instead.

Ok

> > +
> > +               opp-1100000000 {
> > +                       opp-hz = /bits/ 64 <1100000000>;
>
> But your table shows 1.0 GHz and 1.2 GHz instead of 1.1 GHz

Will update it.

> > +                       opp-microvolt = <850000>;
> > +                       opp-supported-hw = <0xF>;
> > +                       clock-latency-ns = <200000>;
> > +               };
> >
> > -               opp-1488000000 {
> > -                       opp-hz = /bits/ 64 <1488000000>;
> > +               opp-1500000000 {
> > +                       opp-hz = /bits/ 64 <1500000000>;
>
> So, 1.488 GHz or 1.5 GHz?

1.5 GHz

> > +                       opp-microvolt = <950000>;
>
> Which regulator is controlled by this microvolt?

Based on the SKU, the XBL sets up the regulator to provide 950000uV
on CPUs capable of running 1.5G and 850000uV on other SKUs. Linux
doesn't control it.

Thanks
Varada
> > +                       opp-supported-hw = <0x3>;
> >                         clock-latency-ns = <200000>;
> >                 };
> >         };
> > @@ -150,6 +173,11 @@
> >                         reg = <0x000a4000 0x721>;
> >                         #address-cells = <1>;
> >                         #size-cells = <1>;
> > +
> > +                       cpu_speed_bin: cpu_speed_bin@1d {
> > +                               reg = <0x1d 0x2>;
> > +                               bits = <7 2>;
> > +                       };
> >                 };
> >
> >                 rng: rng@e3000 {
> > --
> > 2.7.4
> >
>
>
> --
> With best wishes
> Dmitry