From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D52F377 for ; Tue, 10 Oct 2023 00:58:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="alE/a0hD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 99F29C433C7; Tue, 10 Oct 2023 00:58:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696899508; bh=Z3HEkyCKhfQtz//USnNYtderkTDcTelwZj87FWBEUeQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=alE/a0hDYfFZOsjWJzU8vIDLgh3Rb/Am6ZSCuAvYz6kX1wQxxJWuLsWMaMBt1mXfY Sj8wz/H/H1RDlIRcZsTiy9hRu/clFVqPXXsG9PYCnLqUtrPCkHiY+/SspD+pXv+ABD ANN0+gk8LdrvBjivN4I9smcjq6kyAickMEPBbAj16nTio8V60vtD2qJJ9A6QQB4QLV 2DAVG7343ij8AYRadgJOJHrxBJJFdSRGFNFieNo1hzWjHIyLhhT0MDDC0EBPyGA7Fo 2nfySK73WgaNyKFUQg83ltKgcO0bAzHKR+LWF468PtENNy7ldrXuG0KmXH/PABMS7T r0aeRPyE0YunQ== Date: Tue, 10 Oct 2023 08:58:13 +0800 From: Shawn Guo To: Marek Vasut Cc: linux-arm-kernel@lists.infradead.org, Conor Dooley , Fabio Estevam , Frieder Schrempf , Geert Uytterhoeven , Krzysztof Kozlowski , Magnus Damm , NXP Linux Team , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , devicetree@vger.kernel.org Subject: Re: [PATCH] arm64: dts: imx8mp: Describe VDD_ARM run and standby voltage for Data Modul i.MX8M Plus eDM SBC Message-ID: <20231010005813.GG733979@dragon> References: <20230831181850.154813-1-marex@denx.de> <20230924142150.GM7231@dragon> <20231009123606.GA733979@dragon> <18174105-de83-436c-9e77-2c61e1ef2c71@denx.de> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <18174105-de83-436c-9e77-2c61e1ef2c71@denx.de> On Mon, Oct 09, 2023 at 04:03:01PM +0200, Marek Vasut wrote: > On 10/9/23 14:36, Shawn Guo wrote: > > On Sun, Oct 08, 2023 at 08:37:34PM +0200, Marek Vasut wrote: > > > On 9/24/23 16:21, Shawn Guo wrote: > > > > On Thu, Aug 31, 2023 at 08:18:50PM +0200, Marek Vasut wrote: > > > > > Describe VDD_ARM (BUCK2) run and standby voltage in DT. > > > > > > > > > > Signed-off-by: Marek Vasut > > > > > --- > > > > > Cc: Conor Dooley > > > > > Cc: Fabio Estevam > > > > > Cc: Frieder Schrempf > > > > > Cc: Geert Uytterhoeven > > > > > Cc: Krzysztof Kozlowski > > > > > Cc: Magnus Damm > > > > > Cc: Marek Vasut > > > > > Cc: NXP Linux Team > > > > > Cc: Peng Fan > > > > > Cc: Pengutronix Kernel Team > > > > > Cc: Rob Herring > > > > > Cc: Sascha Hauer > > > > > Cc: Shawn Guo > > > > > Cc: devicetree@vger.kernel.org > > > > > Cc: linux-arm-kernel@lists.infradead.org > > > > > --- > > > > > arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts | 2 ++ > > > > > 1 file changed, 2 insertions(+) > > > > > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts > > > > > index 13674dc64be9d..d98a040860a48 100644 > > > > > --- a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts > > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts > > > > > @@ -362,6 +362,8 @@ buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ > > > > > }; > > > > > buck2: BUCK2 { /* VDD_ARM */ > > > > > + nxp,dvs-run-voltage = <950000>; > > > > > + nxp,dvs-standby-voltage = <850000>; > > > > > > > > Buck2 is not turned off in DSM on i.MX8MP? > > > > > > It is turned off in SUSPEND/SNVS/OFF , not in IDLE/RUN . > > > > Right. But nxp,dvs-standby-voltage specifies the voltage when PMIC > > is in STANDBY mode. My understanding is that the SoC will be in SUSPEND > > state while PMIC is in STANDBY mode. > > I agree > > > Is it possible that the SoC in > > IDLE/RUN while PMIC is in STANDBY mode at all? > > No, I don't think so, but there's still the PMIC part: > > https://www.nxp.com/docs/en/data-sheet/PCA9450.pdf > > 7.3.7 STANDBY mode > " > PCA9450 transitions to STANDBY mode from RUN mode when > both PMIC_ON_REQ and PMIC_STBY_REQ are driven high. BUCK1 > and BUCK3 output voltage is set to BUCK1OUT_DVS1 and > BUCK3OUT_DVS1 and BUCK2 are turned off when DVS_CTRL bit > in each BUCKx_CTRL register is configured to 1. > " > > Specifically > " > BUCK2 are turned off when DVS_CTRL bit in each > BUCKx_CTRL register is configured to 1. > " > > 8.2.19 0x13 BUCK2CTRL > " > 4 > DVS_CTRL > DVS Control configuration > 0b = BUCK voltage is determined by BUCK2VOUT_DVS0 register regardless of > PMIC_STBY_REQ > 1b = DVS control through PMIC_STBY_REQ > " > > Notice that the reset-default is '0b' , so unless the PMIC is reconfigured, > the BUCK2 will stay powered on even in STANDBY/SUSPEND. Hmm, isn't B2_ENMODE controlling on/off of BUCK2? BUCK2 enable mode 00b = OFF 01b = ON by PMIC_ON_REQ = H 10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L (default) 11b = Always ON So unless you reconfigure the field, BUCK2 will be off when PMIC_STBY_REQ goes high, right? Shawn