From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B19467F0 for ; Tue, 10 Oct 2023 02:25:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TdATxuCP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 26845C433C7; Tue, 10 Oct 2023 02:25:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696904731; bh=qDFAIZJBZaNLR6S/I5Pe62KY//2o+PXQuDVr5YqKROg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=TdATxuCPTumxA4f6U0UOWfIcKsCH+Y+whTQgEUoHmZhwWOiMxA3BMYU2UMiZ21nWh zRvp4SzjZvdpjIUlfYiLUMwd4l6k0lTT/PmjkN+JSytmxp7dUec6a1XAWqPQOOeIIi Vn5+XxqY8jjPThmH74TDBYJQBGIxG6ZSULAAztmHXLraLY4sdNgUrc9NYJJVDROpir +y7ogVkffDbX3YhD9+EjGZi21Z2AK52/KDnYZs2OvvLemqfS3BfdAdDrK6PIt86L5s JJRmMkM4+OX2bqj44KV3f0uUaha766VvTyhHb1iAQF+omNadOsf2fdj62BkC1AfOM1 fFxGrkAWh2rSA== Date: Tue, 10 Oct 2023 10:25:17 +0800 From: Shawn Guo To: Adam Ford Cc: linux-arm-kernel@lists.infradead.org, aford@beaconembedded.com, Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , Geert Uytterhoeven , Magnus Damm , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH V3] arm64: dts: imx8mp-beacon: Configure 100MHz PCIe Ref Clk Message-ID: <20231010022517.GJ819755@dragon> References: <20231004235148.45562-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231004235148.45562-1-aford173@gmail.com> On Wed, Oct 04, 2023 at 06:51:47PM -0500, Adam Ford wrote: > There is a I2C controlled 100MHz Reference clock used by the PCIe > controller. Configure this clock's DIF1 output to be used by > the PCIe. > > Signed-off-by: Adam Ford > Reviewed-by: Fabio Estevam Applied, thanks!