From: Manivannan Sadhasivam <mani@kernel.org>
To: "Krzysztof Wilczyński" <kw@linux.com>
Cc: Serge Semin <fancer.lancer@gmail.com>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
lpieralisi@kernel.org, robh@kernel.org, bhelgaas@google.com,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
mani@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v24 08/16] PCI: dwc: Disable two BARs to avoid unnecessary memory assignment
Date: Wed, 11 Oct 2023 18:48:40 +0530 [thread overview]
Message-ID: <20231011131840.GB5952@thinkpad> (raw)
In-Reply-To: <20231011130727.GA3722793@rocinante>
On Wed, Oct 11, 2023 at 10:07:27PM +0900, Krzysztof Wilczyński wrote:
> Hello,
>
> [...]
> > > + /*
> > > + * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
> > > + * Rev.5.20a,
> >
> > and 3.5.6.1 "RC mode" in DWC PCIe RC databook v5.20a.
>
> OK. I can fix this citation later.
>
> > > + ... we should disable two BARs to avoid unnecessary memory
> > > + * assignment during device enumeration.
> > > + */
> > > + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0);
> > > + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_1, 0x0);
> > > +
> >
> > What's the point in doing this
> > dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
> > dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
> > ...
> > dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
> > afterward?
> >
> > I guess if the BARs are disabled there is no need in having them
> > touched. Am I wrong?
> >
> > BTW I failed to understand why the BARs inits was originally needed:
> > first merging the BAR0 and BAR1 into a single 64-bit BAR, then
> > switching it back to two 32-bit BARs. Moreover here is what prior DW
> > PCIe RC v5.x databooks say about the BARs:
> >
> > "3.5.6 BAR Details
> > Base Address Registers (Offset: 0x10-x14)
> > The Synopsys core does not implement the optional BARs for the RC
> > product. This is based on the assumption that the RC host probably has
> > registers on some other internal bus and has knowledge and setup
> > access to these registers already."
> >
> > I am not sure I fully understand what it means, but it seems as DW
> > PCIe cores didn't have anything behind the RC BARs even back then. So
> > it seems to me that the BARs manipulation was the Exinos PCIe host
> > specific, from which driver they are originating - commit 340cba6092c2
> > ("pci: Add PCIe driver for Samsung Exynos").
>
> Would any of the above be something we need to address before this series
> can be successfully merged? I am asking if this is a show stopper,
> something we can fix later, or even something I could address once I take
> this series again.
>
> Thoughts?
>
If Yoshihiro can confirm that his controller can work without this patch, then
I'd vote for dropping this patch and applying the rest.
This can be submitted later if required.
- Mani
> > * BTW Yoshihiro, I am sorry to see your patchset is still under review...(
>
> Yes, we need to draw a line somewhere. :) I am happy to take this series
> so we don't miss another merge window. We can always fix other bits and
> pieces later and iron out any kinks that might have fallen through the
> cracks, so to speak.
>
> Krzysztof
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2023-10-11 13:18 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-11 7:14 [PATCH v24 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 01/16] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 02/16] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 03/16] PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 04/16] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 05/16] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 06/16] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 07/16] PCI: dwc: endpoint: Introduce .pre_init() and .deinit() Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 08/16] PCI: dwc: Disable two BARs to avoid unnecessary memory assignment Yoshihiro Shimoda
2023-10-11 11:45 ` Serge Semin
2023-10-11 13:07 ` Krzysztof Wilczyński
2023-10-11 13:18 ` Manivannan Sadhasivam [this message]
2023-10-11 14:50 ` Serge Semin
2023-10-12 8:03 ` Yoshihiro Shimoda
2023-10-16 21:48 ` Bjorn Helgaas
2023-10-17 4:39 ` Siddharth Vadapalli
2023-10-17 9:19 ` Marek Szyprowski
2023-10-17 12:05 ` Yoshihiro Shimoda
2023-10-17 15:16 ` mani
2023-10-18 0:11 ` Yoshihiro Shimoda
2023-10-17 18:58 ` Bjorn Helgaas
2023-10-11 7:14 ` [PATCH v24 09/16] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 10/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 11/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 12/16] PCI: Add T_PVPERL macro Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 13/16] PCI: rcar-gen4: Add R-Car Gen4 PCIe controller support for host mode Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 14/16] PCI: rcar-gen4: Add endpoint mode support Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 15/16] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2023-10-11 7:14 ` [PATCH v24 16/16] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
2023-10-14 21:44 ` [PATCH v24 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Krzysztof Wilczyński
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