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Date: Thu, 12 Oct 2023 10:41:45 +0100
From: Conor Dooley <conor@kernel.org>
To: Inochi Amaoto <inochiama@outlook.com>
Cc: Chen Wang <unicorn_wang@outlook.com>, Chao Wei <chao.wei@sophgo.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Jisheng Zhang <jszhang@kernel.org>, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC
 device tree
Message-ID: <20231012-gratuity-siesta-b9e06b11be43@spud>
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On Tue, Oct 10, 2023 at 03:53:54PM +0800, Inochi Amaoto wrote:
> >On 2023/10/9 19:26, Inochi Amaoto wrote:
> >> Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
> >>
> >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> >> ---
> >>   arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 36 +++++++++++++++++++++++=
++
> >>   1 file changed, 36 insertions(+)
> >>   create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> >>
> >> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot=
/dts/sophgo/cv1812h.dtsi
> >> new file mode 100644
> >> index 000000000000..3864d34b0100
> >> --- /dev/null
> >> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> >> @@ -0,0 +1,36 @@
> >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> +/*
> >> + * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
> >> + */
> >> +
> >> +#include <dt-bindings/interrupt-controller/irq.h>
> >This include is not required.
>=20
> Thx.

I can drop this include on application. Is the rest of the series okay
with you Chen Wang?

Thanks,
Conor.

>=20
> >> +#include "cv180x.dtsi"
> >> +
> >> +/ {
> >> +    compatible =3D "sophgo,cv1812h";
> >> +
> >> +    memory@80000000 {
> >> +        device_type =3D "memory";
> >> +        reg =3D <0x80000000 0x10000000>;
> >> +    };
> >What's this defined for , I see this is different against cv1800b.
>=20
> CV1812h have a embedded 256MB RAM. The cv1800b is 64MB, This is why the
> size is different. I write this node here because the RAM is embedded
> and fixed size, and leave it in the board DT is unnecessary.
>=20
> >> +
> >> +    soc {
> >> +        interrupt-parent =3D <&plic>;
> >> +
> >> +        plic: interrupt-controller@70000000 {
> >> +            compatible =3D "sophgo,cv1812h-plic", "thead,c900-plic";
> >> +            reg =3D <0x70000000 0x4000000>;
> >> +            interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>;
> >> +            interrupt-controller;
> >> +            #address-cells =3D <0>;
> >> +            #interrupt-cells =3D <2>;
> >> +            riscv,ndev =3D <101>;
> >> +        };
> >> +
> >> +        clint: timer@74000000 {
> >> +            compatible =3D "sophgo,cv1812h-clint", "thead,c900-clint";
> >> +            reg =3D <0x74000000 0x10000>;
> >> +            interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>;
> >> +        };
> >> +    };
> >> +};
> >> --
> >> 2.42.0
> >>
> >

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