From: Conor Dooley <conor@kernel.org>
To: kernel@esmil.dk, conor@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu,
william.qiu@starfivetech.com, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Nam Cao <namcao@linutronix.de>
Cc: Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v2] riscv: dts: starfive: visionfive 2: correct spi's ss pin
Date: Thu, 12 Oct 2023 10:24:18 +0100 [thread overview]
Message-ID: <20231012-pointless-underpaid-649da93b1762@spud> (raw)
In-Reply-To: <20231012091729.3fzfDD1I@linutronix.de>
From: Conor Dooley <conor.dooley@microchip.com>
On Thu, 12 Oct 2023 11:17:29 +0200, Nam Cao wrote:
> The ss pin of spi0 is the same as sck pin. According to the
> visionfive 2 documentation, it should be pin 49 instead of 48.
>
>
Applied to riscv-dt-fixes, thanks!
[1/1] riscv: dts: starfive: visionfive 2: correct spi's ss pin
https://git.kernel.org/conor/c/cf98fe6b579e
Thanks,
Conor.
prev parent reply other threads:[~2023-10-12 9:25 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-12 9:17 [PATCH v2] riscv: dts: starfive: visionfive 2: correct spi's ss pin Nam Cao
2023-10-12 9:24 ` Conor Dooley [this message]
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