* [PATCH v2] riscv: dts: starfive: visionfive 2: correct spi's ss pin
@ 2023-10-12 9:17 Nam Cao
2023-10-12 9:24 ` Conor Dooley
0 siblings, 1 reply; 2+ messages in thread
From: Nam Cao @ 2023-10-12 9:17 UTC (permalink / raw)
To: kernel, conor, robh+dt, krzysztof.kozlowski+dt, paul.walmsley,
palmer, aou, william.qiu, linux-riscv, devicetree, linux-kernel
The ss pin of spi0 is the same as sck pin. According to the
visionfive 2 documentation, it should be pin 49 instead of 48.
Fixes: 74fb20c8f05d ("riscv: dts: starfive: Add spi node and pins configuration")
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Nam Cao <namcao@linutronix.de>
---
v2: resend due to email problem
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 12ebe9792356..2c02358abd71 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -431,7 +431,7 @@ GPOEN_ENABLE,
};
ss-pins {
- pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS,
+ pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
GPOEN_ENABLE,
GPI_SYS_SPI0_FSS)>;
bias-disable;
--
2.39.2
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH v2] riscv: dts: starfive: visionfive 2: correct spi's ss pin
2023-10-12 9:17 [PATCH v2] riscv: dts: starfive: visionfive 2: correct spi's ss pin Nam Cao
@ 2023-10-12 9:24 ` Conor Dooley
0 siblings, 0 replies; 2+ messages in thread
From: Conor Dooley @ 2023-10-12 9:24 UTC (permalink / raw)
To: kernel, conor, robh+dt, krzysztof.kozlowski+dt, paul.walmsley,
palmer, aou, william.qiu, linux-riscv, devicetree, linux-kernel,
Nam Cao
Cc: Conor Dooley
From: Conor Dooley <conor.dooley@microchip.com>
On Thu, 12 Oct 2023 11:17:29 +0200, Nam Cao wrote:
> The ss pin of spi0 is the same as sck pin. According to the
> visionfive 2 documentation, it should be pin 49 instead of 48.
>
>
Applied to riscv-dt-fixes, thanks!
[1/1] riscv: dts: starfive: visionfive 2: correct spi's ss pin
https://git.kernel.org/conor/c/cf98fe6b579e
Thanks,
Conor.
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