From: Sascha Hauer <s.hauer@pengutronix.de>
To: Chanwoo Choi <chanwoo@kernel.org>
Cc: linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
Heiko Stuebner <heiko@sntech.de>,
Kyungmin Park <kyungmin.park@samsung.com>,
MyungJoo Ham <myungjoo.ham@samsung.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
kernel@pengutronix.de,
Michael Riesch <michael.riesch@wolfvision.net>,
Robin Murphy <robin.murphy@arm.com>,
Vincent Legoll <vincent.legoll@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org,
Sebastian Reichel <sebastian.reichel@collabora.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH v7 18/26] PM / devfreq: rockchip-dfi: account for multiple DDRMON_CTRL registers
Date: Mon, 16 Oct 2023 14:49:03 +0200 [thread overview]
Message-ID: <20231016124903.GC3359458@pengutronix.de> (raw)
In-Reply-To: <98c448be-8ea8-a0bd-62cc-3bc3a5cf5569@kernel.org>
On Mon, Oct 09, 2023 at 07:19:04AM +0900, Chanwoo Choi wrote:
> On 23. 7. 4. 18:32, Sascha Hauer wrote:
> > The currently supported RK3399 has a set of registers per channel, but
> > it has only a single DDRMON_CTRL register. With upcoming RK3588 this
> > will be different, the RK3588 has a DDRMON_CTRL register per channel.
> >
> > Instead of expecting a single DDRMON_CTRL register, loop over the
> > channels and write the channel specific DDRMON_CTRL register. Break
> > out early out of the loop when there is only a single DDRMON_CTRL
> > register like on the RK3399.
> >
> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > drivers/devfreq/event/rockchip-dfi.c | 72 ++++++++++++++++++----------
> > 1 file changed, 48 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> > index 85ec93fd41858..2362d3953ba40 100644
> > --- a/drivers/devfreq/event/rockchip-dfi.c
> > +++ b/drivers/devfreq/event/rockchip-dfi.c
> > @@ -113,12 +113,13 @@ struct rockchip_dfi {
> > int burst_len;
> > int buswidth[DMC_MAX_CHANNELS];
> > int ddrmon_stride;
> > + bool ddrmon_ctrl_single;
> > };
> >
> > static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
> > {
> > void __iomem *dfi_regs = dfi->regs;
> > - int ret = 0;
> > + int i, ret = 0;
> >
> > mutex_lock(&dfi->mutex);
> >
> > @@ -132,29 +133,41 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
> > goto out;
> > }
> >
> > - /* clear DDRMON_CTRL setting */
> > - writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN |
> > - DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
> > + for (i = 0; i < DMC_MAX_CHANNELS; i++) {
> > + u32 ctrl = 0;
> >
> > - /* set ddr type to dfi */
> > - switch (dfi->ddr_type) {
> > - case ROCKCHIP_DDRTYPE_LPDDR2:
> > - case ROCKCHIP_DDRTYPE_LPDDR3:
> > - writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
> > - dfi_regs + DDRMON_CTRL);
> > - break;
> > - case ROCKCHIP_DDRTYPE_LPDDR4:
> > - case ROCKCHIP_DDRTYPE_LPDDR4X:
> > - writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
> > - dfi_regs + DDRMON_CTRL);
> > - break;
> > - default:
> > - break;
> > - }
> > + if (!(dfi->channel_mask & BIT(i)))
> > + continue;
> >
> > - /* enable count, use software mode */
> > - writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
> > - dfi_regs + DDRMON_CTRL);
> > + /* clear DDRMON_CTRL setting */
> > + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN |
> > + DDRMON_CTRL_SOFTWARE_EN | DDRMON_CTRL_HARDWARE_EN),
> > + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
> > +
> > + /* set ddr type to dfi */
> > + switch (dfi->ddr_type) {
> > + case ROCKCHIP_DDRTYPE_LPDDR2:
> > + case ROCKCHIP_DDRTYPE_LPDDR3:
> > + ctrl = DDRMON_CTRL_LPDDR23;
> > + break;
> > + case ROCKCHIP_DDRTYPE_LPDDR4:
> > + case ROCKCHIP_DDRTYPE_LPDDR4X:
> > + ctrl = DDRMON_CTRL_LPDDR4;
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + writel_relaxed(HIWORD_UPDATE(ctrl, DDRMON_CTRL_DDR_TYPE_MASK),
> > + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
> > +
> > + /* enable count, use software mode */
> > + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
> > + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
> > +
> > + if (dfi->ddrmon_ctrl_single)
> > + break;
> > + }
> > out:
> > mutex_unlock(&dfi->mutex);
> >
> > @@ -164,6 +177,7 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
> > static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
> > {
> > void __iomem *dfi_regs = dfi->regs;
> > + int i;
> >
> > mutex_lock(&dfi->mutex);
> >
> > @@ -174,8 +188,17 @@ static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
> > if (dfi->usecount > 0)
> > goto out;
> >
> > - writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
> > - dfi_regs + DDRMON_CTRL);
> > + for (i = 0; i < DMC_MAX_CHANNELS; i++) {
> > + if (!(dfi->channel_mask & BIT(i)))
> > + continue;
> > +
> > + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
> > + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
> > +
> > + if (dfi->ddrmon_ctrl_single)
> > + break;
> > + }
> > +
> > clk_disable_unprepare(dfi->clk);
> > out:
> > mutex_unlock(&dfi->mutex);
> > @@ -666,6 +689,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
> > dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2;
> >
> > dfi->ddrmon_stride = 0x14;
> > + dfi->ddrmon_ctrl_single = true;
> >
> > return 0;
> > };
>
> Even if rk3568 has the only one channle and don't need to check whether 'dfi->ddrmon_ctrl_single'
> is true or not because of 'if (!(dfi->channel_mask & BIT(i)))',
> I recommand the add 'dfi->ddrmon_ctrl_single = true;' for rk3568 in order to
> provide the number of DDRMON_CTRL reigster of rk3568.
>
> If rk3568 doesn't have the 'ddrmon_ctrl_single', actually it is not easy
> to catch what why are there no initilization for rk3568.
Ok, will change.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
next prev parent reply other threads:[~2023-10-16 12:49 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 9:32 [PATCH v7 00/26] Add perf support to the rockchip-dfi driver Sascha Hauer
2023-07-04 9:32 ` [PATCH v7 01/26] PM / devfreq: rockchip-dfi: Make pmu regmap mandatory Sascha Hauer
2023-10-06 16:03 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 02/26] PM / devfreq: rockchip-dfi: Embed desc into private data struct Sascha Hauer
2023-10-06 16:04 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 03/26] PM / devfreq: rockchip-dfi: use consistent name for " Sascha Hauer
2023-10-06 16:06 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 04/26] PM / devfreq: rockchip-dfi: Add SoC specific init function Sascha Hauer
2023-10-06 16:22 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 05/26] PM / devfreq: rockchip-dfi: dfi store raw values in counter struct Sascha Hauer
2023-10-06 16:34 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 06/26] PM / devfreq: rockchip-dfi: Use free running counter Sascha Hauer
2023-10-06 17:21 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 07/26] PM / devfreq: rockchip-dfi: introduce channel mask Sascha Hauer
2023-10-06 17:21 ` Chanwoo Choi
2023-10-16 11:22 ` Sascha Hauer
2023-10-16 12:45 ` Sascha Hauer
2023-10-17 8:28 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 08/26] PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE defines Sascha Hauer
2023-10-06 17:43 ` Chanwoo Choi
2023-10-16 13:10 ` Sascha Hauer
2023-07-04 9:32 ` [PATCH v7 09/26] PM / devfreq: rockchip-dfi: Clean up DDR type register defines Sascha Hauer
2023-10-06 19:11 ` Chanwoo Choi
2023-10-16 12:03 ` Sascha Hauer
2023-10-17 8:34 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 10/26] PM / devfreq: rockchip-dfi: Add RK3568 support Sascha Hauer
2023-10-06 18:17 ` Chanwoo Choi
2023-10-16 11:34 ` Sascha Hauer
2023-10-17 8:31 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 11/26] PM / devfreq: rockchip-dfi: Handle LPDDR2 correctly Sascha Hauer
2023-10-06 18:24 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 12/26] PM / devfreq: rockchip-dfi: Handle LPDDR4X Sascha Hauer
2023-10-06 18:26 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 13/26] PM / devfreq: rockchip-dfi: Pass private data struct to internal functions Sascha Hauer
2023-10-06 18:28 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 14/26] PM / devfreq: rockchip-dfi: Prepare for multiple users Sascha Hauer
2023-10-06 18:46 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 15/26] PM / devfreq: rockchip-dfi: give variable a better name Sascha Hauer
2023-10-06 18:37 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 16/26] PM / devfreq: rockchip-dfi: Add perf support Sascha Hauer
2023-10-08 21:48 ` Chanwoo Choi
2023-10-16 12:16 ` Sascha Hauer
2023-10-17 8:35 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 17/26] PM / devfreq: rockchip-dfi: make register stride SoC specific Sascha Hauer
2023-10-08 21:57 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 18/26] PM / devfreq: rockchip-dfi: account for multiple DDRMON_CTRL registers Sascha Hauer
2023-10-08 22:19 ` Chanwoo Choi
2023-10-16 12:49 ` Sascha Hauer [this message]
2023-10-17 8:35 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 19/26] PM / devfreq: rockchip-dfi: add support for RK3588 Sascha Hauer
2023-10-08 22:22 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 20/26] dt-bindings: devfreq: event: convert Rockchip DFI binding to yaml Sascha Hauer
2023-10-09 0:40 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 21/26] dt-bindings: devfreq: event: rockchip,dfi: Add rk3568 support Sascha Hauer
2023-10-08 22:24 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 22/26] dt-bindings: devfreq: event: rockchip,dfi: Add rk3588 support Sascha Hauer
2023-10-08 22:24 ` Chanwoo Choi
2023-07-04 9:32 ` [PATCH v7 23/26] dt-bindings: soc: rockchip: grf: add rockchip,rk3588-pmugrf Sascha Hauer
2023-07-04 9:32 ` [PATCH v7 24/26] arm64: dts: rockchip: rk3399: Enable DFI Sascha Hauer
2023-07-04 9:32 ` [PATCH v7 25/26] arm64: dts: rockchip: rk356x: Add DFI Sascha Hauer
2023-07-04 9:32 ` [PATCH v7 26/26] arm64: dts: rockchip: rk3588s: " Sascha Hauer
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231016124903.GC3359458@pengutronix.de \
--to=s.hauer@pengutronix.de \
--cc=Jonathan.Cameron@huawei.com \
--cc=chanwoo@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=heiko@sntech.de \
--cc=kernel@pengutronix.de \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kyungmin.park@samsung.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=mark.rutland@arm.com \
--cc=michael.riesch@wolfvision.net \
--cc=myungjoo.ham@samsung.com \
--cc=robh+dt@kernel.org \
--cc=robin.murphy@arm.com \
--cc=sebastian.reichel@collabora.com \
--cc=vincent.legoll@gmail.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).