From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 743D6CA74 for ; Wed, 18 Oct 2023 07:08:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=none Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [IPv6:2a0a:edc0:2:b01:1d::104]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1A06101 for ; Wed, 18 Oct 2023 00:08:34 -0700 (PDT) Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qt0fP-0007OP-SW; Wed, 18 Oct 2023 09:08:31 +0200 Received: from [2a0a:edc0:2:b01:1d::c0] (helo=ptx.whiteo.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1qt0fO-002Uki-2j; Wed, 18 Oct 2023 09:08:30 +0200 Received: from sha by ptx.whiteo.stw.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1qt0fN-00F2o1-Vu; Wed, 18 Oct 2023 09:08:30 +0200 Date: Wed, 18 Oct 2023 09:08:29 +0200 From: Sascha Hauer To: Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, Mark Rutland , devicetree@vger.kernel.org, Conor Dooley , Krzysztof Kozlowski , linux-pm@vger.kernel.org, Robin Murphy , linux-kernel@vger.kernel.org, Rob Herring , Sebastian Reichel , Chanwoo Choi , Kyungmin Park , MyungJoo Ham , Michael Riesch , Chanwoo Choi , Vincent Legoll , Will Deacon , kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v8 08/26] PM / devfreq: rk3399_dmc, dfi: generalize DDRTYPE defines Message-ID: <20231018070829.GH3359458@pengutronix.de> References: <20231018061714.3553817-1-s.hauer@pengutronix.de> <20231018061714.3553817-9-s.hauer@pengutronix.de> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231018061714.3553817-9-s.hauer@pengutronix.de> X-Sent-From: Pengutronix Hildesheim X-URL: http://www.pengutronix.de/ X-Accept-Language: de,en X-Accept-Content-Type: text/plain User-Agent: Mutt/1.10.1 (2018-07-13) X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Heiko, Could you provide your Ack for this patch? Thanks Sascha On Wed, Oct 18, 2023 at 08:16:56AM +0200, Sascha Hauer wrote: > The DDRTYPE defines are named to be RK3399 specific, but they can be > used for other Rockchip SoCs as well, so replace the RK3399_PMUGRF_ > prefix with ROCKCHIP_. They are defined in a SoC specific header > file, so when generalizing the prefix also move the new defines to > a SoC agnostic header file. While at it use GENMASK to define the > DDRTYPE bitfield and give it a name including the full register name. > > Reviewed-by: Sebastian Reichel > Acked-by: Chanwoo Choi > Signed-off-by: Sascha Hauer > --- > drivers/devfreq/event/rockchip-dfi.c | 9 +++++---- > drivers/devfreq/rk3399_dmc.c | 10 +++++----- > include/soc/rockchip/rk3399_grf.h | 7 +------ > include/soc/rockchip/rockchip_grf.h | 17 +++++++++++++++++ > 4 files changed, 28 insertions(+), 15 deletions(-) > create mode 100644 include/soc/rockchip/rockchip_grf.h > > diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c > index 28c18bbf6baa5..82d18c60538a5 100644 > --- a/drivers/devfreq/event/rockchip-dfi.c > +++ b/drivers/devfreq/event/rockchip-dfi.c > @@ -18,8 +18,10 @@ > #include > #include > #include > +#include > #include > > +#include > #include > > #define DMC_MAX_CHANNELS 2 > @@ -75,9 +77,9 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) > writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); > > /* set ddr type to dfi */ > - if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3) > + if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3) > writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); > - else if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4) > + else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4) > writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); > > /* enable count, use software mode */ > @@ -192,8 +194,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) > > /* get ddr type */ > regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); > - dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & > - RK3399_PMUGRF_DDRTYPE_MASK; > + dfi->ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val); > > dfi->channel_mask = GENMASK(1, 0); > dfi->max_channels = 2; > diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c > index daff407026157..fd2c5ffedf41e 100644 > --- a/drivers/devfreq/rk3399_dmc.c > +++ b/drivers/devfreq/rk3399_dmc.c > @@ -22,6 +22,7 @@ > #include > > #include > +#include > #include > #include > > @@ -381,17 +382,16 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) > } > > regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); > - ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & > - RK3399_PMUGRF_DDRTYPE_MASK; > + ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val); > > switch (ddr_type) { > - case RK3399_PMUGRF_DDRTYPE_DDR3: > + case ROCKCHIP_DDRTYPE_DDR3: > data->odt_dis_freq = data->ddr3_odt_dis_freq; > break; > - case RK3399_PMUGRF_DDRTYPE_LPDDR3: > + case ROCKCHIP_DDRTYPE_LPDDR3: > data->odt_dis_freq = data->lpddr3_odt_dis_freq; > break; > - case RK3399_PMUGRF_DDRTYPE_LPDDR4: > + case ROCKCHIP_DDRTYPE_LPDDR4: > data->odt_dis_freq = data->lpddr4_odt_dis_freq; > break; > default: > diff --git a/include/soc/rockchip/rk3399_grf.h b/include/soc/rockchip/rk3399_grf.h > index 3eebabcb28123..775f8444bea8d 100644 > --- a/include/soc/rockchip/rk3399_grf.h > +++ b/include/soc/rockchip/rk3399_grf.h > @@ -11,11 +11,6 @@ > > /* PMU GRF Registers */ > #define RK3399_PMUGRF_OS_REG2 0x308 > -#define RK3399_PMUGRF_DDRTYPE_SHIFT 13 > -#define RK3399_PMUGRF_DDRTYPE_MASK 7 > -#define RK3399_PMUGRF_DDRTYPE_DDR3 3 > -#define RK3399_PMUGRF_DDRTYPE_LPDDR2 5 > -#define RK3399_PMUGRF_DDRTYPE_LPDDR3 6 > -#define RK3399_PMUGRF_DDRTYPE_LPDDR4 7 > +#define RK3399_PMUGRF_OS_REG2_DDRTYPE GENMASK(15, 13) > > #endif > diff --git a/include/soc/rockchip/rockchip_grf.h b/include/soc/rockchip/rockchip_grf.h > new file mode 100644 > index 0000000000000..dde1a9796ccb5 > --- /dev/null > +++ b/include/soc/rockchip/rockchip_grf.h > @@ -0,0 +1,17 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Rockchip General Register Files definitions > + */ > + > +#ifndef __SOC_ROCKCHIP_GRF_H > +#define __SOC_ROCKCHIP_GRF_H > + > +/* Rockchip DDRTYPE defines */ > +enum { > + ROCKCHIP_DDRTYPE_DDR3 = 3, > + ROCKCHIP_DDRTYPE_LPDDR2 = 5, > + ROCKCHIP_DDRTYPE_LPDDR3 = 6, > + ROCKCHIP_DDRTYPE_LPDDR4 = 7, > +}; > + > +#endif /* __SOC_ROCKCHIP_GRF_H */ > -- > 2.39.2 > > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |