[PATCH v3 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC

Yu Chien Peter Lin
2023-10-22T15:24:30Z

The Andes INTC allows AX45MP cores to handle custom local
interrupts, such as the performance monitor overflow interrupt.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- Fixed possible compatibles for Andes INTC
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 8a726407fb76..dfe27550af11 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -37,7 +37,7 @@ cpu0: cpu@0 {

cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
+ compatible = "andestech,cpu-intc", "riscv,cpu-intc";
interrupt-controller;
};
};
--
2.34.1