[PATCH v3 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string

Yu Chien Peter Lin
2023-10-22T15:24:20Z

Add "andestech,cpu-intc" compatible string which indicates that
Andes specific local interrupt is supported on the core,
e.g. AX45MP cores have 3 types of non-standard local interrupt
can be handled in supervisor mode:

- Slave port ECC error interrupt
- Bus write transaction error interrupt
- Performance monitor overflow interrupt

These interrupts are enabled/disabled via a custom register
SLIE instead of the standard interrupt enable register SIE.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- Updated commit message
- Fixed possible compatibles for Andes INTC
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 97e8441eda1c..4c1bbcf07406 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -99,7 +99,12 @@ properties:
const: 1

compatible:
- const: riscv,cpu-intc
+ oneOf:
+ - items:
+ - enum:
+ - andestech,cpu-intc
+ - const: riscv,cpu-intc
+ - const: riscv,cpu-intc

interrupt-controller: true

--
2.34.1