From: Conor Dooley <conor@kernel.org>
To: Yu Chien Peter Lin <peterlin@andestech.com>
Cc: acme@kernel.org, adrian.hunter@intel.com,
ajones@ventanamicro.com, alexander.shishkin@linux.intel.com,
andre.przywara@arm.com, anup@brainfault.org,
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Subject: Re: [PATCH v3 RESEND 10/13] dt-bindings: riscv: Add Andes PMU extension description
Date: Mon, 23 Oct 2023 13:03:53 +0100 [thread overview]
Message-ID: <20231023-spectacle-module-0516fb35995a@spud> (raw)
In-Reply-To: <20231023004100.2663486-11-peterlin@andestech.com>
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On Mon, Oct 23, 2023 at 08:40:57AM +0800, Yu Chien Peter Lin wrote:
> Document the ISA string for Andes Technology performance monitor
> extension which provides counter overflow interrupt and mode
> filtering mechanisms.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v2 -> v3:
> - New patch
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 5e9291d258d5..e0694e2adbc2 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -246,6 +246,13 @@ properties:
> in commit 2e5236 ("Ztso is now ratified.") of the
> riscv-isa-manual.
>
> + - const: xandespmu
> + description:
> + The Andes Technology performance monitor extension for counter overflow
> + and privilege mode filtering. For more details, see Counter Related
> + Registers in the AX45MP datasheet.
> + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
Does/will this PMU function identically on the other CPUs that support it?
I assume the answer is yes.
Cheers,
Conor.
> +
> - const: xtheadpmu
> description:
> The T-Head performance monitor extension for counter overflow. For more
> --
> 2.34.1
>
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next prev parent reply other threads:[~2023-10-23 12:04 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 0:40 [PATCH v3 RESEND 00/13] Support Andes PMU extension Yu Chien Peter Lin
2023-10-23 0:40 ` [PATCH v3 RESEND 01/13] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-10-23 9:23 ` Conor Dooley
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 02/13] irqchip/riscv-intc: Allow large non-standard hwirq number Yu Chien Peter Lin
2023-10-27 7:12 ` Thomas Gleixner
2023-10-30 7:12 ` Yu-Chien Peter Lin
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 03/13] irqchip/riscv-intc: Introduce Andes IRQ chip Yu Chien Peter Lin
2023-10-27 7:13 ` Thomas Gleixner
2023-10-23 0:40 ` [PATCH v3 RESEND 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-10-23 13:15 ` Conor Dooley
2023-10-26 8:50 ` Yu-Chien Peter Lin
2023-10-23 0:40 ` [PATCH v3 RESEND 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-10-23 0:40 ` [PATCH v3 RESEND 06/13] perf: RISC-V: Eliminate redundant IRQ enable/disable operations Yu Chien Peter Lin
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 07/13] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-10-23 11:56 ` Conor Dooley
2023-10-23 0:40 ` [PATCH v3 RESEND 08/13] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 09/13] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-10-23 12:25 ` Conor Dooley
2023-10-23 0:40 ` [PATCH v3 RESEND 10/13] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-10-23 12:03 ` Conor Dooley [this message]
2023-10-26 8:22 ` Yu-Chien Peter Lin
2023-10-26 14:09 ` Conor Dooley
2023-10-27 7:22 ` Yu-Chien Peter Lin
2023-10-23 0:40 ` [RFC PATCH v3 RESEND 11/13] riscv: dts: allwinner: Add T-Head PMU extension Yu Chien Peter Lin
2023-10-23 0:40 ` [PATCH v3 RESEND 12/13] riscv: dts: renesas: Add Andes " Yu Chien Peter Lin
2023-10-23 0:41 ` [PATCH v3 RESEND 13/13] riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin
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