From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55B42208DA for ; Mon, 23 Oct 2023 17:28:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="cBNptwrt" Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5170910F3 for ; Mon, 23 Oct 2023 10:28:36 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-6bd0e1b1890so2661720b3a.3 for ; Mon, 23 Oct 2023 10:28:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698082115; x=1698686915; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2RNpF/CWjVyq2jAidq9g4JrMuQdRaRtl2xGmvH6ydPA=; b=cBNptwrtDZSMiUgZf9vsibX8GbLSPgcJuMJbwhL0OFH61OXEB7rjqRgvyu/iVoqLI5 R2JnO+0DXpBYoZXZXUtkAKZK+Tv/XlXoMifnlUgtbt4SehdZQNHAjwICffK8kbP3xN7E kir79gwN8g8jBHmz3VqS3M+bVD5HDH9lJWCSbxSt5Wan5jt/d9LPaNbUD9BlPeZVs3mG AlVbTzriSjdFwcRZkbRKf+EwZmuvDBXWwcXnIOV7dbxUQ73R1wRBOBCueYauLNS/kAN+ aLE/8YWLaWt8UAvRFub0U9KKhBWHr0iuPt89wp9K88yJ+0MKuBOzAmZBUdTTDoYYczMX a+YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698082115; x=1698686915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2RNpF/CWjVyq2jAidq9g4JrMuQdRaRtl2xGmvH6ydPA=; b=UmkY5Ss+m+llIXYKuy3rODt+Htc/jj+QQ8B5oLqTuur7BANmb1CU6rP09HQqap+mDQ gV5OFpj0/GVpeUW3XjGZUTm8kaSHeS1aQZnGfF89zuIqlSHIC7PGQbrWRKnYbRdEIMPE oWm67PN74kh3SmwF81toZrIs0Ad0dacqI8m1s3c8Pz0l+hlsfL0BGnK3IjEcXq20Eh4C TXAuWxh5j+2fd9vd8Q+JsxwLYQGqwqgnIR1t2d2yxZBPARlg205b5EuNNgCVImcffqHU x82fD3SWsa3nrf3bpnyn1/FB8CcBQxvmmUIOCurOBEjRxBwdYyms8U/iKrXwnSgLKlSg +0OA== X-Gm-Message-State: AOJu0Ywpk06h+4oHfgpeZHHAS0rzzXq5tBK4L7BzaXWAhFEJEkao6msY 5ZCMGnnZn+rxnfAkIvN9br6U3w== X-Google-Smtp-Source: AGHT+IHZzhWmln5xymK7n5TNPBWqesjYhjRRHleS5bw10ErYzHOB24OJlBMxjJZwp9l07TtUV7pD6Q== X-Received: by 2002:a05:6a00:a0b:b0:6bb:def8:b09c with SMTP id p11-20020a056a000a0b00b006bbdef8b09cmr8323613pfh.1.1698082115306; Mon, 23 Oct 2023 10:28:35 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.9]) by smtp.gmail.com with ESMTPSA id g5-20020aa79f05000000b006be055ab117sm6473194pfr.92.2023.10.23.10.28.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 10:28:34 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v11 05/14] irqchip/riscv-intc: Add support for RISC-V AIA Date: Mon, 23 Oct 2023 22:57:51 +0530 Message-Id: <20231023172800.315343-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com> References: <20231023172800.315343-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The RISC-V advanced interrupt architecture (AIA) extends the per-HART local interrupts in following ways: 1. Minimum 64 local interrupts for both RV32 and RV64 2. Ability to process multiple pending local interrupts in same interrupt handler 3. Priority configuration for each local interrupts 4. Special CSRs to configure/access the per-HART MSI controller We add support for #1 and #2 described above in the RISC-V intc driver. Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-intc.c | 34 ++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index e8d01b14ccdd..bab536bbaf2c 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include #include #include +#include static struct irq_domain *intc_domain; @@ -30,6 +31,15 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) generic_handle_domain_irq(intc_domain, cause); } +static asmlinkage void riscv_intc_aia_irq(struct pt_regs *regs) +{ + unsigned long topi; + + while ((topi = csr_read(CSR_TOPI))) + generic_handle_domain_irq(intc_domain, + topi >> TOPI_IID_SHIFT); +} + /* * On RISC-V systems local interrupts are masked or unmasked by writing * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written @@ -39,12 +49,18 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) static void riscv_intc_irq_mask(struct irq_data *d) { - csr_clear(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) + csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_clear(CSR_IE, BIT(d->hwirq)); } static void riscv_intc_irq_unmask(struct irq_data *d) { - csr_set(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) + csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_set(CSR_IE, BIT(d->hwirq)); } static void riscv_intc_irq_eoi(struct irq_data *d) @@ -115,16 +131,20 @@ static struct fwnode_handle *riscv_intc_hwnode(void) static int __init riscv_intc_init_common(struct fwnode_handle *fn) { - int rc; + int rc, nr_irqs = riscv_isa_extension_available(NULL, SxAIA) ? + 64 : BITS_PER_LONG; - intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG, + intc_domain = irq_domain_create_linear(fn, nr_irqs, &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; } - rc = set_handle_irq(&riscv_intc_irq); + if (riscv_isa_extension_available(NULL, SxAIA)) + rc = set_handle_irq(&riscv_intc_aia_irq); + else + rc = set_handle_irq(&riscv_intc_irq); if (rc) { pr_err("failed to set irq handler\n"); return rc; @@ -132,7 +152,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) riscv_set_intc_hwnode_fn(riscv_intc_hwnode); - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); + pr_info("%d local interrupts mapped%s\n", + nr_irqs, riscv_isa_extension_available(NULL, SxAIA) ? + " using AIA" : ""); return 0; } -- 2.34.1